include/opcode/ppc.h

   1 /* ppc.h -- Header file for PowerPC opcode table
   2    Copyright 1994, 1995, 1999, 2000, 2001 Free Software Foundation, Inc.
   3    Written by Ian Lance Taylor, Cygnus Support
   4
   5 This file is part of GDB, GAS, and the GNU binutils.
   6
   7 GDB, GAS, and the GNU binutils are free software; you can redistribute
   8 them and/or modify them under the terms of the GNU General Public
   9 License as published by the Free Software Foundation; either version
  10 1, or (at your option) any later version.
  11
  12 GDB, GAS, and the GNU binutils are distributed in the hope that they
  13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15 the GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this file; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef PPC_H
  22 #define PPC_H
  23
  24 /* The opcode table is an array of struct powerpc_opcode.  */
  25
  26 struct powerpc_opcode
  27 {
  28   /* The opcode name.  */
  29   const char *name;
  30
  31   /* The opcode itself.  Those bits which will be filled in with
  32      operands are zeroes.  */
  33   unsigned long opcode;
  34
  35   /* The opcode mask.  This is used by the disassembler.  This is a
  36      mask containing ones indicating those bits which must match the
  37      opcode field, and zeroes indicating those bits which need not
  38      match (and are presumably filled in by operands).  */
  39   unsigned long mask;
  40
  41   /* One bit flags for the opcode.  These are used to indicate which
  42      specific processors support the instructions.  The defined values
  43      are listed below.  */
  44   unsigned long flags;
  45
  46   /* An array of operand codes.  Each code is an index into the
  47      operand table.  They appear in the order which the operands must
  48      appear in assembly code, and are terminated by a zero.  */
  49   unsigned char operands[8];
  50 };
  51
  52 /* The table itself is sorted by major opcode number, and is otherwise
  53    in the order in which the disassembler should consider
  54    instructions.  */
  55 extern const struct powerpc_opcode powerpc_opcodes[];
  56 extern const int powerpc_num_opcodes;
  57
  58 /* Values defined for the flags field of a struct powerpc_opcode.  */
  59
  60 /* Opcode is defined for the PowerPC architecture.  */
  61 #define PPC_OPCODE_PPC (01)
  62
  63 /* Opcode is defined for the POWER (RS/6000) architecture.  */
  64 #define PPC_OPCODE_POWER (02)
  65
  66 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
  67 #define PPC_OPCODE_POWER2 (04)
  68
  69 /* Opcode is only defined on 32 bit architectures.  */
  70 #define PPC_OPCODE_32 (010)
  71
  72 /* Opcode is only defined on 64 bit architectures.  */
  73 #define PPC_OPCODE_64 (020)
  74
  75 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
  76    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
  77    but it also supports many additional POWER instructions.  */
  78 #define PPC_OPCODE_601 (040)
  79
  80 /* Opcode is supported in both the Power and PowerPC architectures
  81    (ie, compiler's -mcpu=common or assembler's -mcom).  */
  82 #define PPC_OPCODE_COMMON (0100)
  83
  84 /* Opcode is supported for any Power or PowerPC platform (this is
  85    for the assembler's -many option, and it eliminates duplicates).  */
  86 #define PPC_OPCODE_ANY (0200)
  87
  88 /* Opcode is supported as part of the 64-bit bridge.  */
  89 #define PPC_OPCODE_64_BRIDGE (0400)
  90
  91 /* Opcode is supported by Altivec Vector Unit */
  92 #define PPC_OPCODE_ALTIVEC (01000)
  93
  94 /* Opcode is supported by PowerPC 403 processor.  */
  95 #define PPC_OPCODE_403 (02000)
  96
  97 /* Opcode is supported by Motorola BookE processor.  */
  98 #define PPC_OPCODE_BOOKE (04000)
  99
 100 /* Opcode is only supported by 64-bit Motorola BookE processor.  */
 101 #define PPC_OPCODE_BOOKE64 (010000)
 102
 103 /* A macro to extract the major opcode from an instruction.  */
 104 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 105 \f
 106 /* The operands table is an array of struct powerpc_operand.  */
 107
 108 struct powerpc_operand
 109 {
 110   /* The number of bits in the operand.  */
 111   int bits;
 112
 113   /* How far the operand is left shifted in the instruction.  */
 114   int shift;
 115
 116   /* Insertion function.  This is used by the assembler.  To insert an
 117      operand value into an instruction, check this field.
 118
 119      If it is NULL, execute
 120          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 121      (i is the instruction which we are filling in, o is a pointer to
 122      this structure, and op is the opcode value; this assumes twos
 123      complement arithmetic).
 124
 125      If this field is not NULL, then simply call it with the
 126      instruction and the operand value.  It will return the new value
 127      of the instruction.  If the ERRMSG argument is not NULL, then if
 128      the operand value is illegal, *ERRMSG will be set to a warning
 129      string (the operand will be inserted in any case).  If the
 130      operand value is legal, *ERRMSG will be unchanged (most operands
 131      can accept any value).  */
 132   unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
 133                                    const char **errmsg));
 134
 135   /* Extraction function.  This is used by the disassembler.  To
 136      extract this operand type from an instruction, check this field.
 137
 138      If it is NULL, compute
 139          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 140          if ((o->flags & PPC_OPERAND_SIGNED) != 0
 141              && (op & (1 << (o->bits - 1))) != 0)
 142            op -= 1 << o->bits;
 143      (i is the instruction, o is a pointer to this structure, and op
 144      is the result; this assumes twos complement arithmetic).
 145
 146      If this field is not NULL, then simply call it with the
 147      instruction value.  It will return the value of the operand.  If
 148      the INVALID argument is not NULL, *INVALID will be set to
 149      non-zero if this operand type can not actually be extracted from
 150      this operand (i.e., the instruction does not match).  If the
 151      operand is valid, *INVALID will not be changed.  */
 152   long (*extract) PARAMS ((unsigned long instruction, int *invalid));
 153
 154   /* One bit syntax flags.  */
 155   unsigned long flags;
 156 };
 157
 158 /* Elements in the table are retrieved by indexing with values from
 159    the operands field of the powerpc_opcodes table.  */
 160
 161 extern const struct powerpc_operand powerpc_operands[];
 162
 163 /* Values defined for the flags field of a struct powerpc_operand.  */
 164
 165 /* This operand takes signed values.  */
 166 #define PPC_OPERAND_SIGNED (01)
 167
 168 /* This operand takes signed values, but also accepts a full positive
 169    range of values when running in 32 bit mode.  That is, if bits is
 170    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
 171    this flag is ignored.  */
 172 #define PPC_OPERAND_SIGNOPT (02)
 173
 174 /* This operand does not actually exist in the assembler input.  This
 175    is used to support extended mnemonics such as mr, for which two
 176    operands fields are identical.  The assembler should call the
 177    insert function with any op value.  The disassembler should call
 178    the extract function, ignore the return value, and check the value
 179    placed in the valid argument.  */
 180 #define PPC_OPERAND_FAKE (04)
 181
 182 /* The next operand should be wrapped in parentheses rather than
 183    separated from this one by a comma.  This is used for the load and
 184    store instructions which want their operands to look like
 185        reg,displacement(reg)
 186    */
 187 #define PPC_OPERAND_PARENS (010)
 188
 189 /* This operand may use the symbolic names for the CR fields, which
 190    are
 191        lt  0    gt  1   eq  2   so  3   un  3
 192        cr0 0    cr1 1   cr2 2   cr3 3
 193        cr4 4    cr5 5   cr6 6   cr7 7
 194    These may be combined arithmetically, as in cr2*4+gt.  These are
 195    only supported on the PowerPC, not the POWER.  */
 196 #define PPC_OPERAND_CR (020)
 197
 198 /* This operand names a register.  The disassembler uses this to print
 199    register names with a leading 'r'.  */
 200 #define PPC_OPERAND_GPR (040)
 201
 202 /* This operand names a floating point register.  The disassembler
 203    prints these with a leading 'f'.  */
 204 #define PPC_OPERAND_FPR (0100)
 205
 206 /* This operand is a relative branch displacement.  The disassembler
 207    prints these symbolically if possible.  */
 208 #define PPC_OPERAND_RELATIVE (0200)
 209
 210 /* This operand is an absolute branch address.  The disassembler
 211    prints these symbolically if possible.  */
 212 #define PPC_OPERAND_ABSOLUTE (0400)
 213
 214 /* This operand is optional, and is zero if omitted.  This is used for
 215    the optional BF and L fields in the comparison instructions.  The
 216    assembler must count the number of operands remaining on the line,
 217    and the number of operands remaining for the opcode, and decide
 218    whether this operand is present or not.  The disassembler should
 219    print this operand out only if it is not zero.  */
 220 #define PPC_OPERAND_OPTIONAL (01000)
 221
 222 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
 223    is omitted, then for the next operand use this operand value plus
 224    1, ignoring the next operand field for the opcode.  This wretched
 225    hack is needed because the Power rotate instructions can take
 226    either 4 or 5 operands.  The disassembler should print this operand
 227    out regardless of the PPC_OPERAND_OPTIONAL field.  */
 228 #define PPC_OPERAND_NEXT (02000)
 229
 230 /* This operand should be regarded as a negative number for the
 231    purposes of overflow checking (i.e., the normal most negative
 232    number is disallowed and one more than the normal most positive
 233    number is allowed).  This flag will only be set for a signed
 234    operand.  */
 235 #define PPC_OPERAND_NEGATIVE (04000)
 236
 237 /* This operand names a vector unit register.  The disassembler
 238    prints these with a leading 'v'.  */
 239 #define PPC_OPERAND_VR (010000)
 240
 241 /* This operand is for the DS field in a DS form instruction.  */
 242 #define PPC_OPERAND_DS (020000)
 243 \f
 244 /* The POWER and PowerPC assemblers use a few macros.  We keep them
 245    with the operands table for simplicity.  The macro table is an
 246    array of struct powerpc_macro.  */
 247
 248 struct powerpc_macro
 249 {
 250   /* The macro name.  */
 251   const char *name;
 252
 253   /* The number of operands the macro takes.  */
 254   unsigned int operands;
 255
 256   /* One bit flags for the opcode.  These are used to indicate which
 257      specific processors support the instructions.  The values are the
 258      same as those for the struct powerpc_opcode flags field.  */
 259   unsigned long flags;
 260
 261   /* A format string to turn the macro into a normal instruction.
 262      Each %N in the string is replaced with operand number N (zero
 263      based).  */
 264   const char *format;
 265 };
 266
 267 extern const struct powerpc_macro powerpc_macros[];
 268 extern const int powerpc_num_macros;
 269
 270 #endif /* PPC_H */