include/pcmcia.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _PCMCIA_H
   9 #define _PCMCIA_H
  10
  11 #include <common.h>
  12 #include <config.h>
  13
  14 /*
  15  * Allow configuration to select PCMCIA slot,
  16  * or try to generate a useful default
  17  */
  18 #if defined(CONFIG_CMD_PCMCIA) || \
  19     (defined(CONFIG_CMD_IDE) && \
  20         (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
  21
  22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  23
  24 #if defined(CONFIG_TQM8xxL)
  25 # define        CONFIG_PCMCIA_SLOT_B    /* The TQM8xxL use SLOT_B       */
  26 #elif defined(CONFIG_SPD823TS)          /* The SPD8xx  use SLOT_B       */
  27 # define CONFIG_PCMCIA_SLOT_B
  28 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)   /* The IVM* use SLOT_A  */
  29 # define CONFIG_PCMCIA_SLOT_A
  30 #elif defined(CONFIG_LWMON)             /* The LWMON  use SLOT_B        */
  31 # define CONFIG_PCMCIA_SLOT_B
  32 #elif defined(CONFIG_ICU862)            /* The ICU862 use SLOT_B        */
  33 # define CONFIG_PCMCIA_SLOT_B
  34 #elif defined(CONFIG_R360MPI)           /* The R360MPI use SLOT_B       */
  35 # define CONFIG_PCMCIA_SLOT_B
  36 #elif defined(CONFIG_ATC)               /* The ATC use SLOT_A   */
  37 # define CONFIG_PCMCIA_SLOT_A
  38 #elif defined(CONFIG_UC100)             /* The UC100 use SLOT_B         */
  39 # define CONFIG_PCMCIA_SLOT_B
  40 #else
  41 # error "PCMCIA Slot not configured"
  42 #endif
  43
  44 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
  45
  46 /* Make sure exactly one slot is defined - we support only one for now */
  47 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
  48 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
  49 #endif
  50 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
  51 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
  52 #endif
  53
  54 #ifndef PCMCIA_SOCKETS_NO
  55 #define PCMCIA_SOCKETS_NO       1
  56 #endif
  57 #ifndef PCMCIA_MEM_WIN_NO
  58 #define PCMCIA_MEM_WIN_NO       4
  59 #endif
  60 #define PCMCIA_IO_WIN_NO        2
  61
  62 /* define _slot_ to be able to optimize macros */
  63 #ifdef CONFIG_PCMCIA_SLOT_A
  64 # define _slot_                 0
  65 # define PCMCIA_SLOT_MSG        "slot A"
  66 # define PCMCIA_SLOT_x          PCMCIA_PSLOT_A
  67 #else
  68 # define _slot_                 1
  69 # define PCMCIA_SLOT_MSG        "slot B"
  70 # define PCMCIA_SLOT_x          PCMCIA_PSLOT_B
  71 #endif
  72
  73 /*
  74  * The TQM850L hardware has two pins swapped! Grrrrgh!
  75  */
  76 #ifdef  CONFIG_TQM850L
  77 #define __MY_PCMCIA_GCRX_CXRESET        PCMCIA_GCRX_CXOE
  78 #define __MY_PCMCIA_GCRX_CXOE           PCMCIA_GCRX_CXRESET
  79 #else
  80 #define __MY_PCMCIA_GCRX_CXRESET        PCMCIA_GCRX_CXRESET
  81 #define __MY_PCMCIA_GCRX_CXOE           PCMCIA_GCRX_CXOE
  82 #endif
  83
  84 /*
  85  * This structure is used to address each window in the PCMCIA controller.
  86  *
  87  * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
  88  * after pcmcia_win_t[n]...
  89  */
  90
  91 typedef struct {
  92         ulong   br;
  93         ulong   or;
  94 } pcmcia_win_t;
  95
  96 /*
  97  * Definitions for PCMCIA control registers to operate in IDE mode
  98  *
  99  * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
 100  * to be done later (depending on CPU clock)
 101  */
 102
 103 /* Window 0:
 104  *      Base: 0xFE100000        CS1
 105  *      Port Size:     2 Bytes
 106  *      Port Size:    16 Bit
 107  *      Common Memory Space
 108  */
 109
 110 #define CONFIG_SYS_PCMCIA_PBR0          0xFE100000
 111 #define CONFIG_SYS_PCMCIA_POR0      (   PCMCIA_BSIZE_2  \
 112                             |   PCMCIA_PPS_16   \
 113                             |   PCMCIA_PRS_MEM  \
 114                             |   PCMCIA_SLOT_x   \
 115                             |   PCMCIA_PV       \
 116                             )
 117
 118 /* Window 1:
 119  *      Base: 0xFE100080        CS1
 120  *      Port Size:     8 Bytes
 121  *      Port Size:     8 Bit
 122  *      Common Memory Space
 123  */
 124
 125 #define CONFIG_SYS_PCMCIA_PBR1          0xFE100080
 126 #define CONFIG_SYS_PCMCIA_POR1      (   PCMCIA_BSIZE_8  \
 127                             |   PCMCIA_PPS_8    \
 128                             |   PCMCIA_PRS_MEM  \
 129                             |   PCMCIA_SLOT_x   \
 130                             |   PCMCIA_PV       \
 131                             )
 132
 133 /* Window 2:
 134  *      Base: 0xFE100100        CS2
 135  *      Port Size:     8 Bytes
 136  *      Port Size:     8 Bit
 137  *      Common Memory Space
 138  */
 139
 140 #define CONFIG_SYS_PCMCIA_PBR2          0xFE100100
 141 #define CONFIG_SYS_PCMCIA_POR2      (   PCMCIA_BSIZE_8  \
 142                             |   PCMCIA_PPS_8    \
 143                             |   PCMCIA_PRS_MEM  \
 144                             |   PCMCIA_SLOT_x   \
 145                             |   PCMCIA_PV       \
 146                             )
 147
 148 /* Window 3:
 149  *      not used
 150  */
 151 #define CONFIG_SYS_PCMCIA_PBR3          0
 152 #define CONFIG_SYS_PCMCIA_POR3          0
 153
 154 /* Window 4:
 155  *      Base: 0xFE100C00        CS1
 156  *      Port Size:     2 Bytes
 157  *      Port Size:    16 Bit
 158  *      Common Memory Space
 159  */
 160
 161 #define CONFIG_SYS_PCMCIA_PBR4          0xFE100C00
 162 #define CONFIG_SYS_PCMCIA_POR4      (   PCMCIA_BSIZE_2  \
 163                             |   PCMCIA_PPS_16   \
 164                             |   PCMCIA_PRS_MEM  \
 165                             |   PCMCIA_SLOT_x   \
 166                             |   PCMCIA_PV       \
 167                             )
 168
 169 /* Window 5:
 170  *      Base: 0xFE100C80        CS1
 171  *      Port Size:     8 Bytes
 172  *      Port Size:     8 Bit
 173  *      Common Memory Space
 174  */
 175
 176 #define CONFIG_SYS_PCMCIA_PBR5          0xFE100C80
 177 #define CONFIG_SYS_PCMCIA_POR5      (   PCMCIA_BSIZE_8  \
 178                             |   PCMCIA_PPS_8    \
 179                             |   PCMCIA_PRS_MEM  \
 180                             |   PCMCIA_SLOT_x   \
 181                             |   PCMCIA_PV       \
 182                             )
 183
 184 /* Window 6:
 185  *      Base: 0xFE100D00        CS2
 186  *      Port Size:     8 Bytes
 187  *      Port Size:     8 Bit
 188  *      Common Memory Space
 189  */
 190
 191 #define CONFIG_SYS_PCMCIA_PBR6          0xFE100D00
 192 #define CONFIG_SYS_PCMCIA_POR6      (   PCMCIA_BSIZE_8  \
 193                             |   PCMCIA_PPS_8    \
 194                             |   PCMCIA_PRS_MEM  \
 195                             |   PCMCIA_SLOT_x   \
 196                             |   PCMCIA_PV       \
 197                             )
 198
 199 /* Window 7:
 200  *      not used
 201  */
 202 #define CONFIG_SYS_PCMCIA_PBR7          0
 203 #define CONFIG_SYS_PCMCIA_POR7          0
 204
 205 /**********************************************************************/
 206
 207 /*
 208  * CIS Tupel codes
 209  */
 210 #define CISTPL_NULL             0x00
 211 #define CISTPL_DEVICE           0x01
 212 #define CISTPL_LONGLINK_CB      0x02
 213 #define CISTPL_INDIRECT         0x03
 214 #define CISTPL_CONFIG_CB        0x04
 215 #define CISTPL_CFTABLE_ENTRY_CB 0x05
 216 #define CISTPL_LONGLINK_MFC     0x06
 217 #define CISTPL_BAR              0x07
 218 #define CISTPL_PWR_MGMNT        0x08
 219 #define CISTPL_EXTDEVICE        0x09
 220 #define CISTPL_CHECKSUM         0x10
 221 #define CISTPL_LONGLINK_A       0x11
 222 #define CISTPL_LONGLINK_C       0x12
 223 #define CISTPL_LINKTARGET       0x13
 224 #define CISTPL_NO_LINK          0x14
 225 #define CISTPL_VERS_1           0x15
 226 #define CISTPL_ALTSTR           0x16
 227 #define CISTPL_DEVICE_A         0x17
 228 #define CISTPL_JEDEC_C          0x18
 229 #define CISTPL_JEDEC_A          0x19
 230 #define CISTPL_CONFIG           0x1a
 231 #define CISTPL_CFTABLE_ENTRY    0x1b
 232 #define CISTPL_DEVICE_OC        0x1c
 233 #define CISTPL_DEVICE_OA        0x1d
 234 #define CISTPL_DEVICE_GEO       0x1e
 235 #define CISTPL_DEVICE_GEO_A     0x1f
 236 #define CISTPL_MANFID           0x20
 237 #define CISTPL_FUNCID           0x21
 238 #define CISTPL_FUNCE            0x22
 239 #define CISTPL_SWIL             0x23
 240 #define CISTPL_END              0xff
 241
 242 /*
 243  * CIS Function ID codes
 244  */
 245 #define CISTPL_FUNCID_MULTI     0x00
 246 #define CISTPL_FUNCID_MEMORY    0x01
 247 #define CISTPL_FUNCID_SERIAL    0x02
 248 #define CISTPL_FUNCID_PARALLEL  0x03
 249 #define CISTPL_FUNCID_FIXED     0x04
 250 #define CISTPL_FUNCID_VIDEO     0x05
 251 #define CISTPL_FUNCID_NETWORK   0x06
 252 #define CISTPL_FUNCID_AIMS      0x07
 253 #define CISTPL_FUNCID_SCSI      0x08
 254
 255 /*
 256  * Fixed Disk FUNCE codes
 257  */
 258 #define CISTPL_IDE_INTERFACE    0x01
 259
 260 #define CISTPL_FUNCE_IDE_IFACE  0x01
 261 #define CISTPL_FUNCE_IDE_MASTER 0x02
 262 #define CISTPL_FUNCE_IDE_SLAVE  0x03
 263
 264 /* First feature byte */
 265 #define CISTPL_IDE_SILICON      0x04
 266 #define CISTPL_IDE_UNIQUE       0x08
 267 #define CISTPL_IDE_DUAL         0x10
 268
 269 /* Second feature byte */
 270 #define CISTPL_IDE_HAS_SLEEP    0x01
 271 #define CISTPL_IDE_HAS_STANDBY  0x02
 272 #define CISTPL_IDE_HAS_IDLE     0x04
 273 #define CISTPL_IDE_LOW_POWER    0x08
 274 #define CISTPL_IDE_REG_INHIBIT  0x10
 275 #define CISTPL_IDE_HAS_INDEX    0x20
 276 #define CISTPL_IDE_IOIS16       0x40
 277
 278 #endif
 279
 280 #ifdef  CONFIG_8xx
 281 extern u_int *pcmcia_pgcrx[];
 282 #define PCMCIA_PGCRX(slot)      (*pcmcia_pgcrx[slot])
 283 #endif
 284
 285 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
 286 extern int check_ide_device(int slot);
 287 #endif
 288
 289 #endif /* _PCMCIA_H */