include/ppc405.h

   1 /*----------------------------------------------------------------------------+
   2 |
   3 |       This source code has been made available to you by IBM on an AS-IS
   4 |       basis.  Anyone receiving this source is licensed under IBM
   5 |       copyrights to use it in any way he or she deems fit, including
   6 |       copying it, modifying it, compiling it, and redistributing it either
   7 |       with or without modifications.  No license under IBM patents or
   8 |       patent applications is to be implied by the copyright license.
   9 |
  10 |       Any user of this software should understand that IBM cannot provide
  11 |       technical support for this software and will not be responsible for
  12 |       any consequences resulting from the use of this software.
  13 |
  14 |       Any person who transfers this source code or any derivative work
  15 |       must include the IBM copyright notice, this paragraph, and the
  16 |       preceding two paragraphs in the transferred software.
  17 |
  18 |       COPYRIGHT   I B M   CORPORATION 1999
  19 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20 +----------------------------------------------------------------------------*/
  21
  22 #ifndef __PPC405_H__
  23 #define __PPC405_H__
  24
  25 /* Define bits and masks for real-mode storage attribute control registers */
  26 #define PPC_128MB_SACR_BIT(addr)        ((addr) >> 27)
  27 #define PPC_128MB_SACR_VALUE(addr)      PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
  28
  29 #ifndef CONFIG_IOP480
  30 #define CONFIG_SYS_DCACHE_SIZE          (16 << 10)      /* For AMCC 405 CPUs    */
  31 #else
  32 #define CONFIG_SYS_DCACHE_SIZE          (2 << 10)       /* For PLX IOP480 (403) */
  33 #endif
  34
  35 /*--------------------------------------------------------------------- */
  36 /* Special Purpose Registers                                            */
  37 /*--------------------------------------------------------------------- */
  38         #define  srr2  0x3de      /* save/restore register 2 */
  39         #define  srr3  0x3df      /* save/restore register 3 */
  40
  41         /*
  42          * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
  43          * exception for the exact same purposes - let's alias them and have a
  44          * common handling in crit_return() and CRIT_EXCEPTION
  45          */
  46         #define  csrr0 srr2
  47         #define  csrr1 srr3
  48
  49         #define  dbsr  0x3f0      /* debug status register */
  50         #define  dbcr0 0x3f2      /* debug control register 0 */
  51         #define  dbcr1 0x3bd      /* debug control register 1 */
  52         #define  iac1  0x3f4      /* instruction address comparator 1 */
  53         #define  iac2  0x3f5      /* instruction address comparator 2 */
  54         #define  iac3  0x3b4      /* instruction address comparator 3 */
  55         #define  iac4  0x3b5      /* instruction address comparator 4 */
  56         #define  dac1  0x3f6      /* data address comparator 1 */
  57         #define  dac2  0x3f7      /* data address comparator 2 */
  58         #define  dccr  0x3fa      /* data cache control register */
  59         #define  iccr  0x3fb      /* instruction cache control register */
  60         #define  esr   0x3d4      /* execption syndrome register */
  61         #define  dear  0x3d5      /* data exeption address register */
  62         #define  evpr  0x3d6      /* exeption vector prefix register */
  63         #define  tsr   0x3d8      /* timer status register */
  64         #define  tcr   0x3da      /* timer control register */
  65         #define  pit   0x3db      /* programmable interval timer */
  66         #define  sgr   0x3b9      /* storage guarded reg      */
  67         #define  dcwr  0x3ba      /* data cache write-thru reg*/
  68         #define  sler  0x3bb      /* storage little-endian reg */
  69         #define  cdbcr 0x3d7      /* cache debug cntrl reg    */
  70         #define  icdbdr 0x3d3     /* instr cache dbug data reg*/
  71         #define  ccr0  0x3b3      /* core configuration register */
  72         #define  dvc1  0x3b6      /* data value compare register 1 */
  73         #define  dvc2  0x3b7      /* data value compare register 2 */
  74         #define  pid   0x3b1      /* process ID */
  75         #define  su0r  0x3bc      /* storage user-defined register 0 */
  76         #define  zpr   0x3b0      /* zone protection regsiter */
  77
  78         #define  tbl   0x11c      /* time base lower - privileged write */
  79         #define  tbu   0x11d      /* time base upper - privileged write */
  80
  81         #define  sprg4r 0x104     /* Special purpose general 4 - read only */
  82         #define  sprg5r 0x105     /* Special purpose general 5 - read only */
  83         #define  sprg6r 0x106     /* Special purpose general 6 - read only */
  84         #define  sprg7r 0x107     /* Special purpose general 7 - read only */
  85         #define  sprg4w 0x114     /* Special purpose general 4 - write only */
  86         #define  sprg5w 0x115     /* Special purpose general 5 - write only */
  87         #define  sprg6w 0x116     /* Special purpose general 6 - write only */
  88         #define  sprg7w 0x117     /* Special purpose general 7 - write only */
  89
  90 /******************************************************************************
  91  * Special for PPC405GP
  92  ******************************************************************************/
  93
  94 /******************************************************************************
  95  * DMA
  96  ******************************************************************************/
  97 #define DMA_DCR_BASE 0x100
  98 #define dmacr0  (DMA_DCR_BASE+0x00)  /* DMA channel control register 0       */
  99 #define dmact0  (DMA_DCR_BASE+0x01)  /* DMA count register 0                 */
 100 #define dmada0  (DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
 101 #define dmasa0  (DMA_DCR_BASE+0x03)  /* DMA source address register 0        */
 102 #define dmasb0  (DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
 103 #define dmacr1  (DMA_DCR_BASE+0x08)  /* DMA channel control register 1       */
 104 #define dmact1  (DMA_DCR_BASE+0x09)  /* DMA count register 1                 */
 105 #define dmada1  (DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
 106 #define dmasa1  (DMA_DCR_BASE+0x0b)  /* DMA source address register 1        */
 107 #define dmasb1  (DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
 108 #define dmacr2  (DMA_DCR_BASE+0x10)  /* DMA channel control register 2       */
 109 #define dmact2  (DMA_DCR_BASE+0x11)  /* DMA count register 2                 */
 110 #define dmada2  (DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
 111 #define dmasa2  (DMA_DCR_BASE+0x13)  /* DMA source address register 2        */
 112 #define dmasb2  (DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
 113 #define dmacr3  (DMA_DCR_BASE+0x18)  /* DMA channel control register 3       */
 114 #define dmact3  (DMA_DCR_BASE+0x19)  /* DMA count register 3                 */
 115 #define dmada3  (DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
 116 #define dmasa3  (DMA_DCR_BASE+0x1b)  /* DMA source address register 3        */
 117 #define dmasb3  (DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
 118 #define dmasr   (DMA_DCR_BASE+0x20)  /* DMA status register                  */
 119 #define dmasgc  (DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
 120 #define dmaadr  (DMA_DCR_BASE+0x24)  /* DMA address decode register          */
 121
 122 #ifndef CONFIG_405EP
 123 /******************************************************************************
 124  * Decompression Controller
 125  ******************************************************************************/
 126 #define DECOMP_DCR_BASE 0x14
 127 #define kiar  (DECOMP_DCR_BASE+0x0)  /* Decompression controller addr reg    */
 128 #define kidr  (DECOMP_DCR_BASE+0x1)  /* Decompression controller data reg    */
 129   /* values for kiar register - indirect addressing of these regs */
 130   #define kitor0      0x00    /* index table origin register 0        */
 131   #define kitor1      0x01    /* index table origin register 1        */
 132   #define kitor2      0x02    /* index table origin register 2        */
 133   #define kitor3      0x03    /* index table origin register 3        */
 134   #define kaddr0      0x04    /* address decode definition regsiter 0 */
 135   #define kaddr1      0x05    /* address decode definition regsiter 1 */
 136   #define kconf       0x40    /* decompression core config register   */
 137   #define kid         0x41    /* decompression core ID     register   */
 138   #define kver        0x42    /* decompression core version # reg     */
 139   #define kpear       0x50    /* bus error addr reg (PLB addr)        */
 140   #define kbear       0x51    /* bus error addr reg (DCP to EBIU addr)*/
 141   #define kesr0       0x52    /* bus error status reg 0  (R/clear)    */
 142   #define kesr0s      0x53    /* bus error status reg 0  (set)        */
 143   /* There are 0x400 of the following registers, from krom0 to krom3ff*/
 144   /* Only the first one is given here.                                */
 145   #define krom0      0x400    /* SRAM/ROM read/write                  */
 146 #endif
 147
 148 /******************************************************************************
 149  * Power Management
 150  ******************************************************************************/
 151 #ifdef CONFIG_405EX
 152 #define POWERMAN_DCR_BASE 0xb0
 153 #else
 154 #define POWERMAN_DCR_BASE 0xb8
 155 #endif
 156 #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status             */
 157 #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable             */
 158 #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force              */
 159
 160 /******************************************************************************
 161  * Extrnal Bus Controller
 162  ******************************************************************************/
 163   /* values for ebccfga register - indirect addressing of these regs */
 164   #define pb0cr       0x00    /* periph bank 0 config reg            */
 165   #define pb1cr       0x01    /* periph bank 1 config reg            */
 166   #define pb2cr       0x02    /* periph bank 2 config reg            */
 167   #define pb3cr       0x03    /* periph bank 3 config reg            */
 168   #define pb4cr       0x04    /* periph bank 4 config reg            */
 169 #ifndef CONFIG_405EP
 170   #define pb5cr       0x05    /* periph bank 5 config reg            */
 171   #define pb6cr       0x06    /* periph bank 6 config reg            */
 172   #define pb7cr       0x07    /* periph bank 7 config reg            */
 173 #endif
 174   #define pb0ap       0x10    /* periph bank 0 access parameters     */
 175   #define pb1ap       0x11    /* periph bank 1 access parameters     */
 176   #define pb2ap       0x12    /* periph bank 2 access parameters     */
 177   #define pb3ap       0x13    /* periph bank 3 access parameters     */
 178   #define pb4ap       0x14    /* periph bank 4 access parameters     */
 179 #ifndef CONFIG_405EP
 180   #define pb5ap       0x15    /* periph bank 5 access parameters     */
 181   #define pb6ap       0x16    /* periph bank 6 access parameters     */
 182   #define pb7ap       0x17    /* periph bank 7 access parameters     */
 183 #endif
 184   #define pbear       0x20    /* periph bus error addr reg           */
 185   #define pbesr0      0x21    /* periph bus error status reg 0       */
 186   #define pbesr1      0x22    /* periph bus error status reg 1       */
 187   #define epcr        0x23    /* external periph control reg         */
 188 #define EBC0_CFG        0x23    /* external bus configuration reg       */
 189
 190 #ifdef CONFIG_405EP
 191 /******************************************************************************
 192  * Control
 193  ******************************************************************************/
 194 #define CNTRL_DCR_BASE 0x0f0
 195 #define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0                */
 196 #define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register               */
 197 #define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register        */
 198 #define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1                */
 199 #define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register               */
 200 #define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register                */
 201
 202 #define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register          */
 203 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
 204 #define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
 205 #define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
 206 #define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register          */
 207 #define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register        */
 208 #define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register          */
 209 #define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register             */
 210 #define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                    */
 211 #define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register         */
 212
 213 /* Bit definitions */
 214 #define PLLMR0_CPU_DIV_MASK      0x00300000     /* CPU clock divider */
 215 #define PLLMR0_CPU_DIV_BYPASS    0x00000000
 216 #define PLLMR0_CPU_DIV_2         0x00100000
 217 #define PLLMR0_CPU_DIV_3         0x00200000
 218 #define PLLMR0_CPU_DIV_4         0x00300000
 219
 220 #define PLLMR0_CPU_TO_PLB_MASK   0x00030000     /* CPU:PLB Frequency Divisor */
 221 #define PLLMR0_CPU_PLB_DIV_1     0x00000000
 222 #define PLLMR0_CPU_PLB_DIV_2     0x00010000
 223 #define PLLMR0_CPU_PLB_DIV_3     0x00020000
 224 #define PLLMR0_CPU_PLB_DIV_4     0x00030000
 225
 226 #define PLLMR0_OPB_TO_PLB_MASK   0x00003000     /* OPB:PLB Frequency Divisor */
 227 #define PLLMR0_OPB_PLB_DIV_1     0x00000000
 228 #define PLLMR0_OPB_PLB_DIV_2     0x00001000
 229 #define PLLMR0_OPB_PLB_DIV_3     0x00002000
 230 #define PLLMR0_OPB_PLB_DIV_4     0x00003000
 231
 232 #define PLLMR0_EXB_TO_PLB_MASK   0x00000300     /* External Bus:PLB Divisor  */
 233 #define PLLMR0_EXB_PLB_DIV_2     0x00000000
 234 #define PLLMR0_EXB_PLB_DIV_3     0x00000100
 235 #define PLLMR0_EXB_PLB_DIV_4     0x00000200
 236 #define PLLMR0_EXB_PLB_DIV_5     0x00000300
 237
 238 #define PLLMR0_MAL_TO_PLB_MASK   0x00000030     /* MAL:PLB Divisor  */
 239 #define PLLMR0_MAL_PLB_DIV_1     0x00000000
 240 #define PLLMR0_MAL_PLB_DIV_2     0x00000010
 241 #define PLLMR0_MAL_PLB_DIV_3     0x00000020
 242 #define PLLMR0_MAL_PLB_DIV_4     0x00000030
 243
 244 #define PLLMR0_PCI_TO_PLB_MASK   0x00000003     /* PCI:PLB Frequency Divisor */
 245 #define PLLMR0_PCI_PLB_DIV_1     0x00000000
 246 #define PLLMR0_PCI_PLB_DIV_2     0x00000001
 247 #define PLLMR0_PCI_PLB_DIV_3     0x00000002
 248 #define PLLMR0_PCI_PLB_DIV_4     0x00000003
 249
 250 #define PLLMR1_SSCS_MASK         0x80000000     /* Select system clock source */
 251 #define PLLMR1_PLLR_MASK         0x40000000     /* PLL reset */
 252 #define PLLMR1_FBMUL_MASK        0x00F00000     /* PLL feedback multiplier value */
 253 #define PLLMR1_FBMUL_DIV_16      0x00000000
 254 #define PLLMR1_FBMUL_DIV_1       0x00100000
 255 #define PLLMR1_FBMUL_DIV_2       0x00200000
 256 #define PLLMR1_FBMUL_DIV_3       0x00300000
 257 #define PLLMR1_FBMUL_DIV_4       0x00400000
 258 #define PLLMR1_FBMUL_DIV_5       0x00500000
 259 #define PLLMR1_FBMUL_DIV_6       0x00600000
 260 #define PLLMR1_FBMUL_DIV_7       0x00700000
 261 #define PLLMR1_FBMUL_DIV_8       0x00800000
 262 #define PLLMR1_FBMUL_DIV_9       0x00900000
 263 #define PLLMR1_FBMUL_DIV_10      0x00A00000
 264 #define PLLMR1_FBMUL_DIV_11      0x00B00000
 265 #define PLLMR1_FBMUL_DIV_12      0x00C00000
 266 #define PLLMR1_FBMUL_DIV_13      0x00D00000
 267 #define PLLMR1_FBMUL_DIV_14      0x00E00000
 268 #define PLLMR1_FBMUL_DIV_15      0x00F00000
 269
 270 #define PLLMR1_FWDVA_MASK        0x00070000     /* PLL forward divider A value */
 271 #define PLLMR1_FWDVA_DIV_8       0x00000000
 272 #define PLLMR1_FWDVA_DIV_7       0x00010000
 273 #define PLLMR1_FWDVA_DIV_6       0x00020000
 274 #define PLLMR1_FWDVA_DIV_5       0x00030000
 275 #define PLLMR1_FWDVA_DIV_4       0x00040000
 276 #define PLLMR1_FWDVA_DIV_3       0x00050000
 277 #define PLLMR1_FWDVA_DIV_2       0x00060000
 278 #define PLLMR1_FWDVA_DIV_1       0x00070000
 279 #define PLLMR1_FWDVB_MASK        0x00007000     /* PLL forward divider B value */
 280 #define PLLMR1_TUNING_MASK       0x000003FF     /* PLL tune bits */
 281
 282 /* Defines for CPC0_EPRCSR register */
 283 #define CPC0_EPRCSR_E0NFE          0x80000000
 284 #define CPC0_EPRCSR_E1NFE          0x40000000
 285 #define CPC0_EPRCSR_E1RPP          0x00000080
 286 #define CPC0_EPRCSR_E0RPP          0x00000040
 287 #define CPC0_EPRCSR_E1ERP          0x00000020
 288 #define CPC0_EPRCSR_E0ERP          0x00000010
 289 #define CPC0_EPRCSR_E1PCI          0x00000002
 290 #define CPC0_EPRCSR_E0PCI          0x00000001
 291
 292 /* Defines for CPC0_PCI Register */
 293 #define CPC0_PCI_SPE                       0x00000010 /* PCIINT/WE select       */
 294 #define CPC0_PCI_HOST_CFG_EN               0x00000008 /* PCI host config Enable */
 295 #define CPC0_PCI_ARBIT_EN                  0x00000001 /* PCI Internal Arb Enabled*/
 296
 297 /* Defines for CPC0_BOOR Register */
 298 #define CPC0_BOOT_SEP                      0x00000002 /* serial EEPROM present  */
 299
 300 /* Defines for CPC0_PLLMR1 Register fields */
 301 #define PLL_ACTIVE                 0x80000000
 302 #define CPC0_PLLMR1_SSCS           0x80000000
 303 #define PLL_RESET                  0x40000000
 304 #define CPC0_PLLMR1_PLLR           0x40000000
 305     /* Feedback multiplier */
 306 #define PLL_FBKDIV                 0x00F00000
 307 #define CPC0_PLLMR1_FBDV           0x00F00000
 308 #define PLL_FBKDIV_16              0x00000000
 309 #define PLL_FBKDIV_1               0x00100000
 310 #define PLL_FBKDIV_2               0x00200000
 311 #define PLL_FBKDIV_3               0x00300000
 312 #define PLL_FBKDIV_4               0x00400000
 313 #define PLL_FBKDIV_5               0x00500000
 314 #define PLL_FBKDIV_6               0x00600000
 315 #define PLL_FBKDIV_7               0x00700000
 316 #define PLL_FBKDIV_8               0x00800000
 317 #define PLL_FBKDIV_9               0x00900000
 318 #define PLL_FBKDIV_10              0x00A00000
 319 #define PLL_FBKDIV_11              0x00B00000
 320 #define PLL_FBKDIV_12              0x00C00000
 321 #define PLL_FBKDIV_13              0x00D00000
 322 #define PLL_FBKDIV_14              0x00E00000
 323 #define PLL_FBKDIV_15              0x00F00000
 324     /* Forward A divisor */
 325 #define PLL_FWDDIVA                0x00070000
 326 #define CPC0_PLLMR1_FWDVA          0x00070000
 327 #define PLL_FWDDIVA_8              0x00000000
 328 #define PLL_FWDDIVA_7              0x00010000
 329 #define PLL_FWDDIVA_6              0x00020000
 330 #define PLL_FWDDIVA_5              0x00030000
 331 #define PLL_FWDDIVA_4              0x00040000
 332 #define PLL_FWDDIVA_3              0x00050000
 333 #define PLL_FWDDIVA_2              0x00060000
 334 #define PLL_FWDDIVA_1              0x00070000
 335     /* Forward B divisor */
 336 #define PLL_FWDDIVB                0x00007000
 337 #define CPC0_PLLMR1_FWDVB          0x00007000
 338 #define PLL_FWDDIVB_8              0x00000000
 339 #define PLL_FWDDIVB_7              0x00001000
 340 #define PLL_FWDDIVB_6              0x00002000
 341 #define PLL_FWDDIVB_5              0x00003000
 342 #define PLL_FWDDIVB_4              0x00004000
 343 #define PLL_FWDDIVB_3              0x00005000
 344 #define PLL_FWDDIVB_2              0x00006000
 345 #define PLL_FWDDIVB_1              0x00007000
 346     /* PLL tune bits */
 347 #define PLL_TUNE_MASK            0x000003FF
 348 #define PLL_TUNE_2_M_3           0x00000133     /*  2 <= M <= 3               */
 349 #define PLL_TUNE_4_M_6           0x00000134     /*  3 <  M <= 6               */
 350 #define PLL_TUNE_7_M_10          0x00000138     /*  6 <  M <= 10              */
 351 #define PLL_TUNE_11_M_14         0x0000013C     /* 10 <  M <= 14              */
 352 #define PLL_TUNE_15_M_40         0x0000023E     /* 14 <  M <= 40              */
 353 #define PLL_TUNE_VCO_LOW         0x00000000     /* 500MHz <= VCO <=  800MHz   */
 354 #define PLL_TUNE_VCO_HI          0x00000080     /* 800MHz <  VCO <= 1000MHz   */
 355
 356 /* Defines for CPC0_PLLMR0 Register fields */
 357     /* CPU divisor */
 358 #define PLL_CPUDIV                 0x00300000
 359 #define CPC0_PLLMR0_CCDV           0x00300000
 360 #define PLL_CPUDIV_1               0x00000000
 361 #define PLL_CPUDIV_2               0x00100000
 362 #define PLL_CPUDIV_3               0x00200000
 363 #define PLL_CPUDIV_4               0x00300000
 364     /* PLB divisor */
 365 #define PLL_PLBDIV                 0x00030000
 366 #define CPC0_PLLMR0_CBDV           0x00030000
 367 #define PLL_PLBDIV_1               0x00000000
 368 #define PLL_PLBDIV_2               0x00010000
 369 #define PLL_PLBDIV_3               0x00020000
 370 #define PLL_PLBDIV_4               0x00030000
 371     /* OPB divisor */
 372 #define PLL_OPBDIV                 0x00003000
 373 #define CPC0_PLLMR0_OPDV           0x00003000
 374 #define PLL_OPBDIV_1               0x00000000
 375 #define PLL_OPBDIV_2               0x00001000
 376 #define PLL_OPBDIV_3               0x00002000
 377 #define PLL_OPBDIV_4               0x00003000
 378     /* EBC divisor */
 379 #define PLL_EXTBUSDIV              0x00000300
 380 #define CPC0_PLLMR0_EPDV           0x00000300
 381 #define PLL_EXTBUSDIV_2            0x00000000
 382 #define PLL_EXTBUSDIV_3            0x00000100
 383 #define PLL_EXTBUSDIV_4            0x00000200
 384 #define PLL_EXTBUSDIV_5            0x00000300
 385     /* MAL divisor */
 386 #define PLL_MALDIV                 0x00000030
 387 #define CPC0_PLLMR0_MPDV           0x00000030
 388 #define PLL_MALDIV_1               0x00000000
 389 #define PLL_MALDIV_2               0x00000010
 390 #define PLL_MALDIV_3               0x00000020
 391 #define PLL_MALDIV_4               0x00000030
 392     /* PCI divisor */
 393 #define PLL_PCIDIV                 0x00000003
 394 #define CPC0_PLLMR0_PPFD           0x00000003
 395 #define PLL_PCIDIV_1               0x00000000
 396 #define PLL_PCIDIV_2               0x00000001
 397 #define PLL_PCIDIV_3               0x00000002
 398 #define PLL_PCIDIV_4               0x00000003
 399
 400 /*
 401  *-------------------------------------------------------------------------------
 402  * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
 403  * assuming a 33.3MHz input clock to the 405EP.
 404  *-------------------------------------------------------------------------------
 405  */
 406 #define PLLMR0_266_133_66  (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 407                             PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
 408                             PLL_MALDIV_1 | PLL_PCIDIV_4)
 409 #define PLLMR1_266_133_66  (PLL_FBKDIV_8  |  \
 410                             PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 411                             PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 412
 413 #define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 414                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 415                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 416 #define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
 417                               PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
 418                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 419 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 420                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 421                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 422 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
 423                               PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 424                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 425 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 426                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 427                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 428 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
 429                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 430                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 431 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 |  \
 432                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
 433                               PLL_MALDIV_1 | PLL_PCIDIV_2)
 434 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8  |  \
 435                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 436                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 437 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
 438                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
 439                               PLL_MALDIV_1 | PLL_PCIDIV_3)
 440 #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
 441                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 442                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 443 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
 444                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
 445                               PLL_MALDIV_1 | PLL_PCIDIV_1)
 446 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
 447                               PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 448                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 449
 450 /*
 451  * PLL Voltage Controlled Oscillator (VCO) definitions
 452  * Maximum and minimum values (in MHz) for correct PLL operation.
 453  */
 454 #define VCO_MIN     500
 455 #define VCO_MAX     1000
 456 #elif defined(CONFIG_405EZ)
 457 #define sdrnand0        0x4000
 458 #define sdrultra0       0x4040
 459 #define sdrultra1       0x4050
 460 #define sdricintstat    0x4510
 461
 462 #define SDR_NAND0_NDEN          0x80000000
 463 #define SDR_NAND0_NDBTEN        0x40000000
 464 #define SDR_NAND0_NDBADR_MASK   0x30000000
 465 #define SDR_NAND0_NDBPG_MASK    0x0f000000
 466 #define SDR_NAND0_NDAREN        0x00800000
 467 #define SDR_NAND0_NDRBEN        0x00400000
 468
 469 #define SDR_ULTRA0_NDGPIOBP     0x80000000
 470 #define SDR_ULTRA0_CSN_MASK     0x78000000
 471 #define SDR_ULTRA0_CSNSEL0      0x40000000
 472 #define SDR_ULTRA0_CSNSEL1      0x20000000
 473 #define SDR_ULTRA0_CSNSEL2      0x10000000
 474 #define SDR_ULTRA0_CSNSEL3      0x08000000
 475 #define SDR_ULTRA0_EBCRDYEN     0x04000000
 476 #define SDR_ULTRA0_SPISSINEN    0x02000000
 477 #define SDR_ULTRA0_NFSRSTEN     0x01000000
 478
 479 #define SDR_ULTRA1_LEDNENABLE   0x40000000
 480
 481 #define SDR_ICRX_STAT   0x80000000
 482 #define SDR_ICTX0_STAT  0x40000000
 483 #define SDR_ICTX1_STAT  0x20000000
 484
 485 #define SDR_PINSTP      0x40
 486
 487 /******************************************************************************
 488  * Control
 489  ******************************************************************************/
 490 /* CPR Registers */
 491 #define cprclkupd       0x020           /* CPR_CLKUPD */
 492 #define cprpllc         0x040           /* CPR_PLLC */
 493 #define cprplld         0x060           /* CPR_PLLD */
 494 #define cprprimad       0x080           /* CPR_PRIMAD */
 495 #define cprperd0        0x0e0           /* CPR_PERD0 */
 496 #define cprperd1        0x0e1           /* CPR_PERD1 */
 497 #define cprperc0        0x180           /* CPR_PERC0 */
 498 #define cprmisc0        0x181           /* CPR_MISC0 */
 499 #define cprmisc1        0x182           /* CPR_MISC1 */
 500
 501 #define CPR_CLKUPD_ENPLLCH_EN  0x40000000     /* Enable CPR PLL Changes */
 502 #define CPR_CLKUPD_ENDVCH_EN   0x20000000     /* Enable CPR Sys. Div. Changes */
 503 #define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */
 504
 505 #define PLLC_SRC_MASK          0x20000000     /* PLL feedback source */
 506
 507 #define PLLD_FBDV_MASK         0x1F000000     /* PLL feedback divider value */
 508 #define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
 509 #define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */
 510
 511 #define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */
 512 #define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */
 513 #define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */
 514 #define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */
 515
 516 #define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */
 517 #define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */
 518 #define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */
 519 #define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */
 520
 521 #else /* #ifdef CONFIG_405EP */
 522 /******************************************************************************
 523  * Control
 524  ******************************************************************************/
 525 #define CNTRL_DCR_BASE 0x0b0
 526 #define pllmd   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register                  */
 527 #define cntrl0  (CNTRL_DCR_BASE+0x1)  /* Control 0 register                  */
 528 #define cntrl1  (CNTRL_DCR_BASE+0x2)  /* Control 1 register                  */
 529 #define reset   (CNTRL_DCR_BASE+0x3)  /* reset register                      */
 530 #define strap   (CNTRL_DCR_BASE+0x4)  /* strap register                      */
 531
 532 #define CPC0_CR0  (CNTRL_DCR_BASE+0x1)  /* chip control register 0           */
 533 #define CPC0_CR1  (CNTRL_DCR_BASE+0x2)  /* chip control register 1           */
 534 #define CPC0_PSR  (CNTRL_DCR_BASE+0x4)  /* chip pin strapping register       */
 535
 536 /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
 537 #define CPC0_EIRR (CNTRL_DCR_BASE+0x6)  /* external interrupt routing register */
 538 #define CPC0_ECR  (0xaa)                /* edge conditioner register */
 539
 540 #define ecr     (0xaa)                /* edge conditioner register (405gpr)  */
 541
 542 /* Bit definitions */
 543 #define PLLMR_FWD_DIV_MASK      0xE0000000     /* Forward Divisor */
 544 #define PLLMR_FWD_DIV_BYPASS    0xE0000000
 545 #define PLLMR_FWD_DIV_3         0xA0000000
 546 #define PLLMR_FWD_DIV_4         0x80000000
 547 #define PLLMR_FWD_DIV_6         0x40000000
 548
 549 #define PLLMR_FB_DIV_MASK       0x1E000000     /* Feedback Divisor */
 550 #define PLLMR_FB_DIV_1          0x02000000
 551 #define PLLMR_FB_DIV_2          0x04000000
 552 #define PLLMR_FB_DIV_3          0x06000000
 553 #define PLLMR_FB_DIV_4          0x08000000
 554
 555 #define PLLMR_TUNING_MASK       0x01F80000
 556
 557 #define PLLMR_CPU_TO_PLB_MASK   0x00060000     /* CPU:PLB Frequency Divisor */
 558 #define PLLMR_CPU_PLB_DIV_1     0x00000000
 559 #define PLLMR_CPU_PLB_DIV_2     0x00020000
 560 #define PLLMR_CPU_PLB_DIV_3     0x00040000
 561 #define PLLMR_CPU_PLB_DIV_4     0x00060000
 562
 563 #define PLLMR_OPB_TO_PLB_MASK   0x00018000     /* OPB:PLB Frequency Divisor */
 564 #define PLLMR_OPB_PLB_DIV_1     0x00000000
 565 #define PLLMR_OPB_PLB_DIV_2     0x00008000
 566 #define PLLMR_OPB_PLB_DIV_3     0x00010000
 567 #define PLLMR_OPB_PLB_DIV_4     0x00018000
 568
 569 #define PLLMR_PCI_TO_PLB_MASK   0x00006000     /* PCI:PLB Frequency Divisor */
 570 #define PLLMR_PCI_PLB_DIV_1     0x00000000
 571 #define PLLMR_PCI_PLB_DIV_2     0x00002000
 572 #define PLLMR_PCI_PLB_DIV_3     0x00004000
 573 #define PLLMR_PCI_PLB_DIV_4     0x00006000
 574
 575 #define PLLMR_EXB_TO_PLB_MASK   0x00001800     /* External Bus:PLB Divisor  */
 576 #define PLLMR_EXB_PLB_DIV_2     0x00000000
 577 #define PLLMR_EXB_PLB_DIV_3     0x00000800
 578 #define PLLMR_EXB_PLB_DIV_4     0x00001000
 579 #define PLLMR_EXB_PLB_DIV_5     0x00001800
 580
 581 /* definitions for PPC405GPr (new mode strapping) */
 582 #define PLLMR_FWDB_DIV_MASK     0x00000007     /* Forward Divisor B */
 583
 584 #define PSR_PLL_FWD_MASK        0xC0000000
 585 #define PSR_PLL_FDBACK_MASK     0x30000000
 586 #define PSR_PLL_TUNING_MASK     0x0E000000
 587 #define PSR_PLB_CPU_MASK        0x01800000
 588 #define PSR_OPB_PLB_MASK        0x00600000
 589 #define PSR_PCI_PLB_MASK        0x00180000
 590 #define PSR_EB_PLB_MASK         0x00060000
 591 #define PSR_ROM_WIDTH_MASK      0x00018000
 592 #define PSR_ROM_LOC             0x00004000
 593 #define PSR_PCI_ASYNC_EN        0x00001000
 594 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800     /* PPC405GPr only */
 595 #define PSR_PCI_ARBIT_EN        0x00000400
 596 #define PSR_NEW_MODE_EN         0x00000020     /* PPC405GPr only */
 597
 598 #ifndef CONFIG_IOP480
 599 /*
 600  * PLL Voltage Controlled Oscillator (VCO) definitions
 601  * Maximum and minimum values (in MHz) for correct PLL operation.
 602  */
 603 #define VCO_MIN     400
 604 #define VCO_MAX     800
 605 #endif /* #ifndef CONFIG_IOP480 */
 606 #endif /* #ifdef CONFIG_405EP */
 607
 608 /******************************************************************************
 609  * Memory Access Layer
 610  ******************************************************************************/
 611 #if defined(CONFIG_405EZ)
 612 #define MAL_DCR_BASE    0x380
 613 #define malmcr          (MAL_DCR_BASE+0x00)     /* MAL Config reg             */
 614 #define malesr          (MAL_DCR_BASE+0x01)     /* Err Status reg (Read/Clear)*/
 615 #define malier          (MAL_DCR_BASE+0x02)     /* Interrupt enable reg       */
 616 #define maldbr          (MAL_DCR_BASE+0x03)     /* Mal Debug reg (Read only)  */
 617 #define maltxcasr       (MAL_DCR_BASE+0x04)     /* TX Channel active reg (set)*/
 618 #define maltxcarr       (MAL_DCR_BASE+0x05)     /* TX Channel active reg (Reset)     */
 619 #define maltxeobisr     (MAL_DCR_BASE+0x06)     /* TX End of buffer int status reg   */
 620 #define maltxdeir       (MAL_DCR_BASE+0x07)     /* TX Descr. Error Int reg    */
 621 /*                                    0x08-0x0F    Reserved                   */
 622 #define malrxcasr       (MAL_DCR_BASE+0x10)     /* RX Channel active reg (set)*/
 623 #define malrxcarr       (MAL_DCR_BASE+0x11)     /* RX Channel active reg (Reset)     */
 624 #define malrxeobisr     (MAL_DCR_BASE+0x12)     /* RX End of buffer int status reg   */
 625 #define malrxdeir       (MAL_DCR_BASE+0x13)     /* RX Descr. Error Int reg  */
 626 /*                                    0x14-0x1F    Reserved                 */
 627 #define maltxctp0r      (MAL_DCR_BASE+0x20)  /* TX 0 Channel table ptr reg  */
 628 #define maltxctp1r      (MAL_DCR_BASE+0x21)  /* TX 1 Channel table ptr reg  */
 629 #define maltxctp2r      (MAL_DCR_BASE+0x22)  /* TX 2 Channel table ptr reg  */
 630 #define maltxctp3r      (MAL_DCR_BASE+0x23)  /* TX 3 Channel table ptr reg  */
 631 #define maltxctp4r      (MAL_DCR_BASE+0x24)  /* TX 4 Channel table ptr reg  */
 632 #define maltxctp5r      (MAL_DCR_BASE+0x25)  /* TX 5 Channel table ptr reg  */
 633 #define maltxctp6r      (MAL_DCR_BASE+0x26)  /* TX 6 Channel table ptr reg  */
 634 #define maltxctp7r      (MAL_DCR_BASE+0x27)  /* TX 7 Channel table ptr reg  */
 635 #define maltxctp8r      (MAL_DCR_BASE+0x28)  /* TX 8 Channel table ptr reg  */
 636 #define maltxctp9r      (MAL_DCR_BASE+0x29)  /* TX 9 Channel table ptr reg  */
 637 #define maltxctp10r     (MAL_DCR_BASE+0x2A)  /* TX 10 Channel table ptr reg */
 638 #define maltxctp11r     (MAL_DCR_BASE+0x2B)  /* TX 11 Channel table ptr reg */
 639 #define maltxctp12r     (MAL_DCR_BASE+0x2C)  /* TX 12 Channel table ptr reg */
 640 #define maltxctp13r     (MAL_DCR_BASE+0x2D)  /* TX 13 Channel table ptr reg */
 641 #define maltxctp14r     (MAL_DCR_BASE+0x2E)  /* TX 14 Channel table ptr reg */
 642 #define maltxctp15r     (MAL_DCR_BASE+0x2F)  /* TX 15 Channel table ptr reg */
 643 #define maltxctp16r     (MAL_DCR_BASE+0x30)  /* TX 16 Channel table ptr reg */
 644 #define maltxctp17r     (MAL_DCR_BASE+0x31)  /* TX 17 Channel table ptr reg */
 645 #define maltxctp18r     (MAL_DCR_BASE+0x32)  /* TX 18 Channel table ptr reg */
 646 #define maltxctp19r     (MAL_DCR_BASE+0x33)  /* TX 19 Channel table ptr reg */
 647 #define maltxctp20r     (MAL_DCR_BASE+0x34)  /* TX 20 Channel table ptr reg */
 648 #define maltxctp21r     (MAL_DCR_BASE+0x35)  /* TX 21 Channel table ptr reg */
 649 #define maltxctp22r     (MAL_DCR_BASE+0x36)  /* TX 22 Channel table ptr reg */
 650 #define maltxctp23r     (MAL_DCR_BASE+0x37)  /* TX 23 Channel table ptr reg */
 651 #define maltxctp24r     (MAL_DCR_BASE+0x38)  /* TX 24 Channel table ptr reg */
 652 #define maltxctp25r     (MAL_DCR_BASE+0x39)  /* TX 25 Channel table ptr reg */
 653 #define maltxctp26r     (MAL_DCR_BASE+0x3A)  /* TX 26 Channel table ptr reg */
 654 #define maltxctp27r     (MAL_DCR_BASE+0x3B)  /* TX 27 Channel table ptr reg */
 655 #define maltxctp28r     (MAL_DCR_BASE+0x3C)  /* TX 28 Channel table ptr reg */
 656 #define maltxctp29r     (MAL_DCR_BASE+0x3D)  /* TX 29 Channel table ptr reg */
 657 #define maltxctp30r     (MAL_DCR_BASE+0x3E)  /* TX 30 Channel table ptr reg */
 658 #define maltxctp31r     (MAL_DCR_BASE+0x3F)  /* TX 31 Channel table ptr reg */
 659 #define malrxctp0r      (MAL_DCR_BASE+0x40)  /* RX 0 Channel table ptr reg  */
 660 #define malrxctp1r      (MAL_DCR_BASE+0x41)  /* RX 1 Channel table ptr reg  */
 661 #define malrxctp2r      (MAL_DCR_BASE+0x42)  /* RX 2 Channel table ptr reg  */
 662 #define malrxctp3r      (MAL_DCR_BASE+0x43)  /* RX 3 Channel table ptr reg  */
 663 #define malrxctp4r      (MAL_DCR_BASE+0x44)  /* RX 4 Channel table ptr reg  */
 664 #define malrxctp5r      (MAL_DCR_BASE+0x45)  /* RX 5 Channel table ptr reg  */
 665 #define malrxctp6r      (MAL_DCR_BASE+0x46)  /* RX 6 Channel table ptr reg  */
 666 #define malrxctp7r      (MAL_DCR_BASE+0x47)  /* RX 7 Channel table ptr reg  */
 667 #define malrxctp8r      (MAL_DCR_BASE+0x48)  /* RX 8 Channel table ptr reg  */
 668 #define malrxctp9r      (MAL_DCR_BASE+0x49)  /* RX 9 Channel table ptr reg  */
 669 #define malrxctp10r     (MAL_DCR_BASE+0x4A)  /* RX 10 Channel table ptr reg */
 670 #define malrxctp11r     (MAL_DCR_BASE+0x4B)  /* RX 11 Channel table ptr reg */
 671 #define malrxctp12r     (MAL_DCR_BASE+0x4C)  /* RX 12 Channel table ptr reg */
 672 #define malrxctp13r     (MAL_DCR_BASE+0x4D)  /* RX 13 Channel table ptr reg */
 673 #define malrxctp14r     (MAL_DCR_BASE+0x4E)  /* RX 14 Channel table ptr reg */
 674 #define malrxctp15r     (MAL_DCR_BASE+0x4F)  /* RX 15 Channel table ptr reg */
 675 #define malrxctp16r     (MAL_DCR_BASE+0x50)  /* RX 16 Channel table ptr reg */
 676 #define malrxctp17r     (MAL_DCR_BASE+0x51)  /* RX 17 Channel table ptr reg */
 677 #define malrxctp18r     (MAL_DCR_BASE+0x52)  /* RX 18 Channel table ptr reg */
 678 #define malrxctp19r     (MAL_DCR_BASE+0x53)  /* RX 19 Channel table ptr reg */
 679 #define malrxctp20r     (MAL_DCR_BASE+0x54)  /* RX 20 Channel table ptr reg */
 680 #define malrxctp21r     (MAL_DCR_BASE+0x55)  /* RX 21 Channel table ptr reg */
 681 #define malrxctp22r     (MAL_DCR_BASE+0x56)  /* RX 22 Channel table ptr reg */
 682 #define malrxctp23r     (MAL_DCR_BASE+0x57)  /* RX 23 Channel table ptr reg */
 683 #define malrxctp24r     (MAL_DCR_BASE+0x58)  /* RX 24 Channel table ptr reg */
 684 #define malrxctp25r     (MAL_DCR_BASE+0x59)  /* RX 25 Channel table ptr reg */
 685 #define malrxctp26r     (MAL_DCR_BASE+0x5A)  /* RX 26 Channel table ptr reg */
 686 #define malrxctp27r     (MAL_DCR_BASE+0x5B)  /* RX 27 Channel table ptr reg */
 687 #define malrxctp28r     (MAL_DCR_BASE+0x5C)  /* RX 28 Channel table ptr reg */
 688 #define malrxctp29r     (MAL_DCR_BASE+0x5D)  /* RX 29 Channel table ptr reg */
 689 #define malrxctp30r     (MAL_DCR_BASE+0x5E)  /* RX 30 Channel table ptr reg */
 690 #define malrxctp31r     (MAL_DCR_BASE+0x5F)  /* RX 31 Channel table ptr reg */
 691 #define malrcbs0        (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg */
 692 #define malrcbs1        (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg */
 693 #define malrcbs2        (MAL_DCR_BASE+0x62)  /* RX 2 Channel buffer size reg */
 694 #define malrcbs3        (MAL_DCR_BASE+0x63)  /* RX 3 Channel buffer size reg */
 695 #define malrcbs4        (MAL_DCR_BASE+0x64)  /* RX 4 Channel buffer size reg */
 696 #define malrcbs5        (MAL_DCR_BASE+0x65)  /* RX 5 Channel buffer size reg */
 697 #define malrcbs6        (MAL_DCR_BASE+0x66)  /* RX 6 Channel buffer size reg */
 698 #define malrcbs7        (MAL_DCR_BASE+0x67)  /* RX 7 Channel buffer size reg */
 699 #define malrcbs8        (MAL_DCR_BASE+0x68)  /* RX 8 Channel buffer size reg */
 700 #define malrcbs9        (MAL_DCR_BASE+0x69)  /* RX 9 Channel buffer size reg */
 701 #define malrcbs10       (MAL_DCR_BASE+0x6A)  /* RX 10 Channel buffer size reg */
 702 #define malrcbs11       (MAL_DCR_BASE+0x6B)  /* RX 11 Channel buffer size reg */
 703 #define malrcbs12       (MAL_DCR_BASE+0x6C)  /* RX 12 Channel buffer size reg */
 704 #define malrcbs13       (MAL_DCR_BASE+0x6D)  /* RX 13 Channel buffer size reg */
 705 #define malrcbs14       (MAL_DCR_BASE+0x6E)  /* RX 14 Channel buffer size reg */
 706 #define malrcbs15       (MAL_DCR_BASE+0x6F)  /* RX 15 Channel buffer size reg */
 707 #define malrcbs16       (MAL_DCR_BASE+0x70)  /* RX 16 Channel buffer size reg */
 708 #define malrcbs17       (MAL_DCR_BASE+0x71)  /* RX 17 Channel buffer size reg */
 709 #define malrcbs18       (MAL_DCR_BASE+0x72)  /* RX 18 Channel buffer size reg */
 710 #define malrcbs19       (MAL_DCR_BASE+0x73)  /* RX 19 Channel buffer size reg */
 711 #define malrcbs20       (MAL_DCR_BASE+0x74)  /* RX 20 Channel buffer size reg */
 712 #define malrcbs21       (MAL_DCR_BASE+0x75)  /* RX 21 Channel buffer size reg */
 713 #define malrcbs22       (MAL_DCR_BASE+0x76)  /* RX 22 Channel buffer size reg */
 714 #define malrcbs23       (MAL_DCR_BASE+0x77)  /* RX 23 Channel buffer size reg */
 715 #define malrcbs24       (MAL_DCR_BASE+0x78)  /* RX 24 Channel buffer size reg */
 716 #define malrcbs25       (MAL_DCR_BASE+0x79)  /* RX 25 Channel buffer size reg */
 717 #define malrcbs26       (MAL_DCR_BASE+0x7A)  /* RX 26 Channel buffer size reg */
 718 #define malrcbs27       (MAL_DCR_BASE+0x7B)  /* RX 27 Channel buffer size reg */
 719 #define malrcbs28       (MAL_DCR_BASE+0x7C)  /* RX 28 Channel buffer size reg */
 720 #define malrcbs29       (MAL_DCR_BASE+0x7D)  /* RX 29 Channel buffer size reg */
 721 #define malrcbs30       (MAL_DCR_BASE+0x7E)  /* RX 30 Channel buffer size reg */
 722 #define malrcbs31       (MAL_DCR_BASE+0x7F)  /* RX 31 Channel buffer size reg */
 723
 724 #else /* !defined(CONFIG_405EZ) */
 725
 726 #define MAL_DCR_BASE 0x180
 727 #define malmcr  (MAL_DCR_BASE+0x00)  /* MAL Config reg                       */
 728 #define malesr  (MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)        */
 729 #define malier  (MAL_DCR_BASE+0x02)  /* Interrupt enable reg                 */
 730 #define maldbr  (MAL_DCR_BASE+0x03)  /* Mal Debug reg (Read only)            */
 731 #define maltxcasr  (MAL_DCR_BASE+0x04)  /* TX Channel active reg (set)       */
 732 #define maltxcarr  (MAL_DCR_BASE+0x05)  /* TX Channel active reg (Reset)     */
 733 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg   */
 734 #define maltxdeir  (MAL_DCR_BASE+0x07)  /* TX Descr. Error Int reg           */
 735 #define malrxcasr  (MAL_DCR_BASE+0x10)  /* RX Channel active reg (set)       */
 736 #define malrxcarr  (MAL_DCR_BASE+0x11)  /* RX Channel active reg (Reset)     */
 737 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg   */
 738 #define malrxdeir  (MAL_DCR_BASE+0x13)  /* RX Descr. Error Int reg           */
 739 #define maltxctp0r (MAL_DCR_BASE+0x20)  /* TX 0 Channel table pointer reg    */
 740 #define maltxctp1r (MAL_DCR_BASE+0x21)  /* TX 1 Channel table pointer reg    */
 741 #define maltxctp2r (MAL_DCR_BASE+0x22)  /* TX 2 Channel table pointer reg    */
 742 #define malrxctp0r (MAL_DCR_BASE+0x40)  /* RX 0 Channel table pointer reg    */
 743 #define malrxctp1r (MAL_DCR_BASE+0x41)  /* RX 1 Channel table pointer reg    */
 744 #define malrcbs0   (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg      */
 745 #define malrcbs1   (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg      */
 746 #endif /* defined(CONFIG_405EZ) */
 747
 748 /*-----------------------------------------------------------------------------
 749 | IIC Register Offsets
 750 '----------------------------------------------------------------------------*/
 751 #define    IICMDBUF         0x00
 752 #define    IICSDBUF         0x02
 753 #define    IICLMADR         0x04
 754 #define    IICHMADR         0x05
 755 #define    IICCNTL          0x06
 756 #define    IICMDCNTL        0x07
 757 #define    IICSTS           0x08
 758 #define    IICEXTSTS        0x09
 759 #define    IICLSADR         0x0A
 760 #define    IICHSADR         0x0B
 761 #define    IICCLKDIV        0x0C
 762 #define    IICINTRMSK       0x0D
 763 #define    IICXFRCNT        0x0E
 764 #define    IICXTCNTLSS      0x0F
 765 #define    IICDIRECTCNTL    0x10
 766
 767 /*-----------------------------------------------------------------------------
 768 | UART Register Offsets
 769 '----------------------------------------------------------------------------*/
 770 #define         DATA_REG        0x00
 771 #define         DL_LSB          0x00
 772 #define         DL_MSB          0x01
 773 #define         INT_ENABLE      0x01
 774 #define         FIFO_CONTROL    0x02
 775 #define         LINE_CONTROL    0x03
 776 #define         MODEM_CONTROL   0x04
 777 #define         LINE_STATUS     0x05
 778 #define         MODEM_STATUS    0x06
 779 #define         SCRATCH         0x07
 780
 781 /******************************************************************************
 782  * On Chip Memory
 783  ******************************************************************************/
 784 #if defined(CONFIG_405EZ)
 785 #define OCM_DCR_BASE 0x020
 786 #define ocmplb3cr1      (OCM_DCR_BASE+0x00)  /* OCM PLB3 Bank 1 Config Reg    */
 787 #define ocmplb3cr2      (OCM_DCR_BASE+0x01)  /* OCM PLB3 Bank 2 Config Reg    */
 788 #define ocmplb3bear     (OCM_DCR_BASE+0x02)  /* OCM PLB3 Bus Error Add Reg    */
 789 #define ocmplb3besr0    (OCM_DCR_BASE+0x03)  /* OCM PLB3 Bus Error Stat Reg 0 */
 790 #define ocmplb3besr1    (OCM_DCR_BASE+0x04)  /* OCM PLB3 Bus Error Stat Reg 1 */
 791 #define ocmcid          (OCM_DCR_BASE+0x05)  /* OCM Core ID                   */
 792 #define ocmrevid        (OCM_DCR_BASE+0x06)  /* OCM Revision ID               */
 793 #define ocmplb3dpc      (OCM_DCR_BASE+0x07)  /* OCM PLB3 Data Parity Check    */
 794 #define ocmdscr1        (OCM_DCR_BASE+0x08)  /* OCM D-side Bank 1 Config Reg  */
 795 #define ocmdscr2        (OCM_DCR_BASE+0x09)  /* OCM D-side Bank 2 Config Reg  */
 796 #define ocmiscr1        (OCM_DCR_BASE+0x0A)  /* OCM I-side Bank 1 Config Reg  */
 797 #define ocmiscr2        (OCM_DCR_BASE+0x0B)  /* OCM I-side Bank 2 Config Reg  */
 798 #define ocmdsisdpc      (OCM_DCR_BASE+0x0C)  /* OCM D-side/I-side Data Par Chk*/
 799 #define ocmdsisbear     (OCM_DCR_BASE+0x0D)  /* OCM D-side/I-side Bus Err Addr*/
 800 #define ocmdsisbesr     (OCM_DCR_BASE+0x0E)  /* OCM D-side/I-side Bus Err Stat*/
 801 #else
 802 #define OCM_DCR_BASE 0x018
 803 #define ocmisarc   (OCM_DCR_BASE+0x00)  /* OCM I-side address compare reg    */
 804 #define ocmiscntl  (OCM_DCR_BASE+0x01)  /* OCM I-side control reg            */
 805 #define ocmdsarc   (OCM_DCR_BASE+0x02)  /* OCM D-side address compare reg    */
 806 #define ocmdscntl  (OCM_DCR_BASE+0x03)  /* OCM D-side control reg            */
 807 #endif /* CONFIG_405EZ */
 808
 809 /******************************************************************************
 810  * GPIO macro register defines
 811  ******************************************************************************/
 812 #if defined(CONFIG_405EZ)
 813 /* Only the 405EZ has 2 GPIOs */
 814 #define GPIO_BASE  0xEF600700
 815 #define GPIO0_OR                (GPIO_BASE+0x0)
 816 #define GPIO0_TCR               (GPIO_BASE+0x4)
 817 #define GPIO0_OSRL              (GPIO_BASE+0x8)
 818 #define GPIO0_OSRH              (GPIO_BASE+0xC)
 819 #define GPIO0_TSRL              (GPIO_BASE+0x10)
 820 #define GPIO0_TSRH              (GPIO_BASE+0x14)
 821 #define GPIO0_ODR               (GPIO_BASE+0x18)
 822 #define GPIO0_IR                (GPIO_BASE+0x1C)
 823 #define GPIO0_RR1               (GPIO_BASE+0x20)
 824 #define GPIO0_RR2               (GPIO_BASE+0x24)
 825 #define GPIO0_RR3               (GPIO_BASE+0x28)
 826 #define GPIO0_ISR1L             (GPIO_BASE+0x30)
 827 #define GPIO0_ISR1H             (GPIO_BASE+0x34)
 828 #define GPIO0_ISR2L             (GPIO_BASE+0x38)
 829 #define GPIO0_ISR2H             (GPIO_BASE+0x3C)
 830 #define GPIO0_ISR3L             (GPIO_BASE+0x40)
 831 #define GPIO0_ISR3H             (GPIO_BASE+0x44)
 832
 833 #define GPIO1_BASE  0xEF600800
 834 #define GPIO1_OR                (GPIO1_BASE+0x0)
 835 #define GPIO1_TCR               (GPIO1_BASE+0x4)
 836 #define GPIO1_OSRL              (GPIO1_BASE+0x8)
 837 #define GPIO1_OSRH              (GPIO1_BASE+0xC)
 838 #define GPIO1_TSRL              (GPIO1_BASE+0x10)
 839 #define GPIO1_TSRH              (GPIO1_BASE+0x14)
 840 #define GPIO1_ODR               (GPIO1_BASE+0x18)
 841 #define GPIO1_IR                (GPIO1_BASE+0x1C)
 842 #define GPIO1_RR1               (GPIO1_BASE+0x20)
 843 #define GPIO1_RR2               (GPIO1_BASE+0x24)
 844 #define GPIO1_RR3               (GPIO1_BASE+0x28)
 845 #define GPIO1_ISR1L             (GPIO1_BASE+0x30)
 846 #define GPIO1_ISR1H             (GPIO1_BASE+0x34)
 847 #define GPIO1_ISR2L             (GPIO1_BASE+0x38)
 848 #define GPIO1_ISR2H             (GPIO1_BASE+0x3C)
 849 #define GPIO1_ISR3L             (GPIO1_BASE+0x40)
 850 #define GPIO1_ISR3H             (GPIO1_BASE+0x44)
 851
 852 #elif defined(CONFIG_405EX)
 853 #define GPIO_BASE  0xEF600800
 854 #define GPIO0_OR               (GPIO_BASE+0x0)
 855 #define GPIO0_TCR              (GPIO_BASE+0x4)
 856 #define GPIO0_OSRL             (GPIO_BASE+0x8)
 857 #define GPIO0_OSRH             (GPIO_BASE+0xC)
 858 #define GPIO0_TSRL             (GPIO_BASE+0x10)
 859 #define GPIO0_TSRH             (GPIO_BASE+0x14)
 860 #define GPIO0_ODR              (GPIO_BASE+0x18)
 861 #define GPIO0_IR               (GPIO_BASE+0x1C)
 862 #define GPIO0_RR1              (GPIO_BASE+0x20)
 863 #define GPIO0_RR2              (GPIO_BASE+0x24)
 864 #define GPIO0_ISR1L            (GPIO_BASE+0x30)
 865 #define GPIO0_ISR1H            (GPIO_BASE+0x34)
 866 #define GPIO0_ISR2L            (GPIO_BASE+0x38)
 867 #define GPIO0_ISR2H            (GPIO_BASE+0x3C)
 868 #define GPIO0_ISR3L            (GPIO_BASE+0x40)
 869 #define GPIO0_ISR3H            (GPIO_BASE+0x44)
 870
 871 #else   /* !405EZ */
 872
 873 #define GPIO_BASE  0xEF600700
 874 #define GPIO0_OR               (GPIO_BASE+0x0)
 875 #define GPIO0_TCR              (GPIO_BASE+0x4)
 876 #define GPIO0_OSRH             (GPIO_BASE+0x8)
 877 #define GPIO0_OSRL             (GPIO_BASE+0xC)
 878 #define GPIO0_TSRH             (GPIO_BASE+0x10)
 879 #define GPIO0_TSRL             (GPIO_BASE+0x14)
 880 #define GPIO0_ODR              (GPIO_BASE+0x18)
 881 #define GPIO0_IR               (GPIO_BASE+0x1C)
 882 #define GPIO0_RR1              (GPIO_BASE+0x20)
 883 #define GPIO0_RR2              (GPIO_BASE+0x24)
 884 #define GPIO0_ISR1H            (GPIO_BASE+0x30)
 885 #define GPIO0_ISR1L            (GPIO_BASE+0x34)
 886 #define GPIO0_ISR2H            (GPIO_BASE+0x38)
 887 #define GPIO0_ISR2L            (GPIO_BASE+0x3C)
 888
 889 #endif /* CONFIG_405EZ */
 890
 891 #define GPIO0_BASE              GPIO_BASE
 892
 893 #if defined(CONFIG_405EX)
 894 #define SDR0_SRST               0x0200
 895
 896 /*
 897  * Software Reset Register
 898  */
 899 #define SDR0_SRST_BGO           PPC_REG_VAL(0, 1)
 900 #define SDR0_SRST_PLB4          PPC_REG_VAL(1, 1)
 901 #define SDR0_SRST_EBC           PPC_REG_VAL(2, 1)
 902 #define SDR0_SRST_OPB           PPC_REG_VAL(3, 1)
 903 #define SDR0_SRST_UART0         PPC_REG_VAL(4, 1)
 904 #define SDR0_SRST_UART1         PPC_REG_VAL(5, 1)
 905 #define SDR0_SRST_IIC0          PPC_REG_VAL(6, 1)
 906 #define SDR0_SRST_BGI           PPC_REG_VAL(7, 1)
 907 #define SDR0_SRST_GPIO          PPC_REG_VAL(8, 1)
 908 #define SDR0_SRST_GPT           PPC_REG_VAL(9, 1)
 909 #define SDR0_SRST_DMC           PPC_REG_VAL(10, 1)
 910 #define SDR0_SRST_RGMII         PPC_REG_VAL(11, 1)
 911 #define SDR0_SRST_EMAC0         PPC_REG_VAL(12, 1)
 912 #define SDR0_SRST_EMAC1         PPC_REG_VAL(13, 1)
 913 #define SDR0_SRST_CPM           PPC_REG_VAL(14, 1)
 914 #define SDR0_SRST_EPLL          PPC_REG_VAL(15, 1)
 915 #define SDR0_SRST_UIC           PPC_REG_VAL(16, 1)
 916 #define SDR0_SRST_UPRST         PPC_REG_VAL(17, 1)
 917 #define SDR0_SRST_IIC1          PPC_REG_VAL(18, 1)
 918 #define SDR0_SRST_SCP           PPC_REG_VAL(19, 1)
 919 #define SDR0_SRST_UHRST         PPC_REG_VAL(20, 1)
 920 #define SDR0_SRST_DMA           PPC_REG_VAL(21, 1)
 921 #define SDR0_SRST_DMAC          PPC_REG_VAL(22, 1)
 922 #define SDR0_SRST_MAL           PPC_REG_VAL(23, 1)
 923 #define SDR0_SRST_EBM           PPC_REG_VAL(24, 1)
 924 #define SDR0_SRST_GPTR          PPC_REG_VAL(25, 1)
 925 #define SDR0_SRST_PE0           PPC_REG_VAL(26, 1)
 926 #define SDR0_SRST_PE1           PPC_REG_VAL(27, 1)
 927 #define SDR0_SRST_CRYP          PPC_REG_VAL(28, 1)
 928 #define SDR0_SRST_PKP           PPC_REG_VAL(29, 1)
 929 #define SDR0_SRST_AHB           PPC_REG_VAL(30, 1)
 930 #define SDR0_SRST_NDFC          PPC_REG_VAL(31, 1)
 931
 932 #define sdr_uart0       0x0120  /* UART0 Config */
 933 #define sdr_uart1       0x0121  /* UART1 Config */
 934 #define sdr_mfr         0x4300  /* SDR0_MFR reg */
 935
 936 /* Defines for CPC0_EPRCSR register */
 937 #define CPC0_EPRCSR_E0NFE          0x80000000
 938 #define CPC0_EPRCSR_E1NFE          0x40000000
 939 #define CPC0_EPRCSR_E1RPP          0x00000080
 940 #define CPC0_EPRCSR_E0RPP          0x00000040
 941 #define CPC0_EPRCSR_E1ERP          0x00000020
 942 #define CPC0_EPRCSR_E0ERP          0x00000010
 943 #define CPC0_EPRCSR_E1PCI          0x00000002
 944 #define CPC0_EPRCSR_E0PCI          0x00000001
 945
 946 #define cpr0_clkupd     0x020
 947 #define cpr0_pllc       0x040
 948 #define cpr0_plld       0x060
 949 #define cpr0_cpud       0x080
 950 #define cpr0_plbd       0x0a0
 951 #define cpr0_opbd       0x0c0
 952 #define cpr0_perd       0x0e0
 953 #define cpr0_ahbd       0x100
 954 #define cpr0_icfg       0x140
 955
 956 #define SDR_PINSTP      0x0040
 957 #define sdr_sdcs        0x0060
 958
 959 #define SDR0_SDCS_SDD                   (0x80000000 >> 31)
 960
 961 /* CUST0 Customer Configuration Register0 */
 962 #define SDR0_CUST0                   0x4000
 963 #define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
 964 #define   SDR0_CUST0_MUX_EMAC_SEL     0x40000000       /* Emac Selection */
 965 #define   SDR0_CUST0_MUX_NDFC_SEL     0x80000000       /* NDFC Selection */
 966 #define   SDR0_CUST0_MUX_GPIO_SEL     0xC0000000       /* GPIO Selection */
 967
 968 #define   SDR0_CUST0_NDFC_EN_MASK     0x20000000     /* NDFC Enable Mask */
 969 #define   SDR0_CUST0_NDFC_ENABLE      0x20000000       /* NDFC Enable */
 970 #define   SDR0_CUST0_NDFC_DISABLE     0x00000000       /* NDFC Disable */
 971
 972 #define   SDR0_CUST0_NDFC_BW_MASK     0x10000000     /* NDFC Boot Width */
 973 #define   SDR0_CUST0_NDFC_BW_16_BIT   0x10000000       /* NDFC Boot Width = 16 Bit */
 974 #define   SDR0_CUST0_NDFC_BW_8_BIT    0x00000000       /* NDFC Boot Width =  8 Bit */
 975
 976 #define   SDR0_CUST0_NDFC_BP_MASK     0x0F000000     /* NDFC Boot Page */
 977 #define   SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
 978 #define   SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
 979
 980 #define   SDR0_CUST0_NDFC_BAC_MASK    0x00C00000     /* NDFC Boot Address Cycle */
 981 #define   SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
 982 #define   SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
 983
 984 #define   SDR0_CUST0_NDFC_ARE_MASK    0x00200000     /* NDFC Auto Read Enable */
 985 #define   SDR0_CUST0_NDFC_ARE_ENABLE  0x00200000       /* NDFC Auto Read Enable */
 986 #define   SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000       /* NDFC Auto Read Disable */
 987
 988 #define   SDR0_CUST0_NRB_MASK         0x00100000     /* NDFC Ready / Busy */
 989 #define   SDR0_CUST0_NRB_BUSY         0x00100000       /* Busy */
 990 #define   SDR0_CUST0_NRB_READY        0x00000000       /* Ready */
 991
 992 #define   SDR0_CUST0_NDRSC_MASK       0x0000FFF0     /* NDFC Device Reset Count Mask */
 993 #define   SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
 994 #define   SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
 995
 996 #define   SDR0_CUST0_CHIPSELGAT_MASK  0x0000000F     /* Chip Select Gating Mask */
 997 #define   SDR0_CUST0_CHIPSELGAT_DIS   0x00000000       /* Chip Select Gating Disable */
 998 #define   SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F       /* All Chip Select Gating Enable */
 999 #define   SDR0_CUST0_CHIPSELGAT_EN0   0x00000008       /* Chip Select0 Gating Enable */
1000 #define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
1001 #define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
1002 #define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
1003
1004 #define SDR0_PFC0               0x4100
1005 #define SDR0_PFC1               0x4101
1006 #define SDR0_PFC1_U1ME          0x02000000
1007 #define SDR0_PFC1_U0ME          0x00080000
1008 #define SDR0_PFC1_U0IM          0x00040000
1009 #define SDR0_PFC1_SIS           0x00020000
1010 #define SDR0_PFC1_DMAAEN        0x00010000
1011 #define SDR0_PFC1_DMADEN        0x00008000
1012 #define SDR0_PFC1_USBEN         0x00004000
1013 #define SDR0_PFC1_AHBSWAP       0x00000020
1014 #define SDR0_PFC1_USBBIGEN      0x00000010
1015 #define SDR0_PFC1_GPT_FREQ      0x0000000f
1016 #endif
1017
1018 /* General Purpose Timer (GPT) Register Offsets */
1019 #define GPT0_TBC                0x00000000
1020 #define GPT0_IM                 0x00000018
1021 #define GPT0_ISS                0x0000001C
1022 #define GPT0_ISC                0x00000020
1023 #define GPT0_IE                 0x00000024
1024 #define GPT0_COMP0              0x00000080
1025 #define GPT0_COMP1              0x00000084
1026 #define GPT0_COMP2              0x00000088
1027 #define GPT0_COMP3              0x0000008C
1028 #define GPT0_COMP4              0x00000090
1029 #define GPT0_COMP5              0x00000094
1030 #define GPT0_COMP6              0x00000098
1031 #define GPT0_MASK0              0x000000C0
1032 #define GPT0_MASK1              0x000000C4
1033 #define GPT0_MASK2              0x000000C8
1034 #define GPT0_MASK3              0x000000CC
1035 #define GPT0_MASK4              0x000000D0
1036 #define GPT0_MASK5              0x000000D4
1037 #define GPT0_MASK6              0x000000D8
1038 #define GPT0_DCT0               0x00000110
1039 #define GPT0_DCIS               0x0000011C
1040
1041 #endif  /* __PPC405_H__ */