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git.ipfire.org Git - people/ms/u-boot.git/blob - include/ppc440.h
1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 /*--------------------------------------------------------------------- */
26 /* Special Purpose Registers */
27 /*--------------------------------------------------------------------- */
30 #define dec 0x016 /* decrementer */
31 #define srr0 0x01a /* save/restore register 0 */
32 #define srr1 0x01b /* save/restore register 1 */
33 #define pid 0x030 /* process id */
34 #define decar 0x036 /* decrementer auto-reload */
35 #define csrr0 0x03a /* critical save/restore register 0 */
36 #define csrr1 0x03b /* critical save/restore register 1 */
37 #define dear 0x03d /* data exception address register */
38 #define esr 0x03e /* exception syndrome register */
39 #define ivpr 0x03f /* interrupt prefix register */
40 #define usprg0 0x100 /* user special purpose register general 0 */
41 #define usprg1 0x110 /* user special purpose register general 1 */
42 #define tblr 0x10c /* time base lower, read only */
43 #define tbur 0x10d /* time base upper, read only */
44 #define sprg1 0x111 /* special purpose register general 1 */
45 #define sprg2 0x112 /* special purpose register general 2 */
46 #define sprg3 0x113 /* special purpose register general 3 */
47 #define sprg4 0x114 /* special purpose register general 4 */
48 #define sprg5 0x115 /* special purpose register general 5 */
49 #define sprg6 0x116 /* special purpose register general 6 */
50 #define sprg7 0x117 /* special purpose register general 7 */
51 #define tbl 0x11c /* time base lower (supervisor)*/
52 #define tbu 0x11d /* time base upper (supervisor)*/
53 #define pir 0x11e /* processor id register */
54 /*#define pvr 0x11f processor version register */
55 #define dbsr 0x130 /* debug status register */
56 #define dbcr0 0x134 /* debug control register 0 */
57 #define dbcr1 0x135 /* debug control register 1 */
58 #define dbcr2 0x136 /* debug control register 2 */
59 #define iac1 0x138 /* instruction address compare 1 */
60 #define iac2 0x139 /* instruction address compare 2 */
61 #define iac3 0x13a /* instruction address compare 3 */
62 #define iac4 0x13b /* instruction address compare 4 */
63 #define dac1 0x13c /* data address compare 1 */
64 #define dac2 0x13d /* data address compare 2 */
65 #define dvc1 0x13e /* data value compare 1 */
66 #define dvc2 0x13f /* data value compare 2 */
67 #define tsr 0x150 /* timer status register */
68 #define tcr 0x154 /* timer control register */
69 #define ivor0 0x190 /* interrupt vector offset register 0 */
70 #define ivor1 0x191 /* interrupt vector offset register 1 */
71 #define ivor2 0x192 /* interrupt vector offset register 2 */
72 #define ivor3 0x193 /* interrupt vector offset register 3 */
73 #define ivor4 0x194 /* interrupt vector offset register 4 */
74 #define ivor5 0x195 /* interrupt vector offset register 5 */
75 #define ivor6 0x196 /* interrupt vector offset register 6 */
76 #define ivor7 0x197 /* interrupt vector offset register 7 */
77 #define ivor8 0x198 /* interrupt vector offset register 8 */
78 #define ivor9 0x199 /* interrupt vector offset register 9 */
79 #define ivor10 0x19a /* interrupt vector offset register 10 */
80 #define ivor11 0x19b /* interrupt vector offset register 11 */
81 #define ivor12 0x19c /* interrupt vector offset register 12 */
82 #define ivor13 0x19d /* interrupt vector offset register 13 */
83 #define ivor14 0x19e /* interrupt vector offset register 14 */
84 #define ivor15 0x19f /* interrupt vector offset register 15 */
85 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
86 #define mcsrr0 0x23a /* machine check save/restore register 0 */
87 #define mcsrr1 0x23b /* mahcine check save/restore register 1 */
88 #define mcsr 0x23c /* machine check status register */
90 #define inv0 0x370 /* instruction cache normal victim 0 */
91 #define inv1 0x371 /* instruction cache normal victim 1 */
92 #define inv2 0x372 /* instruction cache normal victim 2 */
93 #define inv3 0x373 /* instruction cache normal victim 3 */
94 #define itv0 0x374 /* instruction cache transient victim 0 */
95 #define itv1 0x375 /* instruction cache transient victim 1 */
96 #define itv2 0x376 /* instruction cache transient victim 2 */
97 #define itv3 0x377 /* instruction cache transient victim 3 */
98 #define dnv0 0x390 /* data cache normal victim 0 */
99 #define dnv1 0x391 /* data cache normal victim 1 */
100 #define dnv2 0x392 /* data cache normal victim 2 */
101 #define dnv3 0x393 /* data cache normal victim 3 */
102 #define dtv0 0x394 /* data cache transient victim 0 */
103 #define dtv1 0x395 /* data cache transient victim 1 */
104 #define dtv2 0x396 /* data cache transient victim 2 */
105 #define dtv3 0x397 /* data cache transient victim 3 */
106 #define dvlim 0x398 /* data cache victim limit */
107 #define ivlim 0x399 /* instruction cache victim limit */
108 #define rstcfg 0x39b /* reset configuration */
109 #define dcdbtrl 0x39c /* data cache debug tag register low */
110 #define dcdbtrh 0x39d /* data cache debug tag register high */
111 #define icdbtrl 0x39e /* instruction cache debug tag register low */
112 #define icdbtrh 0x39f /* instruction cache debug tag register high */
113 #define mmucr 0x3b2 /* mmu control register */
114 #define ccr0 0x3b3 /* core configuration register 0 */
115 #define ccr1 0x378 /* core configuration for 440x5 only */
116 #define icdbdr 0x3d3 /* instruction cache debug data register */
117 #define dbdr 0x3f3 /* debug data register */
119 /******************************************************************************
121 ******************************************************************************/
123 /*-----------------------------------------------------------------------------
124 | Clocking Controller
125 +----------------------------------------------------------------------------*/
126 #define CLOCKING_DCR_BASE 0x0c
127 #define clkcfga (CLOCKING_DCR_BASE+0x0)
128 #define clkcfgd (CLOCKING_DCR_BASE+0x1)
130 /* values for clkcfga register - indirect addressing of these regs */
131 #define clk_clkukpd 0x0020
132 #define clk_pllc 0x0040
133 #define clk_plld 0x0060
134 #define clk_primad 0x0080
135 #define clk_primbd 0x00a0
136 #define clk_opbd 0x00c0
137 #define clk_perd 0x00e0
138 #define clk_mald 0x0100
139 #define clk_spcid 0x0120
140 #define clk_icfg 0x0140
142 /* 440gx sdr register definations */
143 #define SDR_DCR_BASE 0x0e
144 #define sdrcfga (SDR_DCR_BASE+0x0)
145 #define sdrcfgd (SDR_DCR_BASE+0x1)
146 #define sdr_sdstp0 0x0020 /* */
147 #define sdr_sdstp1 0x0021 /* */
148 #define sdr_pinstp 0x0040
149 #define sdr_sdcs 0x0060
150 #define sdr_ecid0 0x0080
151 #define sdr_ecid1 0x0081
152 #define sdr_ecid2 0x0082
153 #define sdr_jtag 0x00c0
154 #define sdr_ddrdl 0x00e0
155 #define sdr_ebc 0x0100
156 #define sdr_uart0 0x0120 /* UART0 Config */
157 #define sdr_uart1 0x0121 /* UART1 Config */
158 #define sdr_uart2 0x0122 /* UART2 Config */
159 #define sdr_uart3 0x0123 /* UART3 Config */
160 #define sdr_cp440 0x0180
161 #define sdr_xcr 0x01c0
162 #define sdr_xpllc 0x01c1
163 #define sdr_xplld 0x01c2
164 #define sdr_srst 0x0200
165 #define sdr_slpipe 0x0220
166 #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
167 #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
168 #define sdr_mirq0 0x0260
169 #define sdr_mirq1 0x0261
170 #define sdr_maltbl 0x0280
171 #define sdr_malrbl 0x02a0
172 #define sdr_maltbs 0x02c0
173 #define sdr_malrbs 0x02e0
174 #define sdr_pci0 0x0300
175 #define sdr_usb0 0x0320
176 #define sdr_cust0 0x4000
177 #define sdr_cust1 0x4002
178 #define sdr_pfc0 0x4100 /* Pin Function 0 */
179 #define sdr_pfc1 0x4101 /* Pin Function 1 */
180 #define sdr_plbtr 0x4200
181 #define sdr_mfr 0x4300 /* SDR0_MFR reg */
183 /*-----------------------------------------------------------------------------
185 +----------------------------------------------------------------------------*/
186 #define SDRAM_DCR_BASE 0x10
187 #define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
188 #define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
190 /* values for memcfga register - indirect addressing of these regs */
191 #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
192 #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
193 #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
194 #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
195 #define mem_bear 0x0010 /* bus error address reg */
196 #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
197 #define mem_mirq_set 0x0012 /* bus master interrupt (set) */
198 #define mem_slio 0x0018 /* ddr sdram slave interface options */
199 #define mem_cfg0 0x0020 /* ddr sdram options 0 */
200 #define mem_cfg1 0x0021 /* ddr sdram options 1 */
201 #define mem_devopt 0x0022 /* ddr sdram device options */
202 #define mem_mcsts 0x0024 /* memory controller status */
203 #define mem_rtr 0x0030 /* refresh timer register */
204 #define mem_pmit 0x0034 /* power management idle timer */
205 #define mem_uabba 0x0038 /* plb UABus base address */
206 #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
207 #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
208 #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
209 #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
210 #define mem_tr0 0x0080 /* sdram timing register 0 */
211 #define mem_tr1 0x0081 /* sdram timing register 1 */
212 #define mem_clktr 0x0082 /* ddr clock timing register */
213 #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
214 #define mem_dlycal 0x0084 /* delay line calibration register */
215 #define mem_eccesr 0x0098 /* ECC error status */
218 #define sdr_amp 0x0240
219 #define sdr_xpllc 0x01c1
220 #define sdr_xplld 0x01c2
221 #define sdr_xcr 0x01c0
222 #define sdr_sdstp2 0x4001
223 #define sdr_sdstp3 0x4003
224 #endif /* CONFIG_440GX */
228 #define sdr_sdstp2 0x0022
230 #define sdr_sdstp3 0x0023
231 #define sdr_ddr0 0x00E1
232 #define sdr_uart2 0x0122
233 #define sdr_xcr0 0x01c0
234 /* #define sdr_xcr1 0x01c3 only one PCIX - SG */
235 /* #define sdr_xcr2 0x01c6 only one PCIX - SG */
236 #define sdr_xpllc0 0x01c1
237 #define sdr_xplld0 0x01c2
238 #define sdr_xpllc1 0x01c4 /*notRCW - SG */
239 #define sdr_xplld1 0x01c5 /*notRCW - SG */
240 #define sdr_xpllc2 0x01c7 /*notRCW - SG */
241 #define sdr_xplld2 0x01c8 /*notRCW - SG */
242 #define sdr_amp0 0x0240
243 #define sdr_amp1 0x0241
244 #define sdr_cust2 0x4004
245 #define sdr_cust3 0x4006
246 #define sdr_sdstp4 0x4001
247 #define sdr_sdstp5 0x4003
248 #define sdr_sdstp6 0x4005
249 #define sdr_sdstp7 0x4007
251 /*----------------------------------------------------------------------------+
252 | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
253 +----------------------------------------------------------------------------*/
254 #define CCR0_PRE 0x40000000
255 #define CCR0_CRPE 0x08000000
256 #define CCR0_DSTG 0x00200000
257 #define CCR0_DAPUIB 0x00100000
258 #define CCR0_DTB 0x00008000
259 #define CCR0_GICBT 0x00004000
260 #define CCR0_GDCBT 0x00002000
261 #define CCR0_FLSTA 0x00000100
262 #define CCR0_ICSLC_MASK 0x0000000C
263 #define CCR0_ICSLT_MASK 0x00000003
264 #define CCR1_TCS_MASK 0x00000080
265 #define CCR1_TCS_INTCLK 0x00000000
266 #define CCR1_TCS_EXTCLK 0x00000080
267 #define MMUCR_SEOA 0x01000000
268 #define MMUCR_U1TE 0x00400000
269 #define MMUCR_U2SWOAE 0x00200000
270 #define MMUCR_DULXE 0x00800000
271 #define MMUCR_IULXE 0x00400000
272 #define MMUCR_STS 0x00100000
273 #define MMUCR_STID_MASK 0x000000FF
275 #define SDR0_CFGADDR 0x00E
276 #define SDR0_CFGDATA 0x00F
278 /******************************************************************************
279 * PCI express defines
280 ******************************************************************************/
281 #define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
282 #define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
283 #define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
284 #define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
285 #define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
286 #define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
287 #define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
288 #define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
289 #define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
290 #define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
291 #define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
292 #define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
293 #define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
294 #define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
295 #define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
296 #define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
297 #define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
298 #define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
299 #define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
300 #define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
301 #define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
302 #define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
303 #define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
304 #define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
305 #define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
306 #define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
307 #define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
308 #define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
309 #define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
310 #define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
311 #define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
312 #define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
313 #define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
315 #define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
316 #define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
317 #define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
318 #define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
319 #define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
320 #define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
321 #define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
322 #define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
323 #define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
324 #define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
325 #define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
326 #define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
327 #define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
328 #define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
329 #define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
330 #define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
331 #define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
332 #define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
333 #define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
334 #define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
335 #define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
336 #define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
337 #define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
338 #define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
339 #define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
340 #define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
341 #define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
342 #define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
343 #define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
344 #define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
345 #define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
346 #define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
347 #define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
348 #define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
349 #define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
350 #define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
351 #define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
352 #define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
353 #define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
354 #define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
355 #define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
356 #define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
357 #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
359 /*----------------------------------------------------------------------------+
361 +----------------------------------------------------------------------------*/
362 /*-----------------------------------------------------------------------------+
363 | SDRAM DLYCAL Options
364 +-----------------------------------------------------------------------------*/
365 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
366 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
367 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
369 /*----------------------------------------------------------------------------+
370 | Memory queue defines
371 +----------------------------------------------------------------------------*/
372 /* A REVOIR versus RWC - SG*/
373 #define SDRAMQ_DCR_BASE 0x040
375 #define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
376 #define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
377 #define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
378 #define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
379 #define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
380 #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
381 #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
382 #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
383 #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
384 #define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
385 #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
386 #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
387 #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
388 #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
389 #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
391 /*-----------------------------------------------------------------------------+
392 | Memory Bank 0-7 configuration
393 +-----------------------------------------------------------------------------*/
394 #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
395 #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
396 #define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
397 #define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
398 #define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
399 #define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
400 #define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
401 #define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
402 #define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
403 #define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
404 #define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
405 #define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
406 #define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
407 #define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
408 #define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
409 #define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
410 #define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
412 /*----------------------------------------------------------------------------+
413 | Memory controller defines
414 +----------------------------------------------------------------------------*/
415 #define SDRAMC_DCR_BASE 0x010
416 #define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */
417 #define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */
419 /* A REVOIR versus specs 4 bank - SG*/
420 #define SDRAM_MCSTAT 0x14 /* memory controller status */
421 #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
422 #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
423 #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
424 #define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
425 #define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
426 #define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
427 #define SDRAM_CODT 0x26 /* on die termination for controller */
428 #define SDRAM_VVPR 0x27 /* variable VRef programmming */
429 #define SDRAM_OPARS 0x28 /* on chip driver control setup */
430 #define SDRAM_OPART 0x29 /* on chip driver control trigger */
431 #define SDRAM_RTR 0x30 /* refresh timer */
432 #define SDRAM_PMIT 0x34 /* power management idle timer */
433 #define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
434 #define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
435 #define SDRAM_MB2CF 0x48
436 #define SDRAM_MB3CF 0x4C
437 #define SDRAM_INITPLR0 0x50 /* manual initialization control */
438 #define SDRAM_INITPLR1 0x51 /* manual initialization control */
439 #define SDRAM_INITPLR2 0x52 /* manual initialization control */
440 #define SDRAM_INITPLR3 0x53 /* manual initialization control */
441 #define SDRAM_INITPLR4 0x54 /* manual initialization control */
442 #define SDRAM_INITPLR5 0x55 /* manual initialization control */
443 #define SDRAM_INITPLR6 0x56 /* manual initialization control */
444 #define SDRAM_INITPLR7 0x57 /* manual initialization control */
445 #define SDRAM_INITPLR8 0x58 /* manual initialization control */
446 #define SDRAM_INITPLR9 0x59 /* manual initialization control */
447 #define SDRAM_INITPLR10 0x5a /* manual initialization control */
448 #define SDRAM_INITPLR11 0x5b /* manual initialization control */
449 #define SDRAM_INITPLR12 0x5c /* manual initialization control */
450 #define SDRAM_INITPLR13 0x5d /* manual initialization control */
451 #define SDRAM_INITPLR14 0x5e /* manual initialization control */
452 #define SDRAM_INITPLR15 0x5f /* manual initialization control */
453 #define SDRAM_RQDC 0x70 /* read DQS delay control */
454 #define SDRAM_RFDC 0x74 /* read feedback delay control */
455 #define SDRAM_RDCC 0x78 /* read data capture control */
456 #define SDRAM_DLCR 0x7A /* delay line calibration */
457 #define SDRAM_CLKTR 0x80 /* DDR clock timing */
458 #define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
459 #define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
460 #define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
461 #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
462 #define SDRAM_MMODE 0x88 /* memory mode */
463 #define SDRAM_MEMODE 0x89 /* memory extended mode */
464 #define SDRAM_ECCCR 0x98 /* ECC error status */
465 #define SDRAM_CID 0xA4 /* core ID */
466 #define SDRAM_RID 0xA8 /* revision ID */
468 /*-----------------------------------------------------------------------------+
469 | Memory Controller Status
470 +-----------------------------------------------------------------------------*/
471 #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
472 #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
473 #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
474 #define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
475 #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
476 #define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
478 /*-----------------------------------------------------------------------------+
479 | Memory Controller Options 1
480 +-----------------------------------------------------------------------------*/
481 #define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
482 #define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
483 #define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
484 #define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
485 #define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
486 #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
487 #define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
488 #define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
489 #define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
490 #define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
491 #define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
492 #define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
493 #define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
494 #define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
495 #define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
496 #define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
497 #define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
498 #define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
499 #define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
500 #define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
501 #define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
502 #define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
503 #define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
504 #define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
505 #define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
506 #define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
507 #define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
508 #define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
509 #define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
510 #define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
511 #define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
512 #define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
513 #define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
514 #define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
515 #define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
517 /*-----------------------------------------------------------------------------+
518 | Memory Controller Options 2
519 +-----------------------------------------------------------------------------*/
520 #define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
521 #define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
522 #define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
523 #define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
524 #define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
525 #define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
526 #define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
527 #define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
528 #define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
529 #define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
530 #define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
531 #define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
532 #define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
533 #define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
534 #define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
535 #define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
536 #define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
537 #define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
539 /*-----------------------------------------------------------------------------+
540 | SDRAM Refresh Timer Register
541 +-----------------------------------------------------------------------------*/
542 #define SDRAM_RTR_RINT_MASK 0xFFF80000
543 #define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
544 #define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
546 /*-----------------------------------------------------------------------------+
547 | SDRAM Read DQS Delay Control Register
548 +-----------------------------------------------------------------------------*/
549 #define SDRAM_RQDC_RQDE_MASK 0x80000000
550 #define SDRAM_RQDC_RQDE_DISABLE 0x00000000
551 #define SDRAM_RQDC_RQDE_ENABLE 0x80000000
552 #define SDRAM_RQDC_RQFD_MASK 0x000001FF
553 #define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
555 #define SDRAM_RQDC_RQFD_MAX 0x1FF
557 /*-----------------------------------------------------------------------------+
558 | SDRAM Read Data Capture Control Register
559 +-----------------------------------------------------------------------------*/
560 #define SDRAM_RDCC_RDSS_MASK 0xC0000000
561 #define SDRAM_RDCC_RDSS_T1 0x00000000
562 #define SDRAM_RDCC_RDSS_T2 0x40000000
563 #define SDRAM_RDCC_RDSS_T3 0x80000000
564 #define SDRAM_RDCC_RDSS_T4 0xC0000000
565 #define SDRAM_RDCC_RSAE_MASK 0x00000001
566 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001
567 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000
569 /*-----------------------------------------------------------------------------+
570 | SDRAM Read Feedback Delay Control Register
571 +-----------------------------------------------------------------------------*/
572 #define SDRAM_RFDC_ARSE_MASK 0x80000000
573 #define SDRAM_RFDC_ARSE_DISABLE 0x80000000
574 #define SDRAM_RFDC_ARSE_ENABLE 0x00000000
575 #define SDRAM_RFDC_RFOS_MASK 0x007F0000
576 #define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
577 #define SDRAM_RFDC_RFFD_MASK 0x000003FF
578 #define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
580 #define SDRAM_RFDC_RFFD_MAX 0x7FF
582 /*-----------------------------------------------------------------------------+
583 | SDRAM Delay Line Calibration Register
584 +-----------------------------------------------------------------------------*/
585 #define SDRAM_DLCR_DCLM_MASK 0x80000000
586 #define SDRAM_DLCR_DCLM_MANUEL 0x80000000
587 #define SDRAM_DLCR_DCLM_AUTO 0x00000000
588 #define SDRAM_DLCR_DLCR_MASK 0x08000000
589 #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
590 #define SDRAM_DLCR_DLCR_IDLE 0x00000000
591 #define SDRAM_DLCR_DLCS_MASK 0x07000000
592 #define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
593 #define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
594 #define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
595 #define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
596 #define SDRAM_DLCR_DLCS_ERROR 0x04000000
597 #define SDRAM_DLCR_DLCV_MASK 0x000001FF
598 #define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
599 #define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
601 /*-----------------------------------------------------------------------------+
602 | SDRAM Controller On Die Termination Register
603 +-----------------------------------------------------------------------------*/
604 #define SDRAM_CODT_ODT_ON 0x80000000
605 #define SDRAM_CODT_ODT_OFF 0x00000000
606 #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
607 #define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
608 #define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
609 #define SDRAM_CODT_DQS_MASK 0x00000010
610 #define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
611 #define SDRAM_CODT_DQS_SINGLE_END 0x00000010
612 #define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
613 #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
614 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
615 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
616 #define SDRAM_CODT_IO_HIZ 0x00000000
617 #define SDRAM_CODT_IO_NMODE 0x00000001
619 /*-----------------------------------------------------------------------------+
620 | SDRAM Mode Register
621 +-----------------------------------------------------------------------------*/
622 #define SDRAM_MMODE_WR_MASK 0x00000E00
623 #define SDRAM_MMODE_WR_DDR1 0x00000000
624 #define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
625 #define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
626 #define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
627 #define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
628 #define SDRAM_MMODE_DCL_MASK 0x00000070
629 #define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
630 #define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
631 #define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
632 #define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
633 #define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
634 #define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
635 #define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
636 #define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
637 #define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
639 /*-----------------------------------------------------------------------------+
640 | SDRAM Extended Mode Register
641 +-----------------------------------------------------------------------------*/
642 #define SDRAM_MEMODE_DIC_MASK 0x00000002
643 #define SDRAM_MEMODE_DIC_NORMAL 0x00000000
644 #define SDRAM_MEMODE_DIC_WEAK 0x00000002
645 #define SDRAM_MEMODE_DLL_MASK 0x00000001
646 #define SDRAM_MEMODE_DLL_DISABLE 0x00000001
647 #define SDRAM_MEMODE_DLL_ENABLE 0x00000000
648 #define SDRAM_MEMODE_RTT_MASK 0x00000044
649 #define SDRAM_MEMODE_RTT_DISABLED 0x00000000
650 #define SDRAM_MEMODE_RTT_75OHM 0x00000004
651 #define SDRAM_MEMODE_RTT_150OHM 0x00000040
652 #define SDRAM_MEMODE_DQS_MASK 0x00000400
653 #define SDRAM_MEMODE_DQS_DISABLE 0x00000400
654 #define SDRAM_MEMODE_DQS_ENABLE 0x00000000
656 /*-----------------------------------------------------------------------------+
657 | SDRAM Clock Timing Register
658 +-----------------------------------------------------------------------------*/
659 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
660 #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
661 #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
663 /*-----------------------------------------------------------------------------+
664 | SDRAM Write Timing Register
665 +-----------------------------------------------------------------------------*/
666 #define SDRAM_WRDTR_LLWP_MASK 0x10000000
667 #define SDRAM_WRDTR_LLWP_DIS 0x10000000
668 #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
669 #define SDRAM_WRDTR_WTR_MASK 0x0E000000
670 #define SDRAM_WRDTR_WTR_0_DEG 0x06000000
671 #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
672 #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
674 /*-----------------------------------------------------------------------------+
675 | SDRAM SDTR1 Options
676 +-----------------------------------------------------------------------------*/
677 #define SDRAM_SDTR1_LDOF_MASK 0x80000000
678 #define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
679 #define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
680 #define SDRAM_SDTR1_RTW_MASK 0x00F00000
681 #define SDRAM_SDTR1_RTW_2_CLK 0x00200000
682 #define SDRAM_SDTR1_RTW_3_CLK 0x00300000
683 #define SDRAM_SDTR1_WTWO_MASK 0x000F0000
684 #define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
685 #define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
686 #define SDRAM_SDTR1_RTRO_MASK 0x0000F000
687 #define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
688 #define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
690 /*-----------------------------------------------------------------------------+
691 | SDRAM SDTR2 Options
692 +-----------------------------------------------------------------------------*/
693 #define SDRAM_SDTR2_RCD_MASK 0xF0000000
694 #define SDRAM_SDTR2_RCD_1_CLK 0x10000000
695 #define SDRAM_SDTR2_RCD_2_CLK 0x20000000
696 #define SDRAM_SDTR2_RCD_3_CLK 0x30000000
697 #define SDRAM_SDTR2_RCD_4_CLK 0x40000000
698 #define SDRAM_SDTR2_RCD_5_CLK 0x50000000
699 #define SDRAM_SDTR2_WTR_MASK 0x0F000000
700 #define SDRAM_SDTR2_WTR_1_CLK 0x01000000
701 #define SDRAM_SDTR2_WTR_2_CLK 0x02000000
702 #define SDRAM_SDTR2_WTR_3_CLK 0x03000000
703 #define SDRAM_SDTR2_WTR_4_CLK 0x04000000
704 #define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
705 #define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
706 #define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
707 #define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
708 #define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
709 #define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
710 #define SDRAM_SDTR2_WPC_MASK 0x0000F000
711 #define SDRAM_SDTR2_WPC_2_CLK 0x00002000
712 #define SDRAM_SDTR2_WPC_3_CLK 0x00003000
713 #define SDRAM_SDTR2_WPC_4_CLK 0x00004000
714 #define SDRAM_SDTR2_WPC_5_CLK 0x00005000
715 #define SDRAM_SDTR2_WPC_6_CLK 0x00006000
716 #define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
717 #define SDRAM_SDTR2_RPC_MASK 0x00000F00
718 #define SDRAM_SDTR2_RPC_2_CLK 0x00000200
719 #define SDRAM_SDTR2_RPC_3_CLK 0x00000300
720 #define SDRAM_SDTR2_RPC_4_CLK 0x00000400
721 #define SDRAM_SDTR2_RP_MASK 0x000000F0
722 #define SDRAM_SDTR2_RP_3_CLK 0x00000030
723 #define SDRAM_SDTR2_RP_4_CLK 0x00000040
724 #define SDRAM_SDTR2_RP_5_CLK 0x00000050
725 #define SDRAM_SDTR2_RP_6_CLK 0x00000060
726 #define SDRAM_SDTR2_RP_7_CLK 0x00000070
727 #define SDRAM_SDTR2_RRD_MASK 0x0000000F
728 #define SDRAM_SDTR2_RRD_2_CLK 0x00000002
729 #define SDRAM_SDTR2_RRD_3_CLK 0x00000003
731 /*-----------------------------------------------------------------------------+
732 | SDRAM SDTR3 Options
733 +-----------------------------------------------------------------------------*/
734 #define SDRAM_SDTR3_RAS_MASK 0x1F000000
735 #define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
736 #define SDRAM_SDTR3_RC_MASK 0x001F0000
737 #define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
738 #define SDRAM_SDTR3_XCS_MASK 0x00001F00
739 #define SDRAM_SDTR3_XCS 0x00000D00
740 #define SDRAM_SDTR3_RFC_MASK 0x0000003F
741 #define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
743 /*-----------------------------------------------------------------------------+
744 | Memory Bank 0-1 configuration
745 +-----------------------------------------------------------------------------*/
746 #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
747 #define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
748 #define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
749 #define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
750 #define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
751 #define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
752 #define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
753 #define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
754 #define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
755 #define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
756 #define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
757 #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
758 #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
759 #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
760 #endif /* CONFIG_440SPE */
762 /*-----------------------------------------------------------------------------
763 | External Bus Controller
764 +----------------------------------------------------------------------------*/
765 #define EBC_DCR_BASE 0x12
766 #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
767 #define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
768 /* values for ebccfga register - indirect addressing of these regs */
769 #define pb0cr 0x00 /* periph bank 0 config reg */
770 #define pb1cr 0x01 /* periph bank 1 config reg */
771 #define pb2cr 0x02 /* periph bank 2 config reg */
772 #define pb3cr 0x03 /* periph bank 3 config reg */
773 #define pb4cr 0x04 /* periph bank 4 config reg */
774 #define pb5cr 0x05 /* periph bank 5 config reg */
775 #define pb6cr 0x06 /* periph bank 6 config reg */
776 #define pb7cr 0x07 /* periph bank 7 config reg */
777 #define pb0ap 0x10 /* periph bank 0 access parameters */
778 #define pb1ap 0x11 /* periph bank 1 access parameters */
779 #define pb2ap 0x12 /* periph bank 2 access parameters */
780 #define pb3ap 0x13 /* periph bank 3 access parameters */
781 #define pb4ap 0x14 /* periph bank 4 access parameters */
782 #define pb5ap 0x15 /* periph bank 5 access parameters */
783 #define pb6ap 0x16 /* periph bank 6 access parameters */
784 #define pb7ap 0x17 /* periph bank 7 access parameters */
785 #define pbear 0x20 /* periph bus error addr reg */
786 #define pbesr 0x21 /* periph bus error status reg */
787 #define xbcfg 0x23 /* external bus configuration reg */
788 #define xbcid 0x24 /* external bus core id reg */
790 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
792 /* PLB4 to PLB3 Bridge OUT */
793 #define P4P3_DCR_BASE 0x020
794 #define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
795 #define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
796 #define p4p3_eadr (P4P3_DCR_BASE+0x2)
797 #define p4p3_euadr (P4P3_DCR_BASE+0x3)
798 #define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
799 #define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
800 #define p4p3_confg (P4P3_DCR_BASE+0x6)
801 #define p4p3_pic (P4P3_DCR_BASE+0x7)
802 #define p4p3_peir (P4P3_DCR_BASE+0x8)
803 #define p4p3_rev (P4P3_DCR_BASE+0xA)
805 /* PLB3 to PLB4 Bridge IN */
806 #define P3P4_DCR_BASE 0x030
807 #define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
808 #define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
809 #define p3p4_eadr (P3P4_DCR_BASE+0x2)
810 #define p3p4_euadr (P3P4_DCR_BASE+0x3)
811 #define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
812 #define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
813 #define p3p4_confg (P3P4_DCR_BASE+0x6)
814 #define p3p4_pic (P3P4_DCR_BASE+0x7)
815 #define p3p4_peir (P3P4_DCR_BASE+0x8)
816 #define p3p4_rev (P3P4_DCR_BASE+0xA)
819 #define PLB3_DCR_BASE 0x070
820 #define plb3_revid (PLB3_DCR_BASE+0x2)
821 #define plb3_besr (PLB3_DCR_BASE+0x3)
822 #define plb3_bear (PLB3_DCR_BASE+0x6)
823 #define plb3_acr (PLB3_DCR_BASE+0x7)
825 /* PLB4 Arbiter - PowerPC440EP Pass1 */
826 #define PLB4_DCR_BASE 0x080
827 #define plb4_revid (PLB4_DCR_BASE+0x2)
828 #define plb4_acr (PLB4_DCR_BASE+0x3)
829 #define plb4_besr (PLB4_DCR_BASE+0x4)
830 #define plb4_bearl (PLB4_DCR_BASE+0x6)
831 #define plb4_bearh (PLB4_DCR_BASE+0x7)
833 /* Nebula PLB4 Arbiter - PowerPC440EP */
834 #define PLB_ARBITER_BASE 0x80
836 #define plb0_revid (PLB_ARBITER_BASE+ 0x00)
837 #define plb0_acr (PLB_ARBITER_BASE+ 0x01)
838 #define plb0_acr_ppm_mask 0xF0000000
839 #define plb0_acr_ppm_fixed 0x00000000
840 #define plb0_acr_ppm_fair 0xD0000000
841 #define plb0_acr_hbu_mask 0x08000000
842 #define plb0_acr_hbu_disabled 0x00000000
843 #define plb0_acr_hbu_enabled 0x08000000
844 #define plb0_acr_rdp_mask 0x06000000
845 #define plb0_acr_rdp_disabled 0x00000000
846 #define plb0_acr_rdp_2deep 0x02000000
847 #define plb0_acr_rdp_3deep 0x04000000
848 #define plb0_acr_rdp_4deep 0x06000000
849 #define plb0_acr_wrp_mask 0x01000000
850 #define plb0_acr_wrp_disabled 0x00000000
851 #define plb0_acr_wrp_2deep 0x01000000
853 #define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
854 #define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
855 #define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
856 #define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
857 #define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
859 #define plb1_acr (PLB_ARBITER_BASE+ 0x09)
860 #define plb1_acr_ppm_mask 0xF0000000
861 #define plb1_acr_ppm_fixed 0x00000000
862 #define plb1_acr_ppm_fair 0xD0000000
863 #define plb1_acr_hbu_mask 0x08000000
864 #define plb1_acr_hbu_disabled 0x00000000
865 #define plb1_acr_hbu_enabled 0x08000000
866 #define plb1_acr_rdp_mask 0x06000000
867 #define plb1_acr_rdp_disabled 0x00000000
868 #define plb1_acr_rdp_2deep 0x02000000
869 #define plb1_acr_rdp_3deep 0x04000000
870 #define plb1_acr_rdp_4deep 0x06000000
871 #define plb1_acr_wrp_mask 0x01000000
872 #define plb1_acr_wrp_disabled 0x00000000
873 #define plb1_acr_wrp_2deep 0x01000000
875 #define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
876 #define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
877 #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
878 #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
880 /* Pin Function Control Register 1 */
881 #define SDR0_PFC1 0x4101
882 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
883 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
884 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
885 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
886 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
887 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
888 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
889 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
890 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
891 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
892 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
893 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
894 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
895 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
896 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
897 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
898 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
899 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
900 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
901 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
902 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
903 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
904 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
905 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
907 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
908 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
909 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
910 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
912 /* USB Control Register */
913 #define SDR0_USB0 0x0320
914 #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
915 #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
916 #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
917 #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
918 #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
919 #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
921 /* CUST0 Customer Configuration Register0 */
922 #define SDR0_CUST0 0x4000
923 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
924 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
925 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
926 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
928 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
929 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
930 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
932 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
933 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
934 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
936 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
937 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
938 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
940 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
941 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
942 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
944 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
945 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
946 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
948 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
949 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
950 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
952 #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
953 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
954 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
956 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
957 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
958 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
959 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
960 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
961 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
962 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
964 /* CUST1 Customer Configuration Register1 */
965 #define SDR0_CUST1 0x4002
966 #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
967 #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
968 #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
970 /* Pin Function Control Register 0 */
971 #define SDR0_PFC0 0x4100
972 #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
973 #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
974 #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
975 #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
976 #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
978 /* Pin Function Control Register 1 */
979 #define SDR0_PFC1 0x4101
980 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
981 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
982 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
983 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
984 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
985 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
986 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
987 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
988 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
989 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
990 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
991 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
992 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
993 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
994 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
995 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
996 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
997 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
998 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
999 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
1000 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
1001 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
1002 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
1003 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
1005 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
1006 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
1007 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
1008 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
1010 /* Miscealleneaous Function Reg. */
1011 #define SDR0_MFR 0x4300
1012 #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
1013 #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
1014 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1015 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1016 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1017 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1018 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1019 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1020 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1021 #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1022 #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
1024 #define SDR0_MFR_ERRATA3_EN0 0x00800000
1025 #define SDR0_MFR_ERRATA3_EN1 0x00400000
1026 #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
1027 #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1028 #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
1029 #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
1030 #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
1034 /*-----------------------------------------------------------------------------
1036 +----------------------------------------------------------------------------*/
1037 #define ISRAM0_DCR_BASE 0x020
1038 #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
1039 #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
1040 #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
1041 #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
1042 #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
1043 #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
1044 #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
1045 #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
1046 #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
1047 #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
1048 #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
1050 /*-----------------------------------------------------------------------------
1052 +----------------------------------------------------------------------------*/
1053 #if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1054 #define L2_CACHE_BASE 0x030
1055 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
1056 #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
1057 #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
1058 #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
1059 #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
1060 #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
1061 #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
1062 #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
1064 #endif /* CONFIG_440GX */
1065 #endif /* !CONFIG_440EP !CONFIG_440GR*/
1067 /*-----------------------------------------------------------------------------
1069 +----------------------------------------------------------------------------*/
1070 /* TODO: as needed */
1072 /*-----------------------------------------------------------------------------
1073 | Clocking, Power Management and Chip Control
1074 +----------------------------------------------------------------------------*/
1075 #define CNTRL_DCR_BASE 0x0b0
1076 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1077 #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
1078 #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
1079 #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
1081 #define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
1082 #define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
1083 #define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
1086 #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
1087 #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
1088 #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
1089 #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
1091 #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
1092 #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
1093 #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
1094 #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
1096 #define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
1098 #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
1099 #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
1101 /*-----------------------------------------------------------------------------
1102 | Universal interrupt controller
1103 +----------------------------------------------------------------------------*/
1104 #define UIC0_DCR_BASE 0xc0
1105 #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
1106 #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
1107 #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
1108 #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
1109 #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
1110 #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
1111 #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
1112 #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
1114 #define UIC1_DCR_BASE 0xd0
1115 #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
1116 #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
1117 #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
1118 #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
1119 #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
1120 #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
1121 #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
1122 #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
1124 #if defined(CONFIG_440SPE)
1125 #define UIC2_DCR_BASE 0xe0
1126 #define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */
1127 #define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */
1128 #define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */
1129 #define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */
1130 #define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */
1131 #define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */
1132 #define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */
1133 #define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */
1134 #define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */
1136 #define UIC3_DCR_BASE 0xf0
1137 #define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */
1138 #define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */
1139 #define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */
1140 #define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */
1141 #define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */
1142 #define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */
1143 #define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */
1144 #define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */
1145 #define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */
1146 #endif /* CONFIG_440SPE */
1148 #if defined(CONFIG_440GX)
1149 #define UIC2_DCR_BASE 0x210
1150 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
1151 #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
1152 #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
1153 #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
1154 #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
1155 #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
1156 #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
1157 #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
1160 #define UIC_DCR_BASE 0x200
1161 #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
1162 #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
1163 #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
1164 #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
1165 #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
1166 #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
1167 #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
1168 #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
1169 #endif /* CONFIG_440GX */
1171 /* The following is for compatibility with 405 code */
1172 #define uicsr uic0sr
1173 #define uicer uic0er
1174 #define uiccr uic0cr
1175 #define uicpr uic0pr
1176 #define uictr uic0tr
1177 #define uicmsr uic0msr
1178 #define uicvr uic0vr
1179 #define uicvcr uic0vcr
1181 #if defined(CONFIG_440SPE)
1182 /*----------------------------------------------------------------------------+
1183 | Clock / Power-on-reset DCR's.
1184 +----------------------------------------------------------------------------*/
1185 #define CPR0_CFGADDR 0x00C
1186 #define CPR0_CFGDATA 0x00D
1188 #define CPR0_CLKUPD 0x20
1189 #define CPR0_CLKUPD_BSY_MASK 0x80000000
1190 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
1191 #define CPR0_CLKUPD_BSY_BUSY 0x80000000
1192 #define CPR0_CLKUPD_CUI_MASK 0x80000000
1193 #define CPR0_CLKUPD_CUI_DISABLE 0x00000000
1194 #define CPR0_CLKUPD_CUI_ENABLE 0x80000000
1195 #define CPR0_CLKUPD_CUD_MASK 0x40000000
1196 #define CPR0_CLKUPD_CUD_DISABLE 0x00000000
1197 #define CPR0_CLKUPD_CUD_ENABLE 0x40000000
1199 #define CPR0_PLLC 0x40
1200 #define CPR0_PLLC_RST_MASK 0x80000000
1201 #define CPR0_PLLC_RST_PLLLOCKED 0x00000000
1202 #define CPR0_PLLC_RST_PLLRESET 0x80000000
1203 #define CPR0_PLLC_ENG_MASK 0x40000000
1204 #define CPR0_PLLC_ENG_DISABLE 0x00000000
1205 #define CPR0_PLLC_ENG_ENABLE 0x40000000
1206 #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1207 #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1208 #define CPR0_PLLC_SRC_MASK 0x20000000
1209 #define CPR0_PLLC_SRC_PLLOUTA 0x00000000
1210 #define CPR0_PLLC_SRC_PLLOUTB 0x20000000
1211 #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1212 #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1213 #define CPR0_PLLC_SEL_MASK 0x07000000
1214 #define CPR0_PLLC_SEL_PLLOUT 0x00000000
1215 #define CPR0_PLLC_SEL_CPU 0x01000000
1216 #define CPR0_PLLC_SEL_EBC 0x05000000
1217 #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1218 #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
1219 #define CPR0_PLLC_TUNE_MASK 0x000003FF
1220 #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
1221 #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
1223 #define CPR0_PLLD 0x60
1224 #define CPR0_PLLD_FBDV_MASK 0x1F000000
1225 #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
1226 #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
1227 #define CPR0_PLLD_FWDVA_MASK 0x000F0000
1228 #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
1229 #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
1230 #define CPR0_PLLD_FWDVB_MASK 0x00000700
1231 #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
1232 #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
1233 #define CPR0_PLLD_LFBDV_MASK 0x0000003F
1234 #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1235 #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1237 #define CPR0_PRIMAD 0x80
1238 #define CPR0_PRIMAD_PRADV0_MASK 0x07000000
1239 #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1240 #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1242 #define CPR0_PRIMBD 0xA0
1243 #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
1244 #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1245 #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1247 #define CPR0_OPBD 0xC0
1248 #define CPR0_OPBD_OPBDV0_MASK 0x03000000
1249 #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1250 #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1252 #define CPR0_PERD 0xE0
1253 #define CPR0_PERD_PERDV0_MASK 0x03000000
1254 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1255 #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1257 #define CPR0_MALD 0x100
1258 #define CPR0_MALD_MALDV0_MASK 0x03000000
1259 #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1260 #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1262 #define CPR0_ICFG 0x140
1263 #define CPR0_ICFG_RLI_MASK 0x80000000
1264 #define CPR0_ICFG_RLI_RESETCPR 0x00000000
1265 #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
1266 #define CPR0_ICFG_ICS_MASK 0x00000007
1267 #define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1268 #define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1270 /************************/
1272 /************************/
1273 #define IIC0_MMIO_BASE 0xA0000400
1274 #define IIC1_MMIO_BASE 0xA0000500
1276 #endif /* CONFIG_440SP */
1278 /*-----------------------------------------------------------------------------
1280 +----------------------------------------------------------------------------*/
1281 #define DMA_DCR_BASE 0x100
1282 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
1283 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
1284 #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
1285 #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
1286 #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
1287 #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
1288 #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
1289 #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
1290 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
1291 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
1292 #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
1293 #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
1294 #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
1295 #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
1296 #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
1297 #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
1298 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
1299 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
1300 #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
1301 #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
1302 #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
1303 #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
1304 #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
1305 #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
1306 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
1307 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
1308 #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
1309 #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
1310 #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
1311 #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
1312 #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
1313 #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
1314 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
1315 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
1316 #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
1317 #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
1319 /*-----------------------------------------------------------------------------
1320 | Memory Access Layer
1321 +----------------------------------------------------------------------------*/
1322 #define MAL_DCR_BASE 0x180
1323 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
1324 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
1325 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
1326 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
1327 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
1328 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
1329 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
1330 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
1331 #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
1332 #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
1333 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
1334 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
1335 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
1336 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
1337 #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
1338 #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
1339 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
1340 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
1341 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
1342 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
1343 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
1344 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
1345 #if defined(CONFIG_440GX)
1346 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
1347 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
1348 #endif /* CONFIG_440GX */
1349 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1350 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
1351 #if defined(CONFIG_440GX)
1352 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
1353 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
1354 #endif /* CONFIG_440GX */
1357 /*---------------------------------------------------------------------------+
1358 | Universal interrupt controller 0 interrupts (UIC0)
1359 +---------------------------------------------------------------------------*/
1360 #if defined(CONFIG_440SP)
1361 #define UIC_U0 0x80000000 /* UART 0 */
1362 #define UIC_U1 0x40000000 /* UART 1 */
1363 #define UIC_IIC0 0x20000000 /* IIC */
1364 #define UIC_IIC1 0x10000000 /* IIC */
1365 #define UIC_PIM 0x08000000 /* PCI0 inbound message */
1366 #define UIC_PCRW 0x04000000 /* PCI0 command write register */
1367 #define UIC_PPM 0x02000000 /* PCI0 power management */
1368 #define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
1369 #define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
1370 #define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
1371 #define UIC_P1CRW 0x00200000 /* PCI1 command write register */
1372 #define UIC_P1PM 0x00100000 /* PCI1 power management */
1373 #define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
1374 #define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
1375 #define UIC_P2IM 0x00020000 /* PCI2 inbound message */
1376 #define UIC_P2CRW 0x00010000 /* PCI2 command register write */
1377 #define UIC_P2PM 0x00008000 /* PCI2 power management */
1378 #define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
1379 #define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
1380 #define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
1381 #define UIC_D0CSF 0x00000800 /* DMA0 command status */
1382 #define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
1383 #define UIC_D1CSF 0x00000200 /* DMA1 command status */
1384 #define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
1385 #define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
1386 #define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
1387 #define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
1388 #define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
1389 #define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
1390 #define UIC_GPTCT 0x00000004 /* GPT count timer */
1391 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1392 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1393 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
1394 #define UIC_U0 0x80000000 /* UART 0 */
1395 #define UIC_U1 0x40000000 /* UART 1 */
1396 #define UIC_IIC0 0x20000000 /* IIC */
1397 #define UIC_IIC1 0x10000000 /* IIC */
1398 #define UIC_PIM 0x08000000 /* PCI inbound message */
1399 #define UIC_PCRW 0x04000000 /* PCI command register write */
1400 #define UIC_PPM 0x02000000 /* PCI power management */
1401 #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
1402 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1403 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1404 #define UIC_MTE 0x00200000 /* MAL TXEOB */
1405 #define UIC_MRE 0x00100000 /* MAL RXEOB */
1406 #define UIC_D0 0x00080000 /* DMA channel 0 */
1407 #define UIC_D1 0x00040000 /* DMA channel 1 */
1408 #define UIC_D2 0x00020000 /* DMA channel 2 */
1409 #define UIC_D3 0x00010000 /* DMA channel 3 */
1410 #define UIC_RSVD0 0x00008000 /* Reserved */
1411 #define UIC_RSVD1 0x00004000 /* Reserved */
1412 #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
1413 #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
1414 #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
1415 #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
1416 #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
1417 #define UIC_EIR0 0x00000100 /* External interrupt 0 */
1418 #define UIC_EIR1 0x00000080 /* External interrupt 1 */
1419 #define UIC_EIR2 0x00000040 /* External interrupt 2 */
1420 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
1421 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
1422 #define UIC_EIR5 0x00000008 /* External interrupt 5 */
1423 #define UIC_EIR6 0x00000004 /* External interrupt 6 */
1424 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1425 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1426 #elif !defined(CONFIG_440SPE)
1427 #define UIC_U0 0x80000000 /* UART 0 */
1428 #define UIC_U1 0x40000000 /* UART 1 */
1429 #define UIC_IIC0 0x20000000 /* IIC */
1430 #define UIC_IIC1 0x10000000 /* IIC */
1431 #define UIC_PIM 0x08000000 /* PCI inbound message */
1432 #define UIC_PCRW 0x04000000 /* PCI command register write */
1433 #define UIC_PPM 0x02000000 /* PCI power management */
1434 #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
1435 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1436 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1437 #define UIC_MTE 0x00200000 /* MAL TXEOB */
1438 #define UIC_MRE 0x00100000 /* MAL RXEOB */
1439 #define UIC_D0 0x00080000 /* DMA channel 0 */
1440 #define UIC_D1 0x00040000 /* DMA channel 1 */
1441 #define UIC_D2 0x00020000 /* DMA channel 2 */
1442 #define UIC_D3 0x00010000 /* DMA channel 3 */
1443 #define UIC_RSVD0 0x00008000 /* Reserved */
1444 #define UIC_RSVD1 0x00004000 /* Reserved */
1445 #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
1446 #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
1447 #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
1448 #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
1449 #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
1450 #define UIC_EIR0 0x00000100 /* External interrupt 0 */
1451 #define UIC_EIR1 0x00000080 /* External interrupt 1 */
1452 #define UIC_EIR2 0x00000040 /* External interrupt 2 */
1453 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
1454 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
1455 #define UIC_EIR5 0x00000008 /* External interrupt 5 */
1456 #define UIC_EIR6 0x00000004 /* External interrupt 6 */
1457 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1458 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1459 #endif /* CONFIG_440GX */
1461 /* For compatibility with 405 code */
1462 #define UIC_MAL_TXEOB UIC_MTE
1463 #define UIC_MAL_RXEOB UIC_MRE
1465 /*---------------------------------------------------------------------------+
1466 | Universal interrupt controller 1 interrupts (UIC1)
1467 +---------------------------------------------------------------------------*/
1468 #if defined(CONFIG_440SP)
1469 #define UIC_EIR0 0x80000000 /* External interrupt 0 */
1470 #define UIC_MS 0x40000000 /* MAL SERR */
1471 #define UIC_MTDE 0x20000000 /* MAL TXDE */
1472 #define UIC_MRDE 0x10000000 /* MAL RXDE */
1473 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1474 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1475 #define UIC_MTE 0x02000000 /* MAL TXEOB */
1476 #define UIC_MRE 0x01000000 /* MAL RXEOB */
1477 #define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
1478 #define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
1479 #define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
1480 #define UIC_L2C 0x00100000 /* L2 cache */
1481 #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
1482 #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
1483 #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
1484 #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
1485 #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
1486 #define UIC_EIR1 0x00004000 /* External interrupt 1 */
1487 #define UIC_EIR2 0x00002000 /* External interrupt 2 */
1488 #define UIC_EIR3 0x00001000 /* External interrupt 3 */
1489 #define UIC_EIR4 0x00000800 /* External interrupt 4 */
1490 #define UIC_EIR5 0x00000400 /* External interrupt 5 */
1491 #define UIC_DMAE 0x00000200 /* DMA error */
1492 #define UIC_I2OE 0x00000100 /* I2O error */
1493 #define UIC_SRE 0x00000080 /* Serial ROM error */
1494 #define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
1495 #define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
1496 #define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
1497 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1498 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1499 #define UIC_ETH1 0x00000002 /* Reserved */
1500 #define UIC_XOR 0x00000001 /* XOR */
1501 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
1502 #define UIC_MS 0x80000000 /* MAL SERR */
1503 #define UIC_MTDE 0x40000000 /* MAL TXDE */
1504 #define UIC_MRDE 0x20000000 /* MAL RXDE */
1505 #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
1506 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1507 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1508 #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
1509 #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
1510 #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
1511 #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
1512 #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
1513 #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
1514 #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
1515 #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
1516 #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
1517 #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
1518 #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
1519 #define UIC_PPMI 0x00004000 /* PPM interrupt status */
1520 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
1521 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
1522 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1523 #define UIC_EIR10 0x00000400 /* External interrupt 10 */
1524 #define UIC_EIR11 0x00000200 /* External interrupt 11 */
1525 #define UIC_EIR12 0x00000100 /* External interrupt 12 */
1526 #define UIC_SRE 0x00000080 /* Serial ROM error */
1527 #define UIC_RSVD2 0x00000040 /* Reserved */
1528 #define UIC_RSVD3 0x00000020 /* Reserved */
1529 #define UIC_PAE 0x00000010 /* PCI asynchronous error */
1530 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1531 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1532 #define UIC_ETH1 0x00000002 /* Ethernet 1 */
1533 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1534 #elif !defined(CONFIG_440SPE)
1535 #define UIC_MS 0x80000000 /* MAL SERR */
1536 #define UIC_MTDE 0x40000000 /* MAL TXDE */
1537 #define UIC_MRDE 0x20000000 /* MAL RXDE */
1538 #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
1539 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1540 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1541 #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
1542 #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
1543 #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
1544 #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
1545 #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
1546 #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
1547 #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
1548 #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
1549 #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
1550 #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
1551 #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
1552 #define UIC_PPMI 0x00004000 /* PPM interrupt status */
1553 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
1554 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
1555 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1556 #define UIC_EIR10 0x00000400 /* External interrupt 10 */
1557 #define UIC_EIR11 0x00000200 /* External interrupt 11 */
1558 #define UIC_EIR12 0x00000100 /* External interrupt 12 */
1559 #define UIC_SRE 0x00000080 /* Serial ROM error */
1560 #define UIC_RSVD2 0x00000040 /* Reserved */
1561 #define UIC_RSVD3 0x00000020 /* Reserved */
1562 #define UIC_PAE 0x00000010 /* PCI asynchronous error */
1563 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1564 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1565 #define UIC_ETH1 0x00000002 /* Ethernet 1 */
1566 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1567 #endif /* CONFIG_440SP */
1569 /* For compatibility with 405 code */
1570 #define UIC_MAL_SERR UIC_MS
1571 #define UIC_MAL_TXDE UIC_MTDE
1572 #define UIC_MAL_RXDE UIC_MRDE
1573 #define UIC_ENET UIC_ETH0
1575 /*---------------------------------------------------------------------------+
1576 | Universal interrupt controller 2 interrupts (UIC2)
1577 +---------------------------------------------------------------------------*/
1578 #if defined(CONFIG_440GX)
1579 #define UIC_ETH2 0x80000000 /* Ethernet 2 */
1580 #define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
1581 #define UIC_ETH3 0x20000000 /* Ethernet 3 */
1582 #define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
1583 #define UIC_TAH0 0x08000000 /* TAH 0 */
1584 #define UIC_TAH1 0x04000000 /* TAH 1 */
1585 #define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
1586 #define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
1587 #define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
1588 #define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
1589 #define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
1590 #define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
1591 #define UIC_IMUTO 0x00080000 /* IMU timeout */
1592 #define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
1593 #define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
1594 #define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
1595 #define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
1596 #define UIC_EIR13 0x00004000 /* External interrupt 13 */
1597 #define UIC_EIR14 0x00002000 /* External interrupt 14 */
1598 #define UIC_EIR15 0x00001000 /* External interrupt 15 */
1599 #define UIC_EIR16 0x00000800 /* External interrupt 16 */
1600 #define UIC_EIR17 0x00000400 /* External interrupt 17 */
1601 #define UIC_PCIVPD 0x00000200 /* PCI VPD */
1602 #define UIC_L2C 0x00000100 /* L2 Cache */
1603 #define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
1604 #define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
1605 #define UIC_RSVD26 0x00000020 /* Reserved */
1606 #define UIC_RSVD27 0x00000010 /* Reserved */
1607 #define UIC_RSVD28 0x00000008 /* Reserved */
1608 #define UIC_RSVD29 0x00000004 /* Reserved */
1609 #define UIC_RSVD30 0x00000002 /* Reserved */
1610 #define UIC_RSVD31 0x00000001 /* Reserved */
1611 #endif /* CONFIG_440GX */
1613 /*---------------------------------------------------------------------------+
1614 | Universal interrupt controller Base 0 interrupts (UICB0)
1615 +---------------------------------------------------------------------------*/
1616 #if defined(CONFIG_440GX)
1617 #define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
1618 #define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
1619 #define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
1620 #define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
1621 #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
1622 #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
1624 #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
1625 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
1626 #endif /* CONFIG_440GX */
1627 /*---------------------------------------------------------------------------+
1628 | Universal interrupt controller interrupts
1629 +---------------------------------------------------------------------------*/
1630 #if defined(CONFIG_440SPE)
1631 /*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
1632 /*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
1633 #define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
1634 #define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
1635 #define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
1636 #define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
1637 #define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
1638 #define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
1640 #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
1641 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
1642 /*---------------------------------------------------------------------------+
1643 | Universal interrupt controller 0 interrupts (UIC0)
1644 +---------------------------------------------------------------------------*/
1645 #define UIC_U0 0x80000000 /* UART 0 */
1646 #define UIC_U1 0x40000000 /* UART 1 */
1647 #define UIC_IIC0 0x20000000 /* IIC */
1648 #define UIC_IIC1 0x10000000 /* IIC */
1649 #define UIC_PIM 0x08000000 /* PCI inbound message */
1650 #define UIC_PCRW 0x04000000 /* PCI command register write */
1651 #define UIC_PPM 0x02000000 /* PCI power management */
1652 #define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
1653 #define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
1654 #define UIC_EIR15 0x00400000 /* External intp 15 */
1655 #define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
1656 #define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
1657 #define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
1658 #define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
1659 #define UIC_EIR14 0x00002000 /* External interrupt 14 */
1660 #define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
1661 #define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
1662 #define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
1663 #define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
1664 #define UIC_I2OID 0x00000100 /* I2O inbound door bell */
1665 #define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
1666 #define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
1667 #define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
1668 #define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
1669 #define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
1670 #define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
1671 /*---------------------------------------------------------------------------+
1672 | Universal interrupt controller 1 interrupts (UIC1)
1673 +---------------------------------------------------------------------------*/
1674 #define UIC_EIR13 0x80000000 /* externei intp 13 */
1675 #define UIC_MS 0x40000000 /* MAL SERR */
1676 #define UIC_MTDE 0x20000000 /* MAL TXDE */
1677 #define UIC_MRDE 0x10000000 /* MAL RXDE */
1678 #define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
1679 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1680 #define UIC_MTE 0x02000000 /* MAL TXEOB */
1681 #define UIC_MRE 0x01000000 /* MAL RXEOB */
1682 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1683 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1684 #define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
1685 #define UIC_L2C 0x00100000 /* L2 cache */
1686 #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
1687 #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
1688 #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
1689 #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
1690 #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
1691 #define UIC_EIR12 0x00004000 /* External interrupt 12 */
1692 #define UIC_EIR11 0x00002000 /* External interrupt 11 */
1693 #define UIC_EIR10 0x00001000 /* External interrupt 10 */
1694 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1695 #define UIC_EIR8 0x00000400 /* External interrupt 8 */
1696 #define UIC_DMAE 0x00000200 /* dma error */
1697 #define UIC_I2OE 0x00000100 /* i2o error */
1698 #define UIC_SRE 0x00000080 /* Serial ROM error */
1699 #define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
1700 #define UIC_EIR7 0x00000020 /* External interrupt 7 */
1701 #define UIC_EIR6 0x00000010 /* External interrupt 6 */
1702 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1703 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1704 #define UIC_ETH1 0x00000002 /* reserved */
1705 #define UIC_XOR 0x00000001 /* xor */
1707 /*---------------------------------------------------------------------------+
1708 | Universal interrupt controller 2 interrupts (UIC2)
1709 +---------------------------------------------------------------------------*/
1710 #define UIC_PEOAL 0x80000000 /* PE0 AL */
1711 #define UIC_PEOVA 0x40000000 /* PE0 VPD access */
1712 #define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
1713 #define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
1714 #define UIC_PE0TCR 0x08000000 /* PE0 TCR */
1715 #define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
1716 #define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
1717 #define UIC_PE1AL 0x00800000 /* PE1 AL */
1718 #define UIC_PE1VA 0x00400000 /* PE1 VPD access */
1719 #define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
1720 #define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
1721 #define UIC_PE1TCR 0x00080000 /* PE1 TCR */
1722 #define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
1723 #define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
1724 #define UIC_PE2AL 0x00008000 /* PE2 AL */
1725 #define UIC_PE2VA 0x00004000 /* PE2 VPD access */
1726 #define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
1727 #define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
1728 #define UIC_PE2TCR 0x00000800 /* PE2 TCR */
1729 #define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
1730 #define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
1731 #define UIC_EIR5 0x00000080 /* External interrupt 5 */
1732 #define UIC_EIR4 0x00000040 /* External interrupt 4 */
1733 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
1734 #define UIC_EIR2 0x00000010 /* External interrupt 2 */
1735 #define UIC_EIR1 0x00000008 /* External interrupt 1 */
1736 #define UIC_EIR0 0x00000004 /* External interrupt 0 */
1737 #endif /* CONFIG_440SPE */
1739 /*-----------------------------------------------------------------------------+
1740 | External Bus Controller Bit Settings
1741 +-----------------------------------------------------------------------------*/
1742 #define EBC_CFGADDR_MASK 0x0000003F
1744 #define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
1745 #define EBC_BXCR_BS_MASK 0x000E0000
1746 #define EBC_BXCR_BS_1MB 0x00000000
1747 #define EBC_BXCR_BS_2MB 0x00020000
1748 #define EBC_BXCR_BS_4MB 0x00040000
1749 #define EBC_BXCR_BS_8MB 0x00060000
1750 #define EBC_BXCR_BS_16MB 0x00080000
1751 #define EBC_BXCR_BS_32MB 0x000A0000
1752 #define EBC_BXCR_BS_64MB 0x000C0000
1753 #define EBC_BXCR_BS_128MB 0x000E0000
1754 #define EBC_BXCR_BU_MASK 0x00018000
1755 #define EBC_BXCR_BU_R 0x00008000
1756 #define EBC_BXCR_BU_W 0x00010000
1757 #define EBC_BXCR_BU_RW 0x00018000
1758 #define EBC_BXCR_BW_MASK 0x00006000
1759 #define EBC_BXCR_BW_8BIT 0x00000000
1760 #define EBC_BXCR_BW_16BIT 0x00002000
1761 #define EBC_BXCR_BW_32BIT 0x00006000
1762 #define EBC_BXAP_BME_ENABLED 0x80000000
1763 #define EBC_BXAP_BME_DISABLED 0x00000000
1764 #define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
1765 #define EBC_BXAP_BCE_DISABLE 0x00000000
1766 #define EBC_BXAP_BCE_ENABLE 0x00400000
1767 #define EBC_BXAP_BCT_MASK 0x00300000
1768 #define EBC_BXAP_BCT_2TRANS 0x00000000
1769 #define EBC_BXAP_BCT_4TRANS 0x00100000
1770 #define EBC_BXAP_BCT_8TRANS 0x00200000
1771 #define EBC_BXAP_BCT_16TRANS 0x00300000
1772 #define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
1773 #define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
1774 #define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
1775 #define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12)
1776 #define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9)
1777 #define EBC_BXAP_RE_ENABLED 0x00000100
1778 #define EBC_BXAP_RE_DISABLED 0x00000000
1779 #define EBC_BXAP_SOR_DELAYED 0x00000000
1780 #define EBC_BXAP_SOR_NONDELAYED 0x00000080
1781 #define EBC_BXAP_BEM_WRITEONLY 0x00000000
1782 #define EBC_BXAP_BEM_RW 0x00000040
1783 #define EBC_BXAP_PEN_DISABLED 0x00000000
1785 #define EBC_CFG_LE_MASK 0x80000000
1786 #define EBC_CFG_LE_UNLOCK 0x00000000
1787 #define EBC_CFG_LE_LOCK 0x80000000
1788 #define EBC_CFG_PTD_MASK 0x40000000
1789 #define EBC_CFG_PTD_ENABLE 0x00000000
1790 #define EBC_CFG_PTD_DISABLE 0x40000000
1791 #define EBC_CFG_RTC_MASK 0x38000000
1792 #define EBC_CFG_RTC_16PERCLK 0x00000000
1793 #define EBC_CFG_RTC_32PERCLK 0x08000000
1794 #define EBC_CFG_RTC_64PERCLK 0x10000000
1795 #define EBC_CFG_RTC_128PERCLK 0x18000000
1796 #define EBC_CFG_RTC_256PERCLK 0x20000000
1797 #define EBC_CFG_RTC_512PERCLK 0x28000000
1798 #define EBC_CFG_RTC_1024PERCLK 0x30000000
1799 #define EBC_CFG_RTC_2048PERCLK 0x38000000
1800 #define EBC_CFG_ATC_MASK 0x04000000
1801 #define EBC_CFG_ATC_HI 0x00000000
1802 #define EBC_CFG_ATC_PREVIOUS 0x04000000
1803 #define EBC_CFG_DTC_MASK 0x02000000
1804 #define EBC_CFG_DTC_HI 0x00000000
1805 #define EBC_CFG_DTC_PREVIOUS 0x02000000
1806 #define EBC_CFG_CTC_MASK 0x01000000
1807 #define EBC_CFG_CTC_HI 0x00000000
1808 #define EBC_CFG_CTC_PREVIOUS 0x01000000
1809 #define EBC_CFG_OEO_MASK 0x00800000
1810 #define EBC_CFG_OEO_HI 0x00000000
1811 #define EBC_CFG_OEO_PREVIOUS 0x00800000
1812 #define EBC_CFG_EMC_MASK 0x00400000
1813 #define EBC_CFG_EMC_NONDEFAULT 0x00000000
1814 #define EBC_CFG_EMC_DEFAULT 0x00400000
1815 #define EBC_CFG_PME_MASK 0x00200000
1816 #define EBC_CFG_PME_DISABLE 0x00000000
1817 #define EBC_CFG_PME_ENABLE 0x00200000
1818 #define EBC_CFG_PMT_MASK 0x001F0000
1819 #define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
1820 #define EBC_CFG_PR_MASK 0x0000C000
1821 #define EBC_CFG_PR_16 0x00000000
1822 #define EBC_CFG_PR_32 0x00004000
1823 #define EBC_CFG_PR_64 0x00008000
1824 #define EBC_CFG_PR_128 0x0000C000
1826 /*-----------------------------------------------------------------------------+
1828 +-----------------------------------------------------------------------------*/
1829 #if defined(CONFIG_440SPE)
1830 #define SDR0_CP440 0x0180
1831 #define SDR0_CP440_ERPN_MASK 0x30000000
1832 #define SDR0_CP440_ERPN_MASK_HI 0x3000
1833 #define SDR0_CP440_ERPN_MASK_LO 0x0000
1834 #define SDR0_CP440_ERPN_EBC 0x10000000
1835 #define SDR0_CP440_ERPN_EBC_HI 0x1000
1836 #define SDR0_CP440_ERPN_EBC_LO 0x0000
1837 #define SDR0_CP440_ERPN_PCI 0x20000000
1838 #define SDR0_CP440_ERPN_PCI_HI 0x2000
1839 #define SDR0_CP440_ERPN_PCI_LO 0x0000
1840 #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1841 #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1842 #define SDR0_CP440_NTO1_MASK 0x00000002
1843 #define SDR0_CP440_NTO1_NTOP 0x00000000
1844 #define SDR0_CP440_NTO1_NTO1 0x00000002
1845 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1846 #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
1847 #define SDR0_CFGADDR 0x00E /*already defined line 277 */
1848 #define SDR0_CFGDATA 0x00F
1851 #define SDR0_SDSTP0 0x0020
1852 #define SDR0_SDSTP0_ENG_MASK 0x80000000
1853 #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
1854 #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
1855 #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1856 #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1857 #define SDR0_SDSTP0_SRC_MASK 0x40000000
1858 #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
1859 #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
1860 #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1861 #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1862 #define SDR0_SDSTP0_SEL_MASK 0x38000000
1863 #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
1864 #define SDR0_SDSTP0_SEL_CPU 0x08000000
1865 #define SDR0_SDSTP0_SEL_EBC 0x28000000
1866 #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
1867 #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
1868 #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
1869 #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
1870 #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
1871 #define SDR0_SDSTP0_FBDV_MASK 0x0001F000
1872 #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
1873 #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
1874 #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
1875 #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
1876 #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
1877 #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
1878 #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
1879 #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
1880 #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
1881 #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
1882 #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
1883 #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
1884 #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
1885 #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
1888 #define SDR0_SDSTP1 0x0021
1889 #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
1890 #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
1891 #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
1892 #define SDR0_SDSTP1_PERDV0_MASK 0x03000000
1893 #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1894 #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
1895 #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
1896 #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
1897 #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1898 #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
1899 #define SDR0_SDSTP1_DDR1_MODE 0x00100000
1900 #define SDR0_SDSTP1_DDR2_MODE 0x00200000
1901 #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
1902 #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
1903 #define SDR0_SDSTP1_ERPN_MASK 0x00080000
1904 #define SDR0_SDSTP1_ERPN_EBC 0x00000000
1905 #define SDR0_SDSTP1_ERPN_PCI 0x00080000
1906 #define SDR0_SDSTP1_PAE_MASK 0x00040000
1907 #define SDR0_SDSTP1_PAE_DISABLE 0x00000000
1908 #define SDR0_SDSTP1_PAE_ENABLE 0x00040000
1909 #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
1910 #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
1911 #define SDR0_SDSTP1_PHCE_MASK 0x00020000
1912 #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
1913 #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
1914 #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
1915 #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
1916 #define SDR0_SDSTP1_PISE_MASK 0x00010000
1917 #define SDR0_SDSTP1_PISE_DISABLE 0x00000000
1918 #define SDR0_SDSTP1_PISE_ENABLE 0x00001000
1919 #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
1920 #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
1921 #define SDR0_SDSTP1_PCWE_MASK 0x00008000
1922 #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
1923 #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
1924 #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
1925 #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
1926 #define SDR0_SDSTP1_PPIM_MASK 0x00007800
1927 #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
1928 #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
1929 #define SDR0_SDSTP1_PR64E_MASK 0x00000400
1930 #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
1931 #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
1932 #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
1933 #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
1934 #define SDR0_SDSTP1_PXFS_MASK 0x00000300
1935 #define SDR0_SDSTP1_PXFS_100_133 0x00000000
1936 #define SDR0_SDSTP1_PXFS_66_100 0x00000100
1937 #define SDR0_SDSTP1_PXFS_50_66 0x00000200
1938 #define SDR0_SDSTP1_PXFS_0_50 0x00000300
1939 #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
1940 #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
1941 #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
1942 #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
1943 #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
1944 #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
1945 #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
1946 #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
1947 #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
1948 #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
1949 #define SDR0_SDSTP1_ETH_MASK 0x00000004
1950 #define SDR0_SDSTP1_ETH_10_100 0x00000000
1951 #define SDR0_SDSTP1_ETH_GIGA 0x00000004
1952 #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
1953 #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
1954 #define SDR0_SDSTP1_NTO1_MASK 0x00000001
1955 #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
1956 #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
1957 #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
1958 #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
1960 #define SDR0_SDSTP2 0x0022
1961 #define SDR0_SDSTP2_P1AE_MASK 0x80000000
1962 #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
1963 #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
1964 #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1965 #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1966 #define SDR0_SDSTP2_P1HCE_MASK 0x40000000
1967 #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
1968 #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
1969 #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1970 #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1971 #define SDR0_SDSTP2_P1ISE_MASK 0x20000000
1972 #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
1973 #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
1974 #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1975 #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1976 #define SDR0_SDSTP2_P1CWE_MASK 0x10000000
1977 #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
1978 #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
1979 #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1980 #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1981 #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
1982 #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1983 #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1984 #define SDR0_SDSTP2_P1R64E_MASK 0x00800000
1985 #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
1986 #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
1987 #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1988 #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1989 #define SDR0_SDSTP2_P1XFS_MASK 0x00600000
1990 #define SDR0_SDSTP2_P1XFS_100_133 0x00000000
1991 #define SDR0_SDSTP2_P1XFS_66_100 0x00200000
1992 #define SDR0_SDSTP2_P1XFS_50_66 0x00400000
1993 #define SDR0_SDSTP2_P1XFS_0_50 0x00600000
1994 #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1995 #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1996 #define SDR0_SDSTP2_P2AE_MASK 0x00040000
1997 #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
1998 #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
1999 #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
2000 #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
2001 #define SDR0_SDSTP2_P2HCE_MASK 0x00020000
2002 #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
2003 #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
2004 #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
2005 #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
2006 #define SDR0_SDSTP2_P2ISE_MASK 0x00010000
2007 #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
2008 #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
2009 #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
2010 #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
2011 #define SDR0_SDSTP2_P2CWE_MASK 0x00008000
2012 #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
2013 #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
2014 #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
2015 #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
2016 #define SDR0_SDSTP2_P2PIM_MASK 0x00007800
2017 #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
2018 #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
2019 #define SDR0_SDSTP2_P2XFS_MASK 0x00000300
2020 #define SDR0_SDSTP2_P2XFS_100_133 0x00000000
2021 #define SDR0_SDSTP2_P2XFS_66_100 0x00000100
2022 #define SDR0_SDSTP2_P2XFS_50_66 0x00000200
2023 #define SDR0_SDSTP2_P2XFS_0_50 0x00000100
2024 #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
2025 #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
2027 #define SDR0_SDSTP3 0x0023
2029 #define SDR0_PINSTP 0x0040
2030 #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
2031 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
2032 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
2033 #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
2034 #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
2035 #define SDR0_SDCS 0x0060
2036 #define SDR0_ECID0 0x0080
2037 #define SDR0_ECID1 0x0081
2038 #define SDR0_ECID2 0x0082
2039 #define SDR0_JTAG 0x00C0
2041 #define SDR0_DDR0 0x00E1
2042 #define SDR0_DDR0_DPLLRST 0x80000000
2043 #define SDR0_DDR0_DDRM_MASK 0x60000000
2044 #define SDR0_DDR0_DDRM_DDR1 0x20000000
2045 #define SDR0_DDR0_DDRM_DDR2 0x40000000
2046 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
2047 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
2048 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
2049 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
2051 #define SDR0_UART0 0x0120
2052 #define SDR0_UART1 0x0121
2053 #define SDR0_UART2 0x0122
2054 #define SDR0_UARTX_UXICS_MASK 0xF0000000
2055 #define SDR0_UARTX_UXICS_PLB 0x20000000
2056 #define SDR0_UARTX_UXEC_MASK 0x00800000
2057 #define SDR0_UARTX_UXEC_INT 0x00000000
2058 #define SDR0_UARTX_UXEC_EXT 0x00800000
2059 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
2060 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
2061 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
2063 #define SDR0_CP440 0x0180
2064 #define SDR0_CP440_ERPN_MASK 0x30000000
2065 #define SDR0_CP440_ERPN_MASK_HI 0x3000
2066 #define SDR0_CP440_ERPN_MASK_LO 0x0000
2067 #define SDR0_CP440_ERPN_EBC 0x10000000
2068 #define SDR0_CP440_ERPN_EBC_HI 0x1000
2069 #define SDR0_CP440_ERPN_EBC_LO 0x0000
2070 #define SDR0_CP440_ERPN_PCI 0x20000000
2071 #define SDR0_CP440_ERPN_PCI_HI 0x2000
2072 #define SDR0_CP440_ERPN_PCI_LO 0x0000
2073 #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2074 #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2075 #define SDR0_CP440_NTO1_MASK 0x00000002
2076 #define SDR0_CP440_NTO1_NTOP 0x00000000
2077 #define SDR0_CP440_NTO1_NTO1 0x00000002
2078 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2079 #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2081 #define SDR0_XCR0 0x01C0
2082 #define SDR0_XCR1 0x01C3
2083 #define SDR0_XCR2 0x01C6
2084 #define SDR0_XCRn_PAE_MASK 0x80000000
2085 #define SDR0_XCRn_PAE_DISABLE 0x00000000
2086 #define SDR0_XCRn_PAE_ENABLE 0x80000000
2087 #define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2088 #define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2089 #define SDR0_XCRn_PHCE_MASK 0x40000000
2090 #define SDR0_XCRn_PHCE_DISABLE 0x00000000
2091 #define SDR0_XCRn_PHCE_ENABLE 0x40000000
2092 #define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2093 #define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2094 #define SDR0_XCRn_PISE_MASK 0x20000000
2095 #define SDR0_XCRn_PISE_DISABLE 0x00000000
2096 #define SDR0_XCRn_PISE_ENABLE 0x20000000
2097 #define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2098 #define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2099 #define SDR0_XCRn_PCWE_MASK 0x10000000
2100 #define SDR0_XCRn_PCWE_DISABLE 0x00000000
2101 #define SDR0_XCRn_PCWE_ENABLE 0x10000000
2102 #define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2103 #define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2104 #define SDR0_XCRn_PPIM_MASK 0x0F000000
2105 #define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2106 #define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2107 #define SDR0_XCRn_PR64E_MASK 0x00800000
2108 #define SDR0_XCRn_PR64E_DISABLE 0x00000000
2109 #define SDR0_XCRn_PR64E_ENABLE 0x00800000
2110 #define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2111 #define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2112 #define SDR0_XCRn_PXFS_MASK 0x00600000
2113 #define SDR0_XCRn_PXFS_100_133 0x00000000
2114 #define SDR0_XCRn_PXFS_66_100 0x00200000
2115 #define SDR0_XCRn_PXFS_50_66 0x00400000
2116 #define SDR0_XCRn_PXFS_0_33 0x00600000
2117 #define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2118 #define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2120 #define SDR0_XPLLC0 0x01C1
2121 #define SDR0_XPLLD0 0x01C2
2122 #define SDR0_XPLLC1 0x01C4
2123 #define SDR0_XPLLD1 0x01C5
2124 #define SDR0_XPLLC2 0x01C7
2125 #define SDR0_XPLLD2 0x01C8
2126 #define SDR0_SRST 0x0200
2127 #define SDR0_SLPIPE 0x0220
2129 #define SDR0_AMP0 0x0240
2130 #define SDR0_AMP0_PRIORITY 0xFFFF0000
2131 #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
2132 #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
2134 #define SDR0_AMP1 0x0241
2135 #define SDR0_AMP1_PRIORITY 0xFC000000
2136 #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
2137 #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
2139 #define SDR0_MIRQ0 0x0260
2140 #define SDR0_MIRQ1 0x0261
2141 #define SDR0_MALTBL 0x0280
2142 #define SDR0_MALRBL 0x02A0
2143 #define SDR0_MALTBS 0x02C0
2144 #define SDR0_MALRBS 0x02E0
2146 /* Reserved for Customer Use */
2147 #define SDR0_CUST0 0x4000
2148 #define SDR0_CUST0_AUTONEG_MASK 0x8000000
2149 #define SDR0_CUST0_NO_AUTONEG 0x0000000
2150 #define SDR0_CUST0_AUTONEG 0x8000000
2151 #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
2152 #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
2153 #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
2154 #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
2155 #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
2156 #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
2157 #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
2159 #define SDR0_SDSTP4 0x4001
2160 #define SDR0_CUST1 0x4002
2161 #define SDR0_SDSTP5 0x4003
2162 #define SDR0_CUST2 0x4004
2163 #define SDR0_SDSTP6 0x4005
2164 #define SDR0_CUST3 0x4006
2165 #define SDR0_SDSTP7 0x4007
2167 #define SDR0_PFC0 0x4100
2168 #define SDR0_PFC0_GPIO_0 0x80000000
2169 #define SDR0_PFC0_PCIX0REQ2_N 0x00000000
2170 #define SDR0_PFC0_GPIO_1 0x40000000
2171 #define SDR0_PFC0_PCIX0REQ3_N 0x00000000
2172 #define SDR0_PFC0_GPIO_2 0x20000000
2173 #define SDR0_PFC0_PCIX0GNT2_N 0x00000000
2174 #define SDR0_PFC0_GPIO_3 0x10000000
2175 #define SDR0_PFC0_PCIX0GNT3_N 0x00000000
2176 #define SDR0_PFC0_GPIO_4 0x08000000
2177 #define SDR0_PFC0_PCIX1REQ2_N 0x00000000
2178 #define SDR0_PFC0_GPIO_5 0x04000000
2179 #define SDR0_PFC0_PCIX1REQ3_N 0x00000000
2180 #define SDR0_PFC0_GPIO_6 0x02000000
2181 #define SDR0_PFC0_PCIX1GNT2_N 0x00000000
2182 #define SDR0_PFC0_GPIO_7 0x01000000
2183 #define SDR0_PFC0_PCIX1GNT3_N 0x00000000
2184 #define SDR0_PFC0_GPIO_8 0x00800000
2185 #define SDR0_PFC0_PERREADY 0x00000000
2186 #define SDR0_PFC0_GPIO_9 0x00400000
2187 #define SDR0_PFC0_PERCS1_N 0x00000000
2188 #define SDR0_PFC0_GPIO_10 0x00200000
2189 #define SDR0_PFC0_PERCS2_N 0x00000000
2190 #define SDR0_PFC0_GPIO_11 0x00100000
2191 #define SDR0_PFC0_IRQ0 0x00000000
2192 #define SDR0_PFC0_GPIO_12 0x00080000
2193 #define SDR0_PFC0_IRQ1 0x00000000
2194 #define SDR0_PFC0_GPIO_13 0x00040000
2195 #define SDR0_PFC0_IRQ2 0x00000000
2196 #define SDR0_PFC0_GPIO_14 0x00020000
2197 #define SDR0_PFC0_IRQ3 0x00000000
2198 #define SDR0_PFC0_GPIO_15 0x00010000
2199 #define SDR0_PFC0_IRQ4 0x00000000
2200 #define SDR0_PFC0_GPIO_16 0x00008000
2201 #define SDR0_PFC0_IRQ5 0x00000000
2202 #define SDR0_PFC0_GPIO_17 0x00004000
2203 #define SDR0_PFC0_PERBE0_N 0x00000000
2204 #define SDR0_PFC0_GPIO_18 0x00002000
2205 #define SDR0_PFC0_PCI0GNT0_N 0x00000000
2206 #define SDR0_PFC0_GPIO_19 0x00001000
2207 #define SDR0_PFC0_PCI0GNT1_N 0x00000000
2208 #define SDR0_PFC0_GPIO_20 0x00000800
2209 #define SDR0_PFC0_PCI0REQ0_N 0x00000000
2210 #define SDR0_PFC0_GPIO_21 0x00000400
2211 #define SDR0_PFC0_PCI0REQ1_N 0x00000000
2212 #define SDR0_PFC0_GPIO_22 0x00000200
2213 #define SDR0_PFC0_PCI1GNT0_N 0x00000000
2214 #define SDR0_PFC0_GPIO_23 0x00000100
2215 #define SDR0_PFC0_PCI1GNT1_N 0x00000000
2216 #define SDR0_PFC0_GPIO_24 0x00000080
2217 #define SDR0_PFC0_PCI1REQ0_N 0x00000000
2218 #define SDR0_PFC0_GPIO_25 0x00000040
2219 #define SDR0_PFC0_PCI1REQ1_N 0x00000000
2220 #define SDR0_PFC0_GPIO_26 0x00000020
2221 #define SDR0_PFC0_PCI2GNT0_N 0x00000000
2222 #define SDR0_PFC0_GPIO_27 0x00000010
2223 #define SDR0_PFC0_PCI2GNT1_N 0x00000000
2224 #define SDR0_PFC0_GPIO_28 0x00000008
2225 #define SDR0_PFC0_PCI2REQ0_N 0x00000000
2226 #define SDR0_PFC0_GPIO_29 0x00000004
2227 #define SDR0_PFC0_PCI2REQ1_N 0x00000000
2228 #define SDR0_PFC0_GPIO_30 0x00000002
2229 #define SDR0_PFC0_UART1RX 0x00000000
2230 #define SDR0_PFC0_GPIO_31 0x00000001
2231 #define SDR0_PFC0_UART1TX 0x00000000
2233 #define SDR0_PFC1 0x4101
2234 #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
2235 #define SDR0_PFC1_UART1_DSR_DTR 0x00000000
2236 #define SDR0_PFC1_UART1_CTS_RTS 0x02000000
2237 #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
2238 #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
2239 #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
2240 #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
2241 #define SDR0_PFC1_ETH_10_100 0x00000000
2242 #define SDR0_PFC1_ETH_GIGA 0x00200000
2243 #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
2244 #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
2245 #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
2246 #define SDR0_PFC1_CPU_NO_TRACE 0x00000000
2247 #define SDR0_PFC1_CPU_TRACE 0x00080000
2248 #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
2249 #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
2251 #define SDR0_MFR 0x4300
2252 #endif /* CONFIG_440SPE */
2255 #define SDR0_SDCS_SDD (0x80000000 >> 31)
2257 #if defined(CONFIG_440GP)
2258 #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
2259 #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
2260 #endif /* defined(CONFIG_440GP) */
2261 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
2262 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
2263 #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
2264 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
2265 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
2266 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
2267 #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
2268 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
2270 #define SDR0_UARTX_UXICS_MASK 0xF0000000
2271 #define SDR0_UARTX_UXICS_PLB 0x20000000
2272 #define SDR0_UARTX_UXEC_MASK 0x00800000
2273 #define SDR0_UARTX_UXEC_INT 0x00000000
2274 #define SDR0_UARTX_UXEC_EXT 0x00800000
2275 #define SDR0_UARTX_UXDTE_MASK 0x00400000
2276 #define SDR0_UARTX_UXDTE_DISABLE 0x00000000
2277 #define SDR0_UARTX_UXDTE_ENABLE 0x00400000
2278 #define SDR0_UARTX_UXDRE_MASK 0x00200000
2279 #define SDR0_UARTX_UXDRE_DISABLE 0x00000000
2280 #define SDR0_UARTX_UXDRE_ENABLE 0x00200000
2281 #define SDR0_UARTX_UXDC_MASK 0x00100000
2282 #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
2283 #define SDR0_UARTX_UXDC_CLEARED 0x00100000
2284 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
2285 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
2286 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
2288 #define SDR0_CPU440_EARV_MASK 0x30000000
2289 #define SDR0_CPU440_EARV_EBC 0x10000000
2290 #define SDR0_CPU440_EARV_PCI 0x20000000
2291 #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2292 #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2293 #define SDR0_CPU440_NTO1_MASK 0x00000002
2294 #define SDR0_CPU440_NTO1_NTOP 0x00000000
2295 #define SDR0_CPU440_NTO1_NTO1 0x00000002
2296 #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2297 #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2299 #define SDR0_XCR_PAE_MASK 0x80000000
2300 #define SDR0_XCR_PAE_DISABLE 0x00000000
2301 #define SDR0_XCR_PAE_ENABLE 0x80000000
2302 #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2303 #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2304 #define SDR0_XCR_PHCE_MASK 0x40000000
2305 #define SDR0_XCR_PHCE_DISABLE 0x00000000
2306 #define SDR0_XCR_PHCE_ENABLE 0x40000000
2307 #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2308 #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2309 #define SDR0_XCR_PISE_MASK 0x20000000
2310 #define SDR0_XCR_PISE_DISABLE 0x00000000
2311 #define SDR0_XCR_PISE_ENABLE 0x20000000
2312 #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2313 #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2314 #define SDR0_XCR_PCWE_MASK 0x10000000
2315 #define SDR0_XCR_PCWE_DISABLE 0x00000000
2316 #define SDR0_XCR_PCWE_ENABLE 0x10000000
2317 #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2318 #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2319 #define SDR0_XCR_PPIM_MASK 0x0F000000
2320 #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2321 #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2322 #define SDR0_XCR_PR64E_MASK 0x00800000
2323 #define SDR0_XCR_PR64E_DISABLE 0x00000000
2324 #define SDR0_XCR_PR64E_ENABLE 0x00800000
2325 #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2326 #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2327 #define SDR0_XCR_PXFS_MASK 0x00600000
2328 #define SDR0_XCR_PXFS_HIGH 0x00000000
2329 #define SDR0_XCR_PXFS_MED 0x00200000
2330 #define SDR0_XCR_PXFS_LOW 0x00400000
2331 #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2332 #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2333 #define SDR0_XCR_PDM_MASK 0x00000040
2334 #define SDR0_XCR_PDM_MULTIPOINT 0x00000000
2335 #define SDR0_XCR_PDM_P2P 0x00000040
2336 #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
2337 #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
2339 #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
2340 #define SDR0_PFC0_GEIE_MASK 0x00003E00
2341 #define SDR0_PFC0_GEIE_TRE 0x00003E00
2342 #define SDR0_PFC0_GEIE_NOTRE 0x00000000
2343 #define SDR0_PFC0_TRE_MASK 0x00000100
2344 #define SDR0_PFC0_TRE_DISABLE 0x00000000
2345 #define SDR0_PFC0_TRE_ENABLE 0x00000100
2346 #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
2347 #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
2349 #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
2350 #define SDR0_PFC1_EPS_MASK 0x01C00000
2351 #define SDR0_PFC1_EPS_GROUP0 0x00000000
2352 #define SDR0_PFC1_EPS_GROUP1 0x00400000
2353 #define SDR0_PFC1_EPS_GROUP2 0x00800000
2354 #define SDR0_PFC1_EPS_GROUP3 0x00C00000
2355 #define SDR0_PFC1_EPS_GROUP4 0x01000000
2356 #define SDR0_PFC1_EPS_GROUP5 0x01400000
2357 #define SDR0_PFC1_EPS_GROUP6 0x01800000
2358 #define SDR0_PFC1_EPS_GROUP7 0x01C00000
2359 #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
2360 #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
2361 #define SDR0_PFC1_RMII_MASK 0x00200000
2362 #define SDR0_PFC1_RMII_100MBIT 0x00000000
2363 #define SDR0_PFC1_RMII_10MBIT 0x00200000
2364 #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
2365 #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
2366 #define SDR0_PFC1_CTEMS_MASK 0x00100000
2367 #define SDR0_PFC1_CTEMS_EMS 0x00000000
2368 #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
2370 #define SDR0_MFR_TAH0_MASK 0x80000000
2371 #define SDR0_MFR_TAH0_ENABLE 0x00000000
2372 #define SDR0_MFR_TAH0_DISABLE 0x80000000
2373 #define SDR0_MFR_TAH1_MASK 0x40000000
2374 #define SDR0_MFR_TAH1_ENABLE 0x00000000
2375 #define SDR0_MFR_TAH1_DISABLE 0x40000000
2376 #define SDR0_MFR_PCM_MASK 0x20000000
2377 #define SDR0_MFR_PCM_PPC440GX 0x00000000
2378 #define SDR0_MFR_PCM_PPC440GP 0x20000000
2379 #define SDR0_MFR_ECS_MASK 0x10000000
2380 #define SDR0_MFR_ECS_INTERNAL 0x10000000
2382 #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
2383 #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
2384 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
2385 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
2386 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
2387 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
2388 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
2389 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
2390 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
2391 #define SDR0_MFR_ERRATA3_EN0 0x00800000
2392 #define SDR0_MFR_ERRATA3_EN1 0x00400000
2393 #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
2394 #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
2395 #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
2396 #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
2397 #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
2399 #define SDR0_SRST_BGO 0x80000000
2400 #define SDR0_SRST_PLB 0x40000000
2401 #define SDR0_SRST_EBC 0x20000000
2402 #define SDR0_SRST_OPB 0x10000000
2403 #define SDR0_SRST_UART0 0x08000000
2404 #define SDR0_SRST_UART1 0x04000000
2405 #define SDR0_SRST_IIC0 0x02000000
2406 #define SDR0_SRST_IIC1 0x01000000
2407 #define SDR0_SRST_GPIO 0x00800000
2408 #define SDR0_SRST_GPT 0x00400000
2409 #define SDR0_SRST_DMC 0x00200000
2410 #define SDR0_SRST_PCI 0x00100000
2411 #define SDR0_SRST_EMAC0 0x00080000
2412 #define SDR0_SRST_EMAC1 0x00040000
2413 #define SDR0_SRST_CPM 0x00020000
2414 #define SDR0_SRST_IMU 0x00010000
2415 #define SDR0_SRST_UIC01 0x00008000
2416 #define SDR0_SRST_UICB2 0x00004000
2417 #define SDR0_SRST_SRAM 0x00002000
2418 #define SDR0_SRST_EBM 0x00001000
2419 #define SDR0_SRST_BGI 0x00000800
2420 #define SDR0_SRST_DMA 0x00000400
2421 #define SDR0_SRST_DMAC 0x00000200
2422 #define SDR0_SRST_MAL 0x00000100
2423 #define SDR0_SRST_ZMII 0x00000080
2424 #define SDR0_SRST_GPTR 0x00000040
2425 #define SDR0_SRST_PPM 0x00000020
2426 #define SDR0_SRST_EMAC2 0x00000010
2427 #define SDR0_SRST_EMAC3 0x00000008
2428 #define SDR0_SRST_RGMII 0x00000001
2430 /*-----------------------------------------------------------------------------+
2432 +-----------------------------------------------------------------------------*/
2433 #if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
2434 #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
2435 #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
2436 #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
2437 #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
2438 #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
2439 #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
2440 #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
2441 #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
2442 #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
2443 #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
2444 #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
2445 #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
2447 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
2448 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
2449 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
2450 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
2451 #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
2452 #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
2453 #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
2454 #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
2455 #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
2456 #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
2457 #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
2458 #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
2459 #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
2460 #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
2462 #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
2463 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
2464 #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
2465 #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
2466 #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
2467 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
2469 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
2470 #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
2471 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
2472 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
2473 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
2475 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
2476 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
2477 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
2478 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
2480 /* Strap 1 Register */
2481 #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
2482 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
2483 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
2484 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
2485 #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
2486 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
2487 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
2488 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
2489 #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
2490 #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
2491 #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
2492 #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
2493 #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
2494 #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
2495 #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
2496 #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
2497 #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
2498 #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
2499 #endif /* CONFIG_440GX */
2501 /*-----------------------------------------------------------------------------
2502 | IIC Register Offsets
2503 '----------------------------------------------------------------------------*/
2504 #define IICMDBUF 0x00
2505 #define IICSDBUF 0x02
2506 #define IICLMADR 0x04
2507 #define IICHMADR 0x05
2508 #define IICCNTL 0x06
2509 #define IICMDCNTL 0x07
2511 #define IICEXTSTS 0x09
2512 #define IICLSADR 0x0A
2513 #define IICHSADR 0x0B
2514 #define IICCLKDIV 0x0C
2515 #define IICINTRMSK 0x0D
2516 #define IICXFRCNT 0x0E
2517 #define IICXTCNTLSS 0x0F
2518 #define IICDIRECTCNTL 0x10
2520 /*-----------------------------------------------------------------------------
2521 | UART Register Offsets
2522 '----------------------------------------------------------------------------*/
2523 #define DATA_REG 0x00
2526 #define INT_ENABLE 0x01
2527 #define FIFO_CONTROL 0x02
2528 #define LINE_CONTROL 0x03
2529 #define MODEM_CONTROL 0x04
2530 #define LINE_STATUS 0x05
2531 #define MODEM_STATUS 0x06
2532 #define SCRATCH 0x07
2534 /*-----------------------------------------------------------------------------
2535 | PCI Internal Registers et. al. (accessed via plb)
2536 +----------------------------------------------------------------------------*/
2537 #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000)
2538 #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004)
2539 #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
2540 #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
2542 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
2544 /* PCI Local Configuration Registers
2545 --------------------------------- */
2546 #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
2548 /* PCI Master Local Configuration Registers */
2549 #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
2550 #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
2551 #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
2552 #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
2553 #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
2554 #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
2555 #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
2556 #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
2557 #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
2558 #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
2559 #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
2560 #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
2562 /* PCI Target Local Configuration Registers */
2563 #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
2564 #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
2565 #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
2566 #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
2570 #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
2571 #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
2572 #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
2573 #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
2574 #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
2575 #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
2576 #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
2577 #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
2578 #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
2579 #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
2580 #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
2581 #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
2582 #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
2583 #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
2584 #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
2585 #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
2586 #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
2587 #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
2588 #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
2589 #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
2590 #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
2591 #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
2592 #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
2593 #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
2594 #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
2595 #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
2596 #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
2597 #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
2599 #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
2600 #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
2602 #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
2603 #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
2604 #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
2605 #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
2606 #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
2607 #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
2608 #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
2609 #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
2610 #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
2611 #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
2612 #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
2614 #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
2615 #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
2616 #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
2617 #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
2618 #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
2619 #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
2620 #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
2621 #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
2622 #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
2624 #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
2626 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
2628 /******************************************************************************
2629 * GPIO macro register defines
2630 ******************************************************************************/
2634 #if defined(CONFIG_440GP)
2635 #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
2637 #define GPIO0_OR (GPIO0_BASE+0x0)
2638 #define GPIO0_TCR (GPIO0_BASE+0x4)
2639 #define GPIO0_ODR (GPIO0_BASE+0x18)
2640 #define GPIO0_IR (GPIO0_BASE+0x1C)
2641 #endif /* CONFIG_440GP */
2643 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
2644 #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
2645 #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
2648 #define GPIOx_OR 0x00 /* GPIO Output Register */
2649 #define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
2650 #define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
2651 #define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
2652 #define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
2653 #define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
2654 #define GPIOx_ODR 0x18 /* GPIO Open drain Register */
2655 #define GPIOx_IR 0x1C /* GPIO Input Register */
2656 #define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
2657 #define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
2658 #define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
2659 #define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
2660 #define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
2661 #define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
2662 #define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
2663 #define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
2664 #define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
2666 #define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */
2667 #define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
2668 #define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
2669 #define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
2670 #define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
2672 #define GPIO0_OR (GPIO0_BASE+0x0)
2673 #define GPIO0_TCR (GPIO0_BASE+0x4)
2674 #define GPIO0_OSRL (GPIO0_BASE+0x8)
2675 #define GPIO0_OSRH (GPIO0_BASE+0xC)
2676 #define GPIO0_TSRL (GPIO0_BASE+0x10)
2677 #define GPIO0_TSRH (GPIO0_BASE+0x14)
2678 #define GPIO0_ODR (GPIO0_BASE+0x18)
2679 #define GPIO0_IR (GPIO0_BASE+0x1C)
2680 #define GPIO0_RR1 (GPIO0_BASE+0x20)
2681 #define GPIO0_RR2 (GPIO0_BASE+0x24)
2682 #define GPIO0_RR3 (GPIO0_BASE+0x28)
2683 #define GPIO0_ISR1L (GPIO0_BASE+0x30)
2684 #define GPIO0_ISR1H (GPIO0_BASE+0x34)
2685 #define GPIO0_ISR2L (GPIO0_BASE+0x38)
2686 #define GPIO0_ISR2H (GPIO0_BASE+0x3C)
2687 #define GPIO0_ISR3L (GPIO0_BASE+0x40)
2688 #define GPIO0_ISR3H (GPIO0_BASE+0x44)
2690 #define GPIO1_OR (GPIO1_BASE+0x0)
2691 #define GPIO1_TCR (GPIO1_BASE+0x4)
2692 #define GPIO1_OSRL (GPIO1_BASE+0x8)
2693 #define GPIO1_OSRH (GPIO1_BASE+0xC)
2694 #define GPIO1_TSRL (GPIO1_BASE+0x10)
2695 #define GPIO1_TSRH (GPIO1_BASE+0x14)
2696 #define GPIO1_ODR (GPIO1_BASE+0x18)
2697 #define GPIO1_IR (GPIO1_BASE+0x1C)
2698 #define GPIO1_RR1 (GPIO1_BASE+0x20)
2699 #define GPIO1_RR2 (GPIO1_BASE+0x24)
2700 #define GPIO1_RR3 (GPIO1_BASE+0x28)
2701 #define GPIO1_ISR1L (GPIO1_BASE+0x30)
2702 #define GPIO1_ISR1H (GPIO1_BASE+0x34)
2703 #define GPIO1_ISR2L (GPIO1_BASE+0x38)
2704 #define GPIO1_ISR2H (GPIO1_BASE+0x3C)
2705 #define GPIO1_ISR3L (GPIO1_BASE+0x40)
2706 #define GPIO1_ISR3H (GPIO1_BASE+0x44)
2709 #define GPIO_GROUP_MAX 2
2711 #define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
2712 #define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
2713 #define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
2714 #define GPIO_MASK 0xC0000000 /* GPIO_MASK */
2715 #define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
2716 /* For the other GPIO number, you must shift */
2718 #ifndef __ASSEMBLY__
2720 typedef enum gpio_select
{ GPIO_SEL
, GPIO_ALT1
, GPIO_ALT2
, GPIO_ALT3
} gpio_select_t
;
2721 typedef enum gpio_driver
{ GPIO_DIS
, GPIO_IN
, GPIO_OUT
, GPIO_BI
} gpio_driver_t
;
2723 typedef struct { unsigned long add
; /* gpio core base address */
2724 gpio_driver_t in_out
; /* Driver Setting */
2725 gpio_select_t alt_nb
; /* Selected Alternate */
2729 #endif /* __ASSEMBLY__ */
2732 * Macros for accessing the indirect EBC registers
2734 #define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
2735 #define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
2738 * Macros for accessing the indirect SDRAM controller registers
2740 #define mtsdram(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
2741 #define mfsdram(reg, data) mtdcr(memcfga,reg);data = mfdcr(memcfgd)
2744 * Macros for accessing the indirect clocking controller registers
2746 #define mtclk(reg, data) mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
2747 #define mfclk(reg, data) mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
2750 * Macros for accessing the sdr controller registers
2752 #define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
2753 #define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
2756 #ifndef __ASSEMBLY__
2759 unsigned long pllFwdDivA
;
2760 unsigned long pllFwdDivB
;
2761 unsigned long pllFbkDiv
;
2762 unsigned long pllOpbDiv
;
2763 unsigned long pllPciDiv
;
2764 unsigned long pllExtBusDiv
;
2765 unsigned long freqVCOMhz
; /* in MHz */
2766 unsigned long freqProcessor
;
2767 unsigned long freqTmrClk
;
2768 unsigned long freqPLB
;
2769 unsigned long freqOPB
;
2770 unsigned long freqEPB
;
2771 unsigned long freqPCI
;
2772 #ifdef CONFIG_440SPE
2773 unsigned long freqDDR
;
2775 unsigned long pciIntArbEn
; /* Internal PCI arbiter is enabled */
2776 unsigned long pciClkSync
; /* PCI clock is synchronous */
2779 #endif /* _ASMLANGUAGE */
2781 #define RESET_VECTOR 0xfffffffc
2782 #define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */
2783 /* cache line aligned data. */
2785 #endif /* __PPC440_H__ */
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