include/ppc4xx.h

   1 /*----------------------------------------------------------------------------+
   2 |
   3 |       This source code has been made available to you by IBM on an AS-IS
   4 |       basis.  Anyone receiving this source is licensed under IBM
   5 |       copyrights to use it in any way he or she deems fit, including
   6 |       copying it, modifying it, compiling it, and redistributing it either
   7 |       with or without modifications.  No license under IBM patents or
   8 |       patent applications is to be implied by the copyright license.
   9 |
  10 |       Any user of this software should understand that IBM cannot provide
  11 |       technical support for this software and will not be responsible for
  12 |       any consequences resulting from the use of this software.
  13 |
  14 |       Any person who transfers this source code or any derivative work
  15 |       must include the IBM copyright notice, this paragraph, and the
  16 |       preceding two paragraphs in the transferred software.
  17 |
  18 |       COPYRIGHT   I B M   CORPORATION 1999
  19 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20 +----------------------------------------------------------------------------*/
  21
  22 #ifndef __PPC4XX_H__
  23 #define __PPC4XX_H__
  24
  25 /*
  26  * Configure which SDRAM/DDR/DDR2 controller is equipped
  27  */
  28 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
  29         defined(CONFIG_AP1000) || defined(CONFIG_ML2)
  30 #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
  31 #endif
  32
  33 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
  34     defined(CONFIG_440EP) || defined(CONFIG_440GR)
  35 #define CONFIG_SDRAM_PPC4xx_IBM_DDR     /* IBM DDR controller */
  36 #endif
  37
  38 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  39 #define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
  40 #endif
  41
  42 #if defined(CONFIG_405EX) || \
  43     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  44     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  45 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2    /* IBM DDR(2) controller */
  46 #endif
  47
  48 #if defined(CONFIG_440)
  49 #include <ppc440.h>
  50 #else
  51 #include <ppc405.h>
  52 #endif
  53
  54 #include <asm/ppc4xx-sdram.h>
  55
  56 /*
  57  * Macro for generating register field mnemonics
  58  */
  59 #define PPC_REG_BITS            32
  60 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
  61
  62 /*
  63  * Elide casts when assembling register mnemonics
  64  */
  65 #ifndef __ASSEMBLY__
  66 #define static_cast(type, val)  (type)(val)
  67 #else
  68 #define static_cast(type, val)  (val)
  69 #endif
  70
  71 /*
  72  * Common stuff for 4xx (405 and 440)
  73  */
  74
  75 #define EXC_OFF_SYS_RESET       0x0100  /* System reset                         */
  76 #define _START_OFFSET           (EXC_OFF_SYS_RESET + 0x2000)
  77
  78 #define RESET_VECTOR    0xfffffffc
  79 #define CACHELINE_MASK  (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
  80                                                      line aligned data. */
  81
  82 #define CPR0_DCR_BASE   0x0C
  83 #define cprcfga         (CPR0_DCR_BASE+0x0)
  84 #define cprcfgd         (CPR0_DCR_BASE+0x1)
  85
  86 #define SDR_DCR_BASE    0x0E
  87 #define sdrcfga         (SDR_DCR_BASE+0x0)
  88 #define sdrcfgd         (SDR_DCR_BASE+0x1)
  89
  90 #define SDRAM_DCR_BASE  0x10
  91 #define memcfga         (SDRAM_DCR_BASE+0x0)
  92 #define memcfgd         (SDRAM_DCR_BASE+0x1)
  93
  94 #define EBC_DCR_BASE    0x12
  95 #define ebccfga         (EBC_DCR_BASE+0x0)
  96 #define ebccfgd         (EBC_DCR_BASE+0x1)
  97
  98 /*
  99  * Macros for indirect DCR access
 100  */
 101 #define mtcpr(reg, d)   do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
 102 #define mfcpr(reg, d)   do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
 103
 104 #define mtebc(reg, d)   do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
 105 #define mfebc(reg, d)   do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
 106
 107 #define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
 108 #define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
 109
 110 #define mtsdr(reg, d)   do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
 111 #define mfsdr(reg, d)   do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
 112
 113 #ifndef __ASSEMBLY__
 114
 115 typedef struct
 116 {
 117         unsigned long freqDDR;
 118         unsigned long freqEBC;
 119         unsigned long freqOPB;
 120         unsigned long freqPCI;
 121         unsigned long freqPLB;
 122         unsigned long freqTmrClk;
 123         unsigned long freqUART;
 124         unsigned long freqProcessor;
 125         unsigned long freqVCOHz;
 126         unsigned long freqVCOMhz;       /* in MHz                          */
 127         unsigned long pciClkSync;       /* PCI clock is synchronous        */
 128         unsigned long pciIntArbEn;      /* Internal PCI arbiter is enabled */
 129         unsigned long pllExtBusDiv;
 130         unsigned long pllFbkDiv;
 131         unsigned long pllFwdDiv;
 132         unsigned long pllFwdDivA;
 133         unsigned long pllFwdDivB;
 134         unsigned long pllOpbDiv;
 135         unsigned long pllPciDiv;
 136         unsigned long pllPlbDiv;
 137 } PPC4xx_SYS_INFO;
 138
 139 #endif  /* __ASSEMBLY__ */
 140
 141 #endif  /* __PPC4XX_H__ */