4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
7 * (C) Copyright 2003, Motorola, Inc.
8 * maintained by Xianghua Xiao (x.xiao@motorola.com)
11 * SPDX-License-Identifier: GPL-2.0+
22 #define TSEC_SIZE 0x40000
23 #define TSEC_MDIO_OFFSET 0x40000
25 #define TSEC_SIZE 0x01000
26 #define TSEC_MDIO_OFFSET 0x01000
29 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
31 #define TSEC_GET_REGS(num, offset) \
32 (struct tsec __iomem *)\
33 (TSEC_BASE_ADDR + (((num) - 1) * (offset)))
35 #define TSEC_GET_REGS_BASE(num) \
36 TSEC_GET_REGS((num), TSEC_SIZE)
38 #define TSEC_GET_MDIO_REGS(num, offset) \
39 (struct tsec_mii_mng __iomem *)\
40 (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset))
42 #define TSEC_GET_MDIO_REGS_BASE(num) \
43 TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
45 #define DEFAULT_MII_NAME "FSL_MDIO"
47 #define STD_TSEC_INFO(num) \
49 .regs = TSEC_GET_REGS_BASE(num), \
50 .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
51 .devname = CONFIG_TSEC##num##_NAME, \
52 .phyaddr = TSEC##num##_PHY_ADDR, \
53 .flags = TSEC##num##_FLAGS, \
54 .mii_devname = DEFAULT_MII_NAME \
57 #define SET_STD_TSEC_INFO(x, num) \
59 x.regs = TSEC_GET_REGS_BASE(num); \
60 x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
61 x.devname = CONFIG_TSEC##num##_NAME; \
62 x.phyaddr = TSEC##num##_PHY_ADDR; \
63 x.flags = TSEC##num##_FLAGS;\
64 x.mii_devname = DEFAULT_MII_NAME;\
67 #define MAC_ADDR_LEN 6
69 /* #define TSEC_TIMEOUT 1000000 */
70 #define TSEC_TIMEOUT 1000
71 #define TOUT_LOOP 1000000
73 /* TBI register addresses */
77 #define TBI_ANLPBPA 0x05
79 #define TBI_TBICON 0x11
81 /* TBI MDIO register bit fields*/
82 #define TBICON_CLK_SELECT 0x0020
83 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
84 #define TBIANA_SYMMETRIC_PAUSE 0x0080
85 #define TBIANA_HALF_DUPLEX 0x0040
86 #define TBIANA_FULL_DUPLEX 0x0020
87 #define TBICR_PHY_RESET 0x8000
88 #define TBICR_ANEG_ENABLE 0x1000
89 #define TBICR_RESTART_ANEG 0x0200
90 #define TBICR_FULL_DUPLEX 0x0100
91 #define TBICR_SPEED1_SET 0x0040
93 /* MAC register bits */
94 #define MACCFG1_SOFT_RESET 0x80000000
95 #define MACCFG1_RESET_RX_MC 0x00080000
96 #define MACCFG1_RESET_TX_MC 0x00040000
97 #define MACCFG1_RESET_RX_FUN 0x00020000
98 #define MACCFG1_RESET_TX_FUN 0x00010000
99 #define MACCFG1_LOOPBACK 0x00000100
100 #define MACCFG1_RX_FLOW 0x00000020
101 #define MACCFG1_TX_FLOW 0x00000010
102 #define MACCFG1_SYNCD_RX_EN 0x00000008
103 #define MACCFG1_RX_EN 0x00000004
104 #define MACCFG1_SYNCD_TX_EN 0x00000002
105 #define MACCFG1_TX_EN 0x00000001
107 #define MACCFG2_INIT_SETTINGS 0x00007205
108 #define MACCFG2_FULL_DUPLEX 0x00000001
109 #define MACCFG2_IF 0x00000300
110 #define MACCFG2_GMII 0x00000200
111 #define MACCFG2_MII 0x00000100
113 #define ECNTRL_INIT_SETTINGS 0x00001000
114 #define ECNTRL_TBI_MODE 0x00000020
115 #define ECNTRL_REDUCED_MODE 0x00000010
116 #define ECNTRL_R100 0x00000008
117 #define ECNTRL_REDUCED_MII_MODE 0x00000004
118 #define ECNTRL_SGMII_MODE 0x00000002
120 #ifndef CONFIG_SYS_TBIPA_VALUE
121 # define CONFIG_SYS_TBIPA_VALUE 0x1f
124 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
126 #define MINFLR_INIT_SETTINGS 0x00000040
128 #define DMACTRL_INIT_SETTINGS 0x000000c3
129 #define DMACTRL_GRS 0x00000010
130 #define DMACTRL_GTS 0x00000008
131 #define DMACTRL_LE 0x00008000
133 #define TSTAT_CLEAR_THALT 0x80000000
134 #define RSTAT_CLEAR_RHALT 0x00800000
136 #define IEVENT_INIT_CLEAR 0xffffffff
137 #define IEVENT_BABR 0x80000000
138 #define IEVENT_RXC 0x40000000
139 #define IEVENT_BSY 0x20000000
140 #define IEVENT_EBERR 0x10000000
141 #define IEVENT_MSRO 0x04000000
142 #define IEVENT_GTSC 0x02000000
143 #define IEVENT_BABT 0x01000000
144 #define IEVENT_TXC 0x00800000
145 #define IEVENT_TXE 0x00400000
146 #define IEVENT_TXB 0x00200000
147 #define IEVENT_TXF 0x00100000
148 #define IEVENT_IE 0x00080000
149 #define IEVENT_LC 0x00040000
150 #define IEVENT_CRL 0x00020000
151 #define IEVENT_XFUN 0x00010000
152 #define IEVENT_RXB0 0x00008000
153 #define IEVENT_GRSC 0x00000100
154 #define IEVENT_RXF0 0x00000080
156 #define IMASK_INIT_CLEAR 0x00000000
157 #define IMASK_TXEEN 0x00400000
158 #define IMASK_TXBEN 0x00200000
159 #define IMASK_TXFEN 0x00100000
160 #define IMASK_RXFEN0 0x00000080
162 /* Default Attribute fields */
163 #define ATTR_INIT_SETTINGS 0x000000c0
164 #define ATTRELI_INIT_SETTINGS 0x00000000
166 /* TxBD status field bits */
167 #define TXBD_READY 0x8000
168 #define TXBD_PADCRC 0x4000
169 #define TXBD_WRAP 0x2000
170 #define TXBD_INTERRUPT 0x1000
171 #define TXBD_LAST 0x0800
172 #define TXBD_CRC 0x0400
173 #define TXBD_DEF 0x0200
174 #define TXBD_HUGEFRAME 0x0080
175 #define TXBD_LATECOLLISION 0x0080
176 #define TXBD_RETRYLIMIT 0x0040
177 #define TXBD_RETRYCOUNTMASK 0x003c
178 #define TXBD_UNDERRUN 0x0002
179 #define TXBD_STATS 0x03ff
181 /* RxBD status field bits */
182 #define RXBD_EMPTY 0x8000
183 #define RXBD_RO1 0x4000
184 #define RXBD_WRAP 0x2000
185 #define RXBD_INTERRUPT 0x1000
186 #define RXBD_LAST 0x0800
187 #define RXBD_FIRST 0x0400
188 #define RXBD_MISS 0x0100
189 #define RXBD_BROADCAST 0x0080
190 #define RXBD_MULTICAST 0x0040
191 #define RXBD_LARGE 0x0020
192 #define RXBD_NONOCTET 0x0010
193 #define RXBD_SHORT 0x0008
194 #define RXBD_CRCERR 0x0004
195 #define RXBD_OVERRUN 0x0002
196 #define RXBD_TRUNCATED 0x0001
197 #define RXBD_STATS 0x003f
200 uint16_t status
; /* Status Fields */
201 uint16_t length
; /* Buffer length */
202 uint32_t bufptr
; /* Buffer Pointer */
206 uint16_t status
; /* Status Fields */
207 uint16_t length
; /* Buffer Length */
208 uint32_t bufptr
; /* Buffer Pointer */
211 struct tsec_rmon_mib
{
212 /* Transmit and Receive Counters */
213 u32 tr64
; /* Tx/Rx 64-byte Frame Counter */
214 u32 tr127
; /* Tx/Rx 65-127 byte Frame Counter */
215 u32 tr255
; /* Tx/Rx 128-255 byte Frame Counter */
216 u32 tr511
; /* Tx/Rx 256-511 byte Frame Counter */
217 u32 tr1k
; /* Tx/Rx 512-1023 byte Frame Counter */
218 u32 trmax
; /* Tx/Rx 1024-1518 byte Frame Counter */
219 u32 trmgv
; /* Tx/Rx 1519-1522 byte Good VLAN Frame */
220 /* Receive Counters */
221 u32 rbyt
; /* Receive Byte Counter */
222 u32 rpkt
; /* Receive Packet Counter */
223 u32 rfcs
; /* Receive FCS Error Counter */
224 u32 rmca
; /* Receive Multicast Packet (Counter) */
225 u32 rbca
; /* Receive Broadcast Packet */
226 u32 rxcf
; /* Receive Control Frame Packet */
227 u32 rxpf
; /* Receive Pause Frame Packet */
228 u32 rxuo
; /* Receive Unknown OP Code */
229 u32 raln
; /* Receive Alignment Error */
230 u32 rflr
; /* Receive Frame Length Error */
231 u32 rcde
; /* Receive Code Error */
232 u32 rcse
; /* Receive Carrier Sense Error */
233 u32 rund
; /* Receive Undersize Packet */
234 u32 rovr
; /* Receive Oversize Packet */
235 u32 rfrg
; /* Receive Fragments */
236 u32 rjbr
; /* Receive Jabber */
237 u32 rdrp
; /* Receive Drop */
238 /* Transmit Counters */
239 u32 tbyt
; /* Transmit Byte Counter */
240 u32 tpkt
; /* Transmit Packet */
241 u32 tmca
; /* Transmit Multicast Packet */
242 u32 tbca
; /* Transmit Broadcast Packet */
243 u32 txpf
; /* Transmit Pause Control Frame */
244 u32 tdfr
; /* Transmit Deferral Packet */
245 u32 tedf
; /* Transmit Excessive Deferral Packet */
246 u32 tscl
; /* Transmit Single Collision Packet */
248 u32 tmcl
; /* Transmit Multiple Collision Packet */
249 u32 tlcl
; /* Transmit Late Collision Packet */
250 u32 txcl
; /* Transmit Excessive Collision Packet */
251 u32 tncl
; /* Transmit Total Collision */
255 u32 tdrp
; /* Transmit Drop Frame */
256 u32 tjbr
; /* Transmit Jabber Frame */
257 u32 tfcs
; /* Transmit FCS Error */
258 u32 txcf
; /* Transmit Control Frame */
259 u32 tovr
; /* Transmit Oversize Frame */
260 u32 tund
; /* Transmit Undersize Frame */
261 u32 tfrg
; /* Transmit Fragments Frame */
262 /* General Registers */
263 u32 car1
; /* Carry Register One */
264 u32 car2
; /* Carry Register Two */
265 u32 cam1
; /* Carry Register One Mask */
266 u32 cam2
; /* Carry Register Two Mask */
269 struct tsec_hash_regs
{
270 u32 iaddr0
; /* Individual Address Register 0 */
271 u32 iaddr1
; /* Individual Address Register 1 */
272 u32 iaddr2
; /* Individual Address Register 2 */
273 u32 iaddr3
; /* Individual Address Register 3 */
274 u32 iaddr4
; /* Individual Address Register 4 */
275 u32 iaddr5
; /* Individual Address Register 5 */
276 u32 iaddr6
; /* Individual Address Register 6 */
277 u32 iaddr7
; /* Individual Address Register 7 */
279 u32 gaddr0
; /* Group Address Register 0 */
280 u32 gaddr1
; /* Group Address Register 1 */
281 u32 gaddr2
; /* Group Address Register 2 */
282 u32 gaddr3
; /* Group Address Register 3 */
283 u32 gaddr4
; /* Group Address Register 4 */
284 u32 gaddr5
; /* Group Address Register 5 */
285 u32 gaddr6
; /* Group Address Register 6 */
286 u32 gaddr7
; /* Group Address Register 7 */
291 /* General Control and Status Registers (0x2_n000) */
294 u32 ievent
; /* Interrupt Event */
295 u32 imask
; /* Interrupt Mask */
296 u32 edis
; /* Error Disabled */
298 u32 ecntrl
; /* Ethernet Control */
299 u32 minflr
; /* Minimum Frame Length */
300 u32 ptv
; /* Pause Time Value */
301 u32 dmactrl
; /* DMA Control */
302 u32 tbipa
; /* TBI PHY Address */
307 /* Transmit Control and Status Registers (0x2_n100) */
308 u32 tctrl
; /* Transmit Control */
309 u32 tstat
; /* Transmit Status */
311 u32 tbdlen
; /* Tx BD Data Length */
313 u32 ctbptr
; /* Current TxBD Pointer */
315 u32 tbptr
; /* TxBD Pointer */
319 u32 tbase
; /* TxBD Base Address */
321 u32 ostbd
; /* Out of Sequence TxBD */
322 u32 ostbdp
; /* Out of Sequence Tx Data Buffer Pointer */
325 /* Receive Control and Status Registers (0x2_n300) */
326 u32 rctrl
; /* Receive Control */
327 u32 rstat
; /* Receive Status */
329 u32 rbdlen
; /* RxBD Data Length */
332 u32 crbptr
; /* Current Receive Buffer Pointer */
334 u32 mrblr
; /* Maximum Receive Buffer Length */
336 u32 rbptr
; /* RxBD Pointer */
340 u32 rbase
; /* RxBD Base Address */
343 /* MAC Registers (0x2_n500) */
344 u32 maccfg1
; /* MAC Configuration #1 */
345 u32 maccfg2
; /* MAC Configuration #2 */
346 u32 ipgifg
; /* Inter Packet Gap/Inter Frame Gap */
347 u32 hafdup
; /* Half-duplex */
348 u32 maxfrm
; /* Maximum Frame */
358 u32 ifstat
; /* Interface Status */
359 u32 macstnaddr1
; /* Station Address, part 1 */
360 u32 macstnaddr2
; /* Station Address, part 2 */
366 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
367 struct tsec_rmon_mib rmon
;
370 /* Hash Function Registers (0x2_n800) */
371 struct tsec_hash_regs hash
;
375 /* Pattern Registers (0x2_nb00) */
377 u32 attr
; /* Default Attribute Register */
378 u32 attreli
; /* Default Attribute Extract Length and Index */
380 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
384 #define TSEC_GIGABIT (1 << 0)
386 /* These flags currently only have meaning if we're using the eTSEC */
387 #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
388 #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
390 struct tsec_private
{
391 struct tsec __iomem
*regs
;
392 struct tsec_mii_mng __iomem
*phyregs_sgmii
;
393 struct phy_device
*phydev
;
394 phy_interface_t interface
;
397 char mii_devname
[16];
401 struct tsec_info_struct
{
402 struct tsec __iomem
*regs
;
403 struct tsec_mii_mng __iomem
*miiregs_sgmii
;
406 phy_interface_t interface
;
407 unsigned int phyaddr
;
411 int tsec_standard_init(bd_t
*bis
);
412 int tsec_eth_init(bd_t
*bis
, struct tsec_info_struct
*tsec_info
, int num
);
414 #endif /* __TSEC_H */