libgcc/config/nds32/isr-library/intr_isr_4b.S

   1 /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2019 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    Under Section 7 of GPL version 3, you are granted additional
  18    permissions described in the GCC Runtime Library Exception, version
  19    3.1, as published by the Free Software Foundation.
  20
  21    You should have received a copy of the GNU General Public License and
  22    a copy of the GCC Runtime Library Exception along with this program;
  23    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  24    <http://www.gnu.org/licenses/>.  */
  25
  26 #include "save_mac_regs.inc"
  27 #include "save_fpu_regs.inc"
  28 #include "save_fpu_regs_00.inc"
  29 #include "save_fpu_regs_01.inc"
  30 #include "save_fpu_regs_02.inc"
  31 #include "save_fpu_regs_03.inc"
  32 #include "save_all.inc"
  33 #include "save_partial.inc"
  34 #include "adj_intr_lvl.inc"
  35 #include "restore_mac_regs.inc"
  36 #include "restore_fpu_regs_00.inc"
  37 #include "restore_fpu_regs_01.inc"
  38 #include "restore_fpu_regs_02.inc"
  39 #include "restore_fpu_regs_03.inc"
  40 #include "restore_fpu_regs.inc"
  41 #include "restore_all.inc"
  42 #include "restore_partial.inc"
  43         .section .nds32_isr, "ax"       /* Put it in the section of 1st level handler. */
  44         .align  1
  45 /*
  46   First Level Handlers
  47   1. First Level Handlers are invokded in vector section via jump instruction
  48   with specific names for different configurations.
  49   2. Naming Format: _nds32_e_SR_NT for exception handlers.
  50                     _nds32_i_SR_NT for interrupt handlers.
  51   2.1 All upper case letters are replaced with specific lower case letters encodings.
  52   2.2 SR: Saved Registers
  53       sa: Save All regs (context)
  54       ps: Partial Save (all caller-saved regs)
  55   2.3 NT: Nested Type
  56       ns: nested
  57       nn: not nested
  58       nr: nested ready
  59 */
  60
  61 /*
  62   This is 4-byte vector size version.
  63   The "_4b" postfix was added for 4-byte version symbol.
  64 */
  65 #ifdef NDS32_SAVE_ALL_REGS
  66 #if defined(NDS32_NESTED)
  67         .globl  _nds32_i_sa_ns_4b
  68         .type   _nds32_i_sa_ns_4b, @function
  69 _nds32_i_sa_ns_4b:
  70 #elif defined(NDS32_NESTED_READY)
  71         .globl  _nds32_i_sa_nr_4b
  72         .type   _nds32_i_sa_nr_4b, @function
  73 _nds32_i_sa_nr_4b:
  74 #else /* Not nested handler. */
  75         .globl  _nds32_i_sa_nn_4b
  76         .type   _nds32_i_sa_nn_4b, @function
  77 _nds32_i_sa_nn_4b:
  78 #endif /* endif for Nest Type */
  79 #else /* not NDS32_SAVE_ALL_REGS */
  80 #if defined(NDS32_NESTED)
  81         .globl  _nds32_i_ps_ns_4b
  82         .type   _nds32_i_ps_ns_4b, @function
  83 _nds32_i_ps_ns_4b:
  84 #elif defined(NDS32_NESTED_READY)
  85         .globl  _nds32_i_ps_nr_4b
  86         .type   _nds32_i_ps_nr_4b, @function
  87 _nds32_i_ps_nr_4b:
  88 #else /* Not nested handler. */
  89         .globl  _nds32_i_ps_nn_4b
  90         .type   _nds32_i_ps_nn_4b, @function
  91 _nds32_i_ps_nn_4b:
  92 #endif /* endif for Nest Type */
  93 #endif /* not NDS32_SAVE_ALL_REGS */
  94
  95 /*
  96   This is 4-byte vector size version.
  97   The vector id was restored into $lp in vector by compiler.
  98 */
  99 #ifdef NDS32_SAVE_ALL_REGS
 100         SAVE_ALL_4B
 101 #else
 102         SAVE_PARTIAL_4B
 103 #endif
 104         /* Prepare to call 2nd level handler. */
 105         la      $r2, _nds32_jmptbl_00
 106         lw      $r2, [$r2 + $r0 << #2]
 107         addi    $r0, $r0, #-9   /* Make interrput vector id zero-based.  */
 108         ADJ_INTR_LVL    /* Adjust INTR level. $r3 is clobbered.  */
 109         jral    $r2
 110         /* Restore used registers. */
 111 #ifdef NDS32_SAVE_ALL_REGS
 112         RESTORE_ALL
 113 #else
 114         RESTORE_PARTIAL
 115 #endif
 116         iret
 117
 118 #ifdef NDS32_SAVE_ALL_REGS
 119 #if defined(NDS32_NESTED)
 120         .size   _nds32_i_sa_ns_4b, .-_nds32_i_sa_ns_4b
 121 #elif defined(NDS32_NESTED_READY)
 122         .size   _nds32_i_sa_nr_4b, .-_nds32_i_sa_nr_4b
 123 #else /* Not nested handler. */
 124         .size   _nds32_i_sa_nn_4b, .-_nds32_i_sa_nn_4b
 125 #endif /* endif for Nest Type */
 126 #else /* not NDS32_SAVE_ALL_REGS */
 127 #if defined(NDS32_NESTED)
 128         .size   _nds32_i_ps_ns_4b, .-_nds32_i_ps_ns_4b
 129 #elif defined(NDS32_NESTED_READY)
 130         .size   _nds32_i_ps_nr_4b, .-_nds32_i_ps_nr_4b
 131 #else /* Not nested handler. */
 132         .size   _nds32_i_ps_nn_4b, .-_nds32_i_ps_nn_4b
 133 #endif /* endif for Nest Type */
 134 #endif /* not NDS32_SAVE_ALL_REGS */