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git.ipfire.org Git - thirdparty/gcc.git/blob - libitm/config/riscv/target.h
1 /* Copyright (C) 2022-2024 Free Software Foundation, Inc.
2 Contributed by Xiongchuan Tan <xc-tan@outlook.com>.
4 This file is part of the GNU Transactional Memory Library (libitm).
6 Libitm is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
13 FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 Under Section 7 of GPL version 3, you are granted additional
17 permissions described in the GCC Runtime Library Exception, version
18 3.1, as published by the Free Software Foundation.
20 You should have received a copy of the GNU General Public License and
21 a copy of the GCC Runtime Library Exception along with this program;
22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23 <http://www.gnu.org/licenses/>. */
25 namespace GTM HIDDEN
{
27 typedef struct gtm_jmpbuf
31 long int s
[12]; /* Saved registers, s0 is fp */
33 #if __riscv_xlen == 32
34 /* Ensure that the stack is 16-byte aligned */
38 /* FP saved registers */
39 #if defined(__riscv_flen) && __riscv_flen == 64
41 #elif defined(__riscv_flen) && __riscv_flen == 32
43 #elif defined(__riscv_flen)
44 # error Q-extension unsupported
48 /* The size of one line in hardware caches (in bytes). */
49 /* 64 bytes is a suggested value in the RVA profiles (see
50 https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc). */
51 #define HW_CACHELINE_SIZE 64
56 #ifdef __riscv_zihintpause
57 __asm
volatile ("pause");
59 /* Encoding of the pause instruction */
60 __asm
volatile (".4byte 0x100000F");