opcodes/ChangeLog

   1 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
   2
   3         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
   4         handling code over to...
   5         <OP_REG_CONTROL>: ... this new case.
   6         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
   7         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
   8         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
   9         replacing the `G' operand code with `g'.  Update "cftc1" and
  10         "cftc2" entries replacing the `E' operand code with `y'.
  11         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
  12         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
  13         entries replacing the `G' operand code with `g'.
  14
  15 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  16
  17         * mips-dis.c (mips_cp0_names_r3900): New variable.
  18         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
  19         for "r3900".
  20
  21 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  22
  23         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
  24         and "mtthc2" to using the `G' rather than `g' operand code for
  25         the coprocessor control register referred.
  26
  27 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  28
  29         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
  30         entries with each other.
  31
  32 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
  33
  34         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
  35
  36 2021-05-25  Alan Modra  <amodra@gmail.com>
  37
  38         * cris-desc.c: Regenerate.
  39         * cris-desc.h: Regenerate.
  40         * cris-opc.h: Regenerate.
  41         * po/POTFILES.in: Regenerate.
  42
  43 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
  44
  45         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
  46         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
  47         (CGEN_CPUS): Add cris.
  48         (CRIS_DEPS): Define.
  49         (stamp-cris): New rule.
  50         * cgen.sh: Handle desc action.
  51         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
  52         * Makefile.in, configure: Regenerate.
  53
  54 2021-05-18  Job Noorman  <mtvec@pm.me>
  55
  56         PR 27814
  57         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
  58         the elf objects.
  59
  60 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
  61
  62         * arm-dis.c (mve_opcodes): Fix disassembly of
  63         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
  64         (is_mve_encoding_conflict): MVE vector loads should not match
  65         when P = W = 0.
  66         (is_mve_unpredictable): It's not unpredictable to use the same
  67         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
  68
  69 2021-05-11  Nick Clifton  <nickc@redhat.com>
  70
  71         PR 27840
  72         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
  73         the end of the code buffer.
  74
  75 2021-05-06  Stafford Horne  <shorne@gmail.com>
  76
  77         PR 21464
  78         * or1k-asm.c: Regenerate.
  79
  80 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
  81
  82         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
  83         info->insn_info_valid.
  84
  85 2021-04-26  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl (lea): Add Optimize.
  88         * opcodes/i386-tbl.h: Re-generate.
  89
  90 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  91
  92         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
  93         of l32r fetch and display referenced literal value.
  94
  95 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  96
  97         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  98         to 4 for literal disassembly.
  99
 100 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 101
 102         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 103         for TLBI instruction.
 104
 105 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 106
 107         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 108         DC instruction.
 109
 110 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 111
 112         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 113         "qualifier".
 114         (convert_mov_to_movewide): Add initializer for "value".
 115
 116 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 117
 118         * aarch64-opc.c: Add RME system registers.
 119
 120 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 121
 122         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 123         "addi d,CV,z" to "c.mv d,CV".
 124
 125 2021-04-12  Alan Modra  <amodra@gmail.com>
 126
 127         * configure.ac (--enable-checking): Add support.
 128         * config.in: Regenerate.
 129         * configure: Regenerate.
 130
 131 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 132
 133         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 134         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 135
 136 2021-04-09  Alan Modra  <amodra@gmail.com>
 137
 138         * ppc-dis.c (struct dis_private): Add "special".
 139         (POWERPC_DIALECT): Delete.  Replace uses with..
 140         (private_data): ..this.  New inline function.
 141         (disassemble_init_powerpc): Init "special" names.
 142         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 143         field of prefix instructions.
 144         (bsearch_reloc, print_got_plt): New functions.
 145         (print_insn_powerpc): For pcrel instructions, print target address
 146         and symbol if known, and decode plt and got loads too.
 147
 148 2021-04-08  Alan Modra  <amodra@gmail.com>
 149
 150         PR 27684
 151         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 152
 153 2021-04-08  Alan Modra  <amodra@gmail.com>
 154
 155         PR 27676
 156         * ppc-opc.c (DCBT_EO): Move earlier.
 157         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 158         (powerpc_operands): Add THCT and THDS entries.
 159         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 160
 161 2021-04-06  Alan Modra  <amodra@gmail.com>
 162
 163         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 164         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 165         symbol_at_address_func.
 166
 167 2021-04-05  Alan Modra  <amodra@gmail.com>
 168
 169         * configure.ac: Don't check for limits.h, string.h, strings.h or
 170         stdlib.h.
 171         (AC_ISC_POSIX): Don't invoke.
 172         * sysdep.h: Include stdlib.h and string.h unconditionally.
 173         * i386-opc.h: Include limits.h unconditionally.
 174         * wasm32-dis.c: Likewise.
 175         * cgen-opc.c: Don't include alloca-conf.h.
 176         * config.in: Regenerate.
 177         * configure: Regenerate.
 178
 179 2021-04-01  Martin Liska  <mliska@suse.cz>
 180
 181         * arm-dis.c (strneq): Remove strneq and use startswith.
 182         * cr16-dis.c (print_insn_cr16): Likewise.
 183         * score-dis.c (streq): Likewise.
 184         (strneq): Likewise.
 185         * score7-dis.c (strneq): Likewise.
 186
 187 2021-04-01  Alan Modra  <amodra@gmail.com>
 188
 189         PR 27675
 190         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 191
 192 2021-03-31  Alan Modra  <amodra@gmail.com>
 193
 194         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 195         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 196         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 197         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 198         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 199         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 200         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 201         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 202         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 203         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 204         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 205         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 206         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 207         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 208         and TRUE with true throughout.
 209
 210 2021-03-31  Alan Modra  <amodra@gmail.com>
 211
 212         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 213         * aarch64-dis.h: Likewise.
 214         * aarch64-opc.c: Likewise.
 215         * avr-dis.c: Likewise.
 216         * csky-dis.c: Likewise.
 217         * nds32-asm.c: Likewise.
 218         * nds32-dis.c: Likewise.
 219         * nfp-dis.c: Likewise.
 220         * riscv-dis.c: Likewise.
 221         * s12z-dis.c: Likewise.
 222         * wasm32-dis.c: Likewise.
 223
 224 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 225
 226         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 227         (i386_seg_prefixes): New.
 228         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 229         (i386_seg_prefixes): Declare.
 230
 231 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 234
 235 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 236
 237         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 238         * i386-reg.tbl (st): Move down.
 239         (st(0)): Delete. Extend comment.
 240         * i386-tbl.h: Re-generate.
 241
 242 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 245         (cmpsd): Move next to cmps.
 246         (movsd): Move next to movs.
 247         (cmpxchg16b): Move to separate section.
 248         (fisttp, fisttpll): Likewise.
 249         (monitor, mwait): Likewise.
 250         * i386-tbl.h: Re-generate.
 251
 252 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 255         (vpsadbw): Add C.
 256         * i386-tbl.h: Re-generate.
 257
 258 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 261         pclmul, gfni): New templates. Use them wherever possible. Move
 262         SSE4.1 pextrw into respective section.
 263         * i386-tbl.h: Re-generate.
 264
 265 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 268         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 269         "length".
 270         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 271         Convert all of their uses to representation in opcode.
 272
 273 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 276         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 277         value of None. Shrink operands to 3 bits.
 278
 279 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 280
 281         * i386-gen.c (process_i386_opcode_modifier): New parameter
 282         "space".
 283         (output_i386_opcode): New local variable "space". Adjust
 284         process_i386_opcode_modifier() invocation.
 285         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 286         invocation.
 287         * i386-tbl.h: Re-generate.
 288
 289 2021-03-29  Alan Modra  <amodra@gmail.com>
 290
 291         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 292         (fp_qualifier_p, get_data_pattern): Likewise.
 293         (aarch64_get_operand_modifier_from_value): Likewise.
 294         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 295         (operand_variant_qualifier_p): Likewise.
 296         (qualifier_value_in_range_constraint_p): Likewise.
 297         (aarch64_get_qualifier_esize): Likewise.
 298         (aarch64_get_qualifier_nelem): Likewise.
 299         (aarch64_get_qualifier_standard_value): Likewise.
 300         (get_lower_bound, get_upper_bound): Likewise.
 301         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 302         (aarch64_print_operand): Likewise.
 303         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 304         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 305         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 306         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 307         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 308         (print_insn_tic6x): Likewise.
 309
 310 2021-03-29  Alan Modra  <amodra@gmail.com>
 311
 312         * arc-dis.c (extract_operand_value): Correct NULL cast.
 313         * frv-opc.h: Regenerate.
 314
 315 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 316
 317         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 318         MMX form.
 319         * i386-tbl.h: Re-generate.
 320
 321 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 322
 323         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 324         immediate in br.n instruction.
 325
 326 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-dis.c (XMGatherD, VexGatherD): New.
 329         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 330         (print_insn): Check masking for S/G insns.
 331         (OP_E_memory): New local variable check_gather. Extend mandatory
 332         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 333         Extend check for disallowed 16-bit addressing.
 334         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 335         if()s to switch(). Check register conflicts for (VEX-encoded)
 336         gathers. Drop no longer reachable cases.
 337         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 338         vgatherdp*.
 339
 340 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 341
 342         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 343         zeroing-masking without masking.
 344
 345 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 348         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 349         single-operand forms as deprecated.
 350         * i386-tbl.h: Re-generate.
 351
 352 2021-03-25  Alan Modra  <amodra@gmail.com>
 353
 354         PR 27647
 355         * ppc-opc.c (XLOCB_MASK): Delete.
 356         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 357         XLBH_MASK.
 358         (powerpc_opcodes): Accept a BH field on all extended forms of
 359         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 360
 361 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 362
 363         * i386-gen.c (output_i386_opcode): Drop processing of
 364         opcode_length. Calculate length from base_opcode. Adjust prefix
 365         encoding determination.
 366         (process_i386_opcodes): Drop output of fake opcode_length.
 367         * i386-opc.h (struct insn_template): Drop opcode_length field.
 368         * i386-opc.tbl: Drop opcode length field from all templates.
 369         * i386-tbl.h: Re-generate.
 370
 371 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 374         parameter "prefix". Drop local variable "regular_encoding".
 375         Record prefix setting / check for consistency.
 376         (output_i386_opcode): Parse opcode_length and base_opcode
 377         earlier. Derive prefix encoding. Drop no longer applicable
 378         consistency checking. Adjust process_i386_opcode_modifier()
 379         invocation.
 380         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 381         invocation.
 382         * i386-tbl.h: Re-generate.
 383
 384 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 387         check.
 388         * i386-opc.h (Prefix_*): Move #define-s.
 389         * i386-opc.tbl: Move pseudo prefix enumerator values to
 390         extension opcode field. Introduce pseudopfx template.
 391         * i386-tbl.h: Re-generate.
 392
 393 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 396         comment.
 397         * i386-tbl.h: Re-generate.
 398
 399 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 400
 401         * i386-opc.h (struct insn_template): Move cpu_flags field past
 402         opcode_modifier one.
 403         * i386-tbl.h: Re-generate.
 404
 405 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 408         * i386-opc.h (OpcodeSpace): New enumerator.
 409         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 410         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 411         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 412         (struct i386_opcode_modifier): New field opcodespace. Shrink
 413         opcodeprefix field.
 414         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 415         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 416         OpcodePrefix uses.
 417         * i386-tbl.h: Re-generate.
 418
 419 2021-03-22  Martin Liska  <mliska@suse.cz>
 420
 421         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 422         * arc-dis.c (parse_option): Likewise.
 423         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 424         * cris-dis.c (print_with_operands): Likewise.
 425         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 426         * i386-dis.c (print_insn): Likewise.
 427         * ia64-gen.c (fetch_insn_class): Likewise.
 428         (parse_resource_users): Likewise.
 429         (in_iclass): Likewise.
 430         (lookup_specifier): Likewise.
 431         (insert_opcode_dependencies): Likewise.
 432         * mips-dis.c (parse_mips_ase_option): Likewise.
 433         (parse_mips_dis_option): Likewise.
 434         * s390-dis.c (disassemble_init_s390): Likewise.
 435         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 436
 437 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 438
 439         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 440
 441 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 442
 443         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 444         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 445
 446 2021-03-12  Alan Modra  <amodra@gmail.com>
 447
 448         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 449
 450 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 451
 452         * i386-dis.c (OP_XMM): Re-order checks.
 453
 454 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 455
 456         * i386-dis.c (putop): Drop need_vex check when also checking
 457         vex.evex.
 458         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 459         checking vex.b.
 460
 461 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 462
 463         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 464         checks. Move case label past broadcast check.
 465
 466 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 467
 468         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 469         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 470         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 471         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 472         EVEX_W_0F38C7_M_0_L_2): Delete.
 473         (REG_EVEX_0F38C7_M_0_L_2): New.
 474         (intel_operand_size): Handle VEX and EVEX the same for
 475         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 476         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 477         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 478         vex_vsib_q_w_d_mode uses.
 479         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 480         0F38A1, and 0F38A3 entries.
 481         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 482         entry.
 483         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 484         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 485         0F38A3 entries.
 486
 487 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 488
 489         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 490         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 491         MOD_VEX_0FXOP_09_12): Rename to ...
 492         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 493         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 494         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 495         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 496         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 497         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 498         (reg_table): Adjust comments.
 499         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 500         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 501         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 502         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 503         (vex_len_table): Adjust opcode 0A_12 entry.
 504         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 505         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 506         (rm_table): Move hreset entry.
 507
 508 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 509
 510         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 511         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 512         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 513         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 514         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 515         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 516         (get_valid_dis386): Also handle 512-bit vector length when
 517         vectoring into vex_len_table[].
 518         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 519         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 520         entries.
 521         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 522         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 523         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 524         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 525         entries.
 526
 527 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 528
 529         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 530         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 531         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 532         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 533         entries.
 534         * i386-dis-evex-len.h (evex_len_table): Likewise.
 535         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 536
 537 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 538
 539         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 540         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 541         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 542         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 543         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 544         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 545         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 546         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 547         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 548         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 549         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 550         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 551         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 552         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 553         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 554         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 555         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 556         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 557         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 558         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 559         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 560         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 561         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 562         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 563         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 564         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 565         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 566         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 567         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 568         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 569         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 570         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 571         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 572         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 573         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 574         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 575         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 576         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 577         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 578         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 579         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 580         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 581         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 582         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 583         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 584         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 585         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 586         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 587         EVEX_W_0F3A43_L_n): New.
 588         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 589         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 590         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 591         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 592         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 593         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 594         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 595         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 596         0F385B, 0F38C6, and 0F38C7 entries.
 597         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 598         0F38C6 and 0F38C7.
 599         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 600         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 601         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 602         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 603
 604 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 605
 606         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 607         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 608         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 609         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 610         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 611         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 612         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 613         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 614         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 615         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 616         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 617         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 618         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 619         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 620         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 621         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 622         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 623         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 624         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 625         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 626         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 627         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 628         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 629         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 630         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 631         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 632         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 633         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 634         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 635         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 636         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 637         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 638         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 639         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 640         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 641         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 642         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 643         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 644         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 645         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 646         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 647         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 648         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 649         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 650         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 651         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 652         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 653         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 654         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 655         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 656         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 657         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 658         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 659         VEX_W_0F99_P_2_LEN_0): Delete.
 660         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 661         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 662         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 663         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 664         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 665         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 666         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 667         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 668         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 669         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 670         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 671         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 672         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 673         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 674         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 675         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 676         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 677         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 678         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 679         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 680         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 681         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 682         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 683         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 684         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 685         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 686         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 687         (prefix_table): No longer link to vex_len_table[] for opcodes
 688         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 689         0F92, 0F93, 0F98, and 0F99.
 690         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 691         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 692         0F98, and 0F99.
 693         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 694         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 695         0F98, and 0F99.
 696         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 697         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 698         0F98, and 0F99.
 699         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 700         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 701         0F98, and 0F99.
 702
 703 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 704
 705         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 706         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 707         REG_VEX_0F73_M_0 respectively.
 708         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 709         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 710         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 711         MOD_VEX_0F73_REG_7): Delete.
 712         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 713         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 714         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 715         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 716         PREFIX_VEX_0F3AF0_L_0 respectively.
 717         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 718         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 719         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 720         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 721         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 722         VEX_LEN_0F38F7): New.
 723         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 724         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 725         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 726         0F38F3.
 727         (prefix_table): No longer link to vex_len_table[] for opcodes
 728         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 729         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 730         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 731         0F38F6, 0F38F7, and 0F3AF0.
 732         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 733         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 734         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 735         0F73.
 736
 737 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 738
 739         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 740         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 741         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 742         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 743         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 744         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 745         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 746         73.
 747         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 748         0F72, and 0F73.
 749         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 750         0F73.
 751
 752 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 753
 754         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 755         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 756         (reg_table): Don't link to mod_table[] where not needed. Add
 757         PREFIX_IGNORED to nop entries.
 758         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 759         (mod_table): Add nop entries next to prefetch ones. Drop
 760         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 761         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 762         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 763         PREFIX_OPCODE from endbr* entries.
 764         (get_valid_dis386): Also consider entry's name when zapping
 765         vindex.
 766         (print_insn): Handle PREFIX_IGNORED.
 767
 768 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 769
 770         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 771         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 772         element.
 773         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 774         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 775         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 776         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 777         (struct i386_opcode_modifier): Delete notrackprefixok,
 778         islockable, hleprefixok, and repprefixok fields. Add prefixok
 779         field.
 780         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 781         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 782         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 783         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 784         Replace HLEPrefixOk.
 785         * opcodes/i386-tbl.h: Re-generate.
 786
 787 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 788
 789         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 790         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 791         64-bit form.
 792         * opcodes/i386-tbl.h: Re-generate.
 793
 794 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 797         for {} instead of {0}. Don't look for '0'.
 798         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 799         size specifiers.
 800
 801 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 802
 803         PR 27158
 804         * riscv-dis.c (print_insn_args): Updated encoding macros.
 805         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 806         (match_c_addi16sp): Updated encoding macros.
 807         (match_c_lui): Likewise.
 808         (match_c_lui_with_hint): Likewise.
 809         (match_c_addi4spn): Likewise.
 810         (match_c_slli): Likewise.
 811         (match_slli_as_c_slli): Likewise.
 812         (match_c_slli64): Likewise.
 813         (match_srxi_as_c_srxi): Likewise.
 814         (riscv_insn_types): Added .insn css/cl/cs.
 815
 816 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 817
 818         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 819         (default_priv_spec): Updated type to riscv_spec_class.
 820         (parse_riscv_dis_option): Updated.
 821         * riscv-opc.c: Moved stuff and make the file tidy.
 822
 823 2021-02-17  Alan Modra  <amodra@gmail.com>
 824
 825         * wasm32-dis.c: Include limits.h.
 826         (CHAR_BIT): Provide backup define.
 827         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 828         Correct signed overflow checking.
 829
 830 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 831
 832         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 833         * i386-tbl.h: Re-generate.
 834
 835 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 836
 837         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 838         Oword.
 839         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 840
 841 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 842
 843         * s390-mkopc.c (main): Accept arch14 as cpu string.
 844         * s390-opc.txt: Add new arch14 instructions.
 845
 846 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 847
 848         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 849         favour of LIBINTL.
 850         * configure: Regenerated.
 851
 852 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 853
 854         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 855         * tic54x-opc.c (regs): Rename to ...
 856         (tic54x_regs): ... this.
 857         (mmregs): Rename to ...
 858         (tic54x_mmregs): ... this.
 859         (condition_codes): Rename to ...
 860         (tic54x_condition_codes): ... this.
 861         (cc2_codes): Rename to ...
 862         (tic54x_cc2_codes): ... this.
 863         (cc3_codes): Rename to ...
 864         (tic54x_cc3_codes): ... this.
 865         (status_bits): Rename to ...
 866         (tic54x_status_bits): ... this.
 867         (misc_symbols): Rename to ...
 868         (tic54x_misc_symbols): ... this.
 869
 870 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 871
 872         * riscv-opc.c (MASK_RVB_IMM): Removed.
 873         (riscv_opcodes): Removed zb* instructions.
 874         (riscv_ext_version_table): Removed versions for zb*.
 875
 876 2021-01-26  Alan Modra  <amodra@gmail.com>
 877
 878         * i386-gen.c (parse_template): Ensure entire template_instance
 879         is initialised.
 880
 881 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 882
 883         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 884         (riscv_fpr_names_abi): Likewise.
 885         (riscv_opcodes): Likewise.
 886         (riscv_insn_types): Likewise.
 887
 888 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 889
 890         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 891
 892 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 893
 894         * riscv-dis.c: Comments tidy and improvement.
 895         * riscv-opc.c: Likewise.
 896
 897 2021-01-13  Alan Modra  <amodra@gmail.com>
 898
 899         * Makefile.in: Regenerate.
 900
 901 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 902
 903         PR binutils/26792
 904         * configure.ac: Use GNU_MAKE_JOBSERVER.
 905         * aclocal.m4: Regenerated.
 906         * configure: Likewise.
 907
 908 2021-01-12  Nick Clifton  <nickc@redhat.com>
 909
 910         * po/sr.po: Updated Serbian translation.
 911
 912 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 913
 914         PR ld/27173
 915         * configure: Regenerated.
 916
 917 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 918
 919         * aarch64-asm-2.c: Regenerate.
 920         * aarch64-dis-2.c: Likewise.
 921         * aarch64-opc-2.c: Likewise.
 922         * aarch64-opc.c (aarch64_print_operand):
 923         Delete handling of AARCH64_OPND_CSRE_CSR.
 924         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 925         (CSRE): Likewise.
 926         (_CSRE_INSN): Likewise.
 927         (aarch64_opcode_table): Delete csr.
 928
 929 2021-01-11  Nick Clifton  <nickc@redhat.com>
 930
 931         * po/de.po: Updated German translation.
 932         * po/fr.po: Updated French translation.
 933         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 934         * po/sv.po: Updated Swedish translation.
 935         * po/uk.po: Updated Ukranian translation.
 936
 937 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 938
 939         * configure: Regenerated.
 940
 941 2021-01-09  Nick Clifton  <nickc@redhat.com>
 942
 943         * configure: Regenerate.
 944         * po/opcodes.pot: Regenerate.
 945
 946 2021-01-09  Nick Clifton  <nickc@redhat.com>
 947
 948         * 2.36 release branch crated.
 949
 950 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 951
 952         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 953         (DW, (XRC_MASK): Define.
 954         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 955
 956 2021-01-09  Alan Modra  <amodra@gmail.com>
 957
 958         * configure: Regenerate.
 959
 960 2021-01-08  Nick Clifton  <nickc@redhat.com>
 961
 962         * po/sv.po: Updated Swedish translation.
 963
 964 2021-01-08  Nick Clifton  <nickc@redhat.com>
 965
 966         PR 27129
 967         * aarch64-dis.c (determine_disassembling_preference): Move call to
 968         aarch64_match_operands_constraint outside of the assertion.
 969         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 970         Replace with a return of FALSE.
 971
 972         PR 27139
 973         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 974         core system register.
 975
 976 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 977
 978         * configure: Regenerate.
 979
 980 2021-01-07  Nick Clifton  <nickc@redhat.com>
 981
 982         * po/fr.po: Updated French translation.
 983
 984 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 985
 986         * m68k-opc.c (chkl): Change minimum architecture requirement to
 987         m68020.
 988
 989 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 990
 991         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 992
 993 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 994             Jim Wilson  <jimw@sifive.com>
 995             Andrew Waterman  <andrew@sifive.com>
 996             Maxim Blinov  <maxim.blinov@embecosm.com>
 997             Kito Cheng  <kito.cheng@sifive.com>
 998             Nelson Chu  <nelson.chu@sifive.com>
 999
1000         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1001         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1002
1003 2021-01-01  Alan Modra  <amodra@gmail.com>
1004
1005         Update year range in copyright notice of all files.
1006
1007 For older changes see ChangeLog-2020
1008 \f
1009 Copyright (C) 2021 Free Software Foundation, Inc.
1010
1011 Copying and distribution of this file, with or without modification,
1012 are permitted in any medium without royalty provided the copyright
1013 notice and this notice are preserved.
1014
1015 Local Variables:
1016 mode: change-log
1017 left-margin: 8
1018 fill-column: 74
1019 version-control: never
1020 End: