1 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
3 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
5 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
7 * nds32-asm.c (operand_fields): Remove the unused fields.
8 (nds32_opcodes): Remove the unused instructions.
9 * nds32-dis.c (nds32_ex9_info): Removed.
10 (nds32_parse_opcode): Updated.
11 (print_insn_nds32): Likewise.
12 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
13 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
14 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
15 build_opcode_hash_table): New functions.
16 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
17 nds32_opcode_table): New.
18 (hw_ktabs): Declare it to a pointer rather than an array.
19 (build_hash_table): Removed.
20 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
21 SYN_ROPT and upadte HW_GPR and HW_INT.
22 * nds32-dis.c (keywords): Remove const.
23 (match_field): New function.
24 (nds32_parse_opcode): Updated.
25 * disassemble.c (disassemble_init_for_target):
26 Add disassemble_init_nds32.
27 * nds32-dis.c (eum map_type): New.
28 (nds32_private_data): Likewise.
29 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
30 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
31 (print_insn_nds32): Updated.
32 * nds32-asm.c (parse_aext_reg): Add new parameter.
33 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
36 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
37 (operand_fields): Add new fields.
38 (nds32_opcodes): Add new instructions.
39 (keyword_aridxi_mx): New keyword.
40 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
42 (ALU2_1, ALU2_2, ALU2_3): New macros.
43 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
45 2018-09-17 Kito Cheng <kito@andestech.com>
47 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
49 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
52 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
53 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
54 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
55 (EVEX_LEN_0F7E_P_1): Likewise.
56 (EVEX_LEN_0F7E_P_2): Likewise.
57 (EVEX_LEN_0FD6_P_2): Likewise.
58 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
59 (EVEX_LEN_TABLE): Likewise.
60 (EVEX_LEN_0F6E_P_2): New enum.
61 (EVEX_LEN_0F7E_P_1): Likewise.
62 (EVEX_LEN_0F7E_P_2): Likewise.
63 (EVEX_LEN_0FD6_P_2): Likewise.
64 (evex_len_table): New.
65 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
66 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
67 * i386-tbl.h: Regenerated.
69 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
72 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
73 VEX_LEN_0F7E_P_2 entries.
74 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
75 * i386-tbl.h: Regenerated.
77 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
79 * i386-dis.c (VZERO_Fixup): Removed.
81 (VEX_LEN_0F10_P_1): Likewise.
82 (VEX_LEN_0F10_P_3): Likewise.
83 (VEX_LEN_0F11_P_1): Likewise.
84 (VEX_LEN_0F11_P_3): Likewise.
85 (VEX_LEN_0F2E_P_0): Likewise.
86 (VEX_LEN_0F2E_P_2): Likewise.
87 (VEX_LEN_0F2F_P_0): Likewise.
88 (VEX_LEN_0F2F_P_2): Likewise.
89 (VEX_LEN_0F51_P_1): Likewise.
90 (VEX_LEN_0F51_P_3): Likewise.
91 (VEX_LEN_0F52_P_1): Likewise.
92 (VEX_LEN_0F53_P_1): Likewise.
93 (VEX_LEN_0F58_P_1): Likewise.
94 (VEX_LEN_0F58_P_3): Likewise.
95 (VEX_LEN_0F59_P_1): Likewise.
96 (VEX_LEN_0F59_P_3): Likewise.
97 (VEX_LEN_0F5A_P_1): Likewise.
98 (VEX_LEN_0F5A_P_3): Likewise.
99 (VEX_LEN_0F5C_P_1): Likewise.
100 (VEX_LEN_0F5C_P_3): Likewise.
101 (VEX_LEN_0F5D_P_1): Likewise.
102 (VEX_LEN_0F5D_P_3): Likewise.
103 (VEX_LEN_0F5E_P_1): Likewise.
104 (VEX_LEN_0F5E_P_3): Likewise.
105 (VEX_LEN_0F5F_P_1): Likewise.
106 (VEX_LEN_0F5F_P_3): Likewise.
107 (VEX_LEN_0FC2_P_1): Likewise.
108 (VEX_LEN_0FC2_P_3): Likewise.
109 (VEX_LEN_0F3A0A_P_2): Likewise.
110 (VEX_LEN_0F3A0B_P_2): Likewise.
111 (VEX_W_0F10_P_0): Likewise.
112 (VEX_W_0F10_P_1): Likewise.
113 (VEX_W_0F10_P_2): Likewise.
114 (VEX_W_0F10_P_3): Likewise.
115 (VEX_W_0F11_P_0): Likewise.
116 (VEX_W_0F11_P_1): Likewise.
117 (VEX_W_0F11_P_2): Likewise.
118 (VEX_W_0F11_P_3): Likewise.
119 (VEX_W_0F12_P_0_M_0): Likewise.
120 (VEX_W_0F12_P_0_M_1): Likewise.
121 (VEX_W_0F12_P_1): Likewise.
122 (VEX_W_0F12_P_2): Likewise.
123 (VEX_W_0F12_P_3): Likewise.
124 (VEX_W_0F13_M_0): Likewise.
125 (VEX_W_0F14): Likewise.
126 (VEX_W_0F15): Likewise.
127 (VEX_W_0F16_P_0_M_0): Likewise.
128 (VEX_W_0F16_P_0_M_1): Likewise.
129 (VEX_W_0F16_P_1): Likewise.
130 (VEX_W_0F16_P_2): Likewise.
131 (VEX_W_0F17_M_0): Likewise.
132 (VEX_W_0F28): Likewise.
133 (VEX_W_0F29): Likewise.
134 (VEX_W_0F2B_M_0): Likewise.
135 (VEX_W_0F2E_P_0): Likewise.
136 (VEX_W_0F2E_P_2): Likewise.
137 (VEX_W_0F2F_P_0): Likewise.
138 (VEX_W_0F2F_P_2): Likewise.
139 (VEX_W_0F50_M_0): Likewise.
140 (VEX_W_0F51_P_0): Likewise.
141 (VEX_W_0F51_P_1): Likewise.
142 (VEX_W_0F51_P_2): Likewise.
143 (VEX_W_0F51_P_3): Likewise.
144 (VEX_W_0F52_P_0): Likewise.
145 (VEX_W_0F52_P_1): Likewise.
146 (VEX_W_0F53_P_0): Likewise.
147 (VEX_W_0F53_P_1): Likewise.
148 (VEX_W_0F58_P_0): Likewise.
149 (VEX_W_0F58_P_1): Likewise.
150 (VEX_W_0F58_P_2): Likewise.
151 (VEX_W_0F58_P_3): Likewise.
152 (VEX_W_0F59_P_0): Likewise.
153 (VEX_W_0F59_P_1): Likewise.
154 (VEX_W_0F59_P_2): Likewise.
155 (VEX_W_0F59_P_3): Likewise.
156 (VEX_W_0F5A_P_0): Likewise.
157 (VEX_W_0F5A_P_1): Likewise.
158 (VEX_W_0F5A_P_3): Likewise.
159 (VEX_W_0F5B_P_0): Likewise.
160 (VEX_W_0F5B_P_1): Likewise.
161 (VEX_W_0F5B_P_2): Likewise.
162 (VEX_W_0F5C_P_0): Likewise.
163 (VEX_W_0F5C_P_1): Likewise.
164 (VEX_W_0F5C_P_2): Likewise.
165 (VEX_W_0F5C_P_3): Likewise.
166 (VEX_W_0F5D_P_0): Likewise.
167 (VEX_W_0F5D_P_1): Likewise.
168 (VEX_W_0F5D_P_2): Likewise.
169 (VEX_W_0F5D_P_3): Likewise.
170 (VEX_W_0F5E_P_0): Likewise.
171 (VEX_W_0F5E_P_1): Likewise.
172 (VEX_W_0F5E_P_2): Likewise.
173 (VEX_W_0F5E_P_3): Likewise.
174 (VEX_W_0F5F_P_0): Likewise.
175 (VEX_W_0F5F_P_1): Likewise.
176 (VEX_W_0F5F_P_2): Likewise.
177 (VEX_W_0F5F_P_3): Likewise.
178 (VEX_W_0F60_P_2): Likewise.
179 (VEX_W_0F61_P_2): Likewise.
180 (VEX_W_0F62_P_2): Likewise.
181 (VEX_W_0F63_P_2): Likewise.
182 (VEX_W_0F64_P_2): Likewise.
183 (VEX_W_0F65_P_2): Likewise.
184 (VEX_W_0F66_P_2): Likewise.
185 (VEX_W_0F67_P_2): Likewise.
186 (VEX_W_0F68_P_2): Likewise.
187 (VEX_W_0F69_P_2): Likewise.
188 (VEX_W_0F6A_P_2): Likewise.
189 (VEX_W_0F6B_P_2): Likewise.
190 (VEX_W_0F6C_P_2): Likewise.
191 (VEX_W_0F6D_P_2): Likewise.
192 (VEX_W_0F6F_P_1): Likewise.
193 (VEX_W_0F6F_P_2): Likewise.
194 (VEX_W_0F70_P_1): Likewise.
195 (VEX_W_0F70_P_2): Likewise.
196 (VEX_W_0F70_P_3): Likewise.
197 (VEX_W_0F71_R_2_P_2): Likewise.
198 (VEX_W_0F71_R_4_P_2): Likewise.
199 (VEX_W_0F71_R_6_P_2): Likewise.
200 (VEX_W_0F72_R_2_P_2): Likewise.
201 (VEX_W_0F72_R_4_P_2): Likewise.
202 (VEX_W_0F72_R_6_P_2): Likewise.
203 (VEX_W_0F73_R_2_P_2): Likewise.
204 (VEX_W_0F73_R_3_P_2): Likewise.
205 (VEX_W_0F73_R_6_P_2): Likewise.
206 (VEX_W_0F73_R_7_P_2): Likewise.
207 (VEX_W_0F74_P_2): Likewise.
208 (VEX_W_0F75_P_2): Likewise.
209 (VEX_W_0F76_P_2): Likewise.
210 (VEX_W_0F77_P_0): Likewise.
211 (VEX_W_0F7C_P_2): Likewise.
212 (VEX_W_0F7C_P_3): Likewise.
213 (VEX_W_0F7D_P_2): Likewise.
214 (VEX_W_0F7D_P_3): Likewise.
215 (VEX_W_0F7E_P_1): Likewise.
216 (VEX_W_0F7F_P_1): Likewise.
217 (VEX_W_0F7F_P_2): Likewise.
218 (VEX_W_0FAE_R_2_M_0): Likewise.
219 (VEX_W_0FAE_R_3_M_0): Likewise.
220 (VEX_W_0FC2_P_0): Likewise.
221 (VEX_W_0FC2_P_1): Likewise.
222 (VEX_W_0FC2_P_2): Likewise.
223 (VEX_W_0FC2_P_3): Likewise.
224 (VEX_W_0FD0_P_2): Likewise.
225 (VEX_W_0FD0_P_3): Likewise.
226 (VEX_W_0FD1_P_2): Likewise.
227 (VEX_W_0FD2_P_2): Likewise.
228 (VEX_W_0FD3_P_2): Likewise.
229 (VEX_W_0FD4_P_2): Likewise.
230 (VEX_W_0FD5_P_2): Likewise.
231 (VEX_W_0FD6_P_2): Likewise.
232 (VEX_W_0FD7_P_2_M_1): Likewise.
233 (VEX_W_0FD8_P_2): Likewise.
234 (VEX_W_0FD9_P_2): Likewise.
235 (VEX_W_0FDA_P_2): Likewise.
236 (VEX_W_0FDB_P_2): Likewise.
237 (VEX_W_0FDC_P_2): Likewise.
238 (VEX_W_0FDD_P_2): Likewise.
239 (VEX_W_0FDE_P_2): Likewise.
240 (VEX_W_0FDF_P_2): Likewise.
241 (VEX_W_0FE0_P_2): Likewise.
242 (VEX_W_0FE1_P_2): Likewise.
243 (VEX_W_0FE2_P_2): Likewise.
244 (VEX_W_0FE3_P_2): Likewise.
245 (VEX_W_0FE4_P_2): Likewise.
246 (VEX_W_0FE5_P_2): Likewise.
247 (VEX_W_0FE6_P_1): Likewise.
248 (VEX_W_0FE6_P_2): Likewise.
249 (VEX_W_0FE6_P_3): Likewise.
250 (VEX_W_0FE7_P_2_M_0): Likewise.
251 (VEX_W_0FE8_P_2): Likewise.
252 (VEX_W_0FE9_P_2): Likewise.
253 (VEX_W_0FEA_P_2): Likewise.
254 (VEX_W_0FEB_P_2): Likewise.
255 (VEX_W_0FEC_P_2): Likewise.
256 (VEX_W_0FED_P_2): Likewise.
257 (VEX_W_0FEE_P_2): Likewise.
258 (VEX_W_0FEF_P_2): Likewise.
259 (VEX_W_0FF0_P_3_M_0): Likewise.
260 (VEX_W_0FF1_P_2): Likewise.
261 (VEX_W_0FF2_P_2): Likewise.
262 (VEX_W_0FF3_P_2): Likewise.
263 (VEX_W_0FF4_P_2): Likewise.
264 (VEX_W_0FF5_P_2): Likewise.
265 (VEX_W_0FF6_P_2): Likewise.
266 (VEX_W_0FF7_P_2): Likewise.
267 (VEX_W_0FF8_P_2): Likewise.
268 (VEX_W_0FF9_P_2): Likewise.
269 (VEX_W_0FFA_P_2): Likewise.
270 (VEX_W_0FFB_P_2): Likewise.
271 (VEX_W_0FFC_P_2): Likewise.
272 (VEX_W_0FFD_P_2): Likewise.
273 (VEX_W_0FFE_P_2): Likewise.
274 (VEX_W_0F3800_P_2): Likewise.
275 (VEX_W_0F3801_P_2): Likewise.
276 (VEX_W_0F3802_P_2): Likewise.
277 (VEX_W_0F3803_P_2): Likewise.
278 (VEX_W_0F3804_P_2): Likewise.
279 (VEX_W_0F3805_P_2): Likewise.
280 (VEX_W_0F3806_P_2): Likewise.
281 (VEX_W_0F3807_P_2): Likewise.
282 (VEX_W_0F3808_P_2): Likewise.
283 (VEX_W_0F3809_P_2): Likewise.
284 (VEX_W_0F380A_P_2): Likewise.
285 (VEX_W_0F380B_P_2): Likewise.
286 (VEX_W_0F3817_P_2): Likewise.
287 (VEX_W_0F381C_P_2): Likewise.
288 (VEX_W_0F381D_P_2): Likewise.
289 (VEX_W_0F381E_P_2): Likewise.
290 (VEX_W_0F3820_P_2): Likewise.
291 (VEX_W_0F3821_P_2): Likewise.
292 (VEX_W_0F3822_P_2): Likewise.
293 (VEX_W_0F3823_P_2): Likewise.
294 (VEX_W_0F3824_P_2): Likewise.
295 (VEX_W_0F3825_P_2): Likewise.
296 (VEX_W_0F3828_P_2): Likewise.
297 (VEX_W_0F3829_P_2): Likewise.
298 (VEX_W_0F382A_P_2_M_0): Likewise.
299 (VEX_W_0F382B_P_2): Likewise.
300 (VEX_W_0F3830_P_2): Likewise.
301 (VEX_W_0F3831_P_2): Likewise.
302 (VEX_W_0F3832_P_2): Likewise.
303 (VEX_W_0F3833_P_2): Likewise.
304 (VEX_W_0F3834_P_2): Likewise.
305 (VEX_W_0F3835_P_2): Likewise.
306 (VEX_W_0F3837_P_2): Likewise.
307 (VEX_W_0F3838_P_2): Likewise.
308 (VEX_W_0F3839_P_2): Likewise.
309 (VEX_W_0F383A_P_2): Likewise.
310 (VEX_W_0F383B_P_2): Likewise.
311 (VEX_W_0F383C_P_2): Likewise.
312 (VEX_W_0F383D_P_2): Likewise.
313 (VEX_W_0F383E_P_2): Likewise.
314 (VEX_W_0F383F_P_2): Likewise.
315 (VEX_W_0F3840_P_2): Likewise.
316 (VEX_W_0F3841_P_2): Likewise.
317 (VEX_W_0F38DB_P_2): Likewise.
318 (VEX_W_0F3A08_P_2): Likewise.
319 (VEX_W_0F3A09_P_2): Likewise.
320 (VEX_W_0F3A0A_P_2): Likewise.
321 (VEX_W_0F3A0B_P_2): Likewise.
322 (VEX_W_0F3A0C_P_2): Likewise.
323 (VEX_W_0F3A0D_P_2): Likewise.
324 (VEX_W_0F3A0E_P_2): Likewise.
325 (VEX_W_0F3A0F_P_2): Likewise.
326 (VEX_W_0F3A21_P_2): Likewise.
327 (VEX_W_0F3A40_P_2): Likewise.
328 (VEX_W_0F3A41_P_2): Likewise.
329 (VEX_W_0F3A42_P_2): Likewise.
330 (VEX_W_0F3A62_P_2): Likewise.
331 (VEX_W_0F3A63_P_2): Likewise.
332 (VEX_W_0F3ADF_P_2): Likewise.
333 (VEX_LEN_0F77_P_0): New.
334 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
335 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
336 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
337 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
338 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
339 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
340 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
341 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
342 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
343 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
344 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
345 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
346 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
347 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
348 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
349 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
350 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
351 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
352 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
353 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
354 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
355 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
356 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
357 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
358 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
359 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
360 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
361 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
362 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
363 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
364 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
365 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
366 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
367 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
368 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
369 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
370 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
371 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
372 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
373 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
374 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
375 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
376 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
377 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
378 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
379 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
380 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
381 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
382 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
383 (vex_table): Update VEX 0F28 and 0F29 entries.
384 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
385 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
386 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
387 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
388 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
389 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
390 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
391 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
392 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
393 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
394 VEX_LEN_0F3A0B_P_2 entries.
395 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
396 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
397 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
398 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
399 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
400 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
401 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
402 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
403 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
404 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
405 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
406 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
407 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
408 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
409 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
410 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
411 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
412 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
413 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
414 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
415 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
416 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
417 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
418 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
419 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
420 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
421 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
422 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
423 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
424 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
425 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
426 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
427 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
428 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
429 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
430 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
431 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
432 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
433 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
434 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
435 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
436 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
437 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
438 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
439 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
440 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
441 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
442 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
443 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
444 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
445 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
446 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
447 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
448 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
449 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
450 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
451 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
452 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
453 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
454 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
455 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
456 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
457 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
458 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
459 VEX_W_0F3ADF_P_2 entries.
460 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
461 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
462 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
464 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
466 * i386-opc.tbl (VexWIG): New.
467 Replace VexW=3 with VexWIG.
469 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
471 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
472 * i386-tbl.h: Regenerated.
474 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
477 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
478 VEX_LEN_0FD6_P_2 entries.
479 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
480 * i386-tbl.h: Regenerated.
482 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
485 * i386-opc.h (VEXWIG): New.
486 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
487 * i386-tbl.h: Regenerated.
489 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
492 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
493 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
494 * i386-dis.c (EXxEVexR64): New.
495 (evex_rounding_64_mode): Likewise.
496 (OP_Rounding): Handle evex_rounding_64_mode.
498 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
501 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
502 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
503 * i386-dis.c (Edqa): New.
504 (dqa_mode): Likewise.
505 (intel_operand_size): Handle dqa_mode as m_mode.
506 (OP_E_register): Handle dqa_mode as dq_mode.
507 (OP_E_memory): Set shift for dqa_mode based on address_mode.
509 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
511 * i386-dis.c (OP_E_memory): Reformat.
513 2018-09-14 Jan Beulich <jbeulich@suse.com>
515 * i386-opc.tbl (crc32): Fold byte and word forms.
516 * i386-tbl.h: Re-generate.
518 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
520 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
521 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
522 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
523 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
524 * i386-tbl.h: Regenerated.
526 2018-09-13 Jan Beulich <jbeulich@suse.com>
528 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
530 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
531 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
532 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
533 * i386-tbl.h: Re-generate.
535 2018-09-13 Jan Beulich <jbeulich@suse.com>
537 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
539 * i386-tbl.h: Re-generate.
541 2018-09-13 Jan Beulich <jbeulich@suse.com>
543 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
545 * i386-tbl.h: Re-generate.
547 2018-09-13 Jan Beulich <jbeulich@suse.com>
549 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
551 * i386-tbl.h: Re-generate.
553 2018-09-13 Jan Beulich <jbeulich@suse.com>
555 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
557 * i386-tbl.h: Re-generate.
559 2018-09-13 Jan Beulich <jbeulich@suse.com>
561 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
563 * i386-tbl.h: Re-generate.
565 2018-09-13 Jan Beulich <jbeulich@suse.com>
567 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
569 * i386-tbl.h: Re-generate.
571 2018-09-13 Jan Beulich <jbeulich@suse.com>
573 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
574 * i386-tbl.h: Re-generate.
576 2018-09-13 Jan Beulich <jbeulich@suse.com>
578 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
579 * i386-tbl.h: Re-generate.
581 2018-09-13 Jan Beulich <jbeulich@suse.com>
583 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
585 * i386-tbl.h: Re-generate.
587 2018-09-13 Jan Beulich <jbeulich@suse.com>
589 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
591 * i386-tbl.h: Re-generate.
593 2018-09-13 Jan Beulich <jbeulich@suse.com>
595 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
596 * i386-tbl.h: Re-generate.
598 2018-09-13 Jan Beulich <jbeulich@suse.com>
600 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
601 * i386-tbl.h: Re-generate.
603 2018-09-13 Jan Beulich <jbeulich@suse.com>
605 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
606 * i386-tbl.h: Re-generate.
608 2018-09-13 Jan Beulich <jbeulich@suse.com>
610 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
612 * i386-tbl.h: Re-generate.
614 2018-09-13 Jan Beulich <jbeulich@suse.com>
616 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
618 * i386-tbl.h: Re-generate.
620 2018-09-13 Jan Beulich <jbeulich@suse.com>
622 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
624 * i386-tbl.h: Re-generate.
626 2018-09-13 Jan Beulich <jbeulich@suse.com>
628 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
629 * i386-tbl.h: Re-generate.
631 2018-09-13 Jan Beulich <jbeulich@suse.com>
633 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
634 * i386-tbl.h: Re-generate.
636 2018-09-13 Jan Beulich <jbeulich@suse.com>
638 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
639 * i386-tbl.h: Re-generate.
641 2018-09-13 Jan Beulich <jbeulich@suse.com>
643 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
644 (vpbroadcastw, rdpid): Drop NoRex64.
645 * i386-tbl.h: Re-generate.
647 2018-09-13 Jan Beulich <jbeulich@suse.com>
649 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
650 store templates, adding D.
651 * i386-tbl.h: Re-generate.
653 2018-09-13 Jan Beulich <jbeulich@suse.com>
655 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
656 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
657 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
658 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
659 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
660 Fold load and store templates where possible, adding D. Drop
661 IgnoreSize where it was pointlessly present. Drop redundant
663 * i386-tbl.h: Re-generate.
665 2018-09-13 Jan Beulich <jbeulich@suse.com>
667 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
668 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
669 (intel_operand_size): Handle v_bndmk_mode.
670 (OP_E_memory): Likewise. Produce (bad) when also riprel.
672 2018-09-08 John Darrington <john@darrington.wattle.id.au>
674 * disassemble.c (ARCH_s12z): Define if ARCH_all.
676 2018-08-31 Kito Cheng <kito@andestech.com>
678 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
679 compressed floating point instructions.
681 2018-08-30 Kito Cheng <kito@andestech.com>
683 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
684 riscv_opcode.xlen_requirement.
685 * riscv-opc.c (riscv_opcodes): Update for struct change.
687 2018-08-29 Martin Aberg <maberg@gaisler.com>
689 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
690 psr (PWRPSR) instruction.
692 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
694 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
696 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
698 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
700 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
702 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
703 loongson3a as an alias of gs464 for compatibility.
704 * mips-opc.c (mips_opcodes): Change Comments.
706 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
708 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
710 (print_mips_disassembler_options): Document -M loongson-ext.
711 * mips-opc.c (LEXT2): New macro.
712 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
714 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
716 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
718 (parse_mips_ase_option): Handle -M loongson-ext option.
719 (print_mips_disassembler_options): Document -M loongson-ext.
720 * mips-opc.c (IL3A): Delete.
721 * mips-opc.c (LEXT): New macro.
722 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
725 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
727 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
729 (parse_mips_ase_option): Handle -M loongson-cam option.
730 (print_mips_disassembler_options): Document -M loongson-cam.
731 * mips-opc.c (LCAM): New macro.
732 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
735 2018-08-21 Alan Modra <amodra@gmail.com>
737 * ppc-dis.c (operand_value_powerpc): Init "invalid".
738 (skip_optional_operands): Count optional operands, and update
739 ppc_optional_operand_value call.
740 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
741 (extract_vlensi): Likewise.
742 (extract_fxm): Return default value for missing optional operand.
743 (extract_ls, extract_raq, extract_tbr): Likewise.
744 (insert_sxl, extract_sxl): New functions.
745 (insert_esync, extract_esync): Remove Power9 handling and simplify.
746 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
747 flag and extra entry.
748 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
751 2018-08-20 Alan Modra <amodra@gmail.com>
753 * sh-opc.h (MASK): Simplify.
755 2018-08-18 John Darrington <john@darrington.wattle.id.au>
757 * s12z-dis.c (bm_decode): Deal with cases where the mode is
758 BM_RESERVED0 or BM_RESERVED1
759 (bm_rel_decode, bm_n_bytes): Ditto.
761 2018-08-18 John Darrington <john@darrington.wattle.id.au>
765 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
767 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
768 address with the addr32 prefix and without base nor index
771 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
773 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
774 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
775 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
776 (cpu_flags): Add CpuCMOV and CpuFXSR.
777 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
778 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
779 * i386-init.h: Regenerated.
780 * i386-tbl.h: Likewise.
782 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
784 * arc-regs.h: Update auxiliary registers.
786 2018-08-06 Jan Beulich <jbeulich@suse.com>
788 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
789 (RegIP, RegIZ): Define.
790 * i386-reg.tbl: Adjust comments.
791 (rip): Use Qword instead of BaseIndex. Use RegIP.
792 (eip): Use Dword instead of BaseIndex. Use RegIP.
793 (riz): Add Qword. Use RegIZ.
794 (eiz): Add Dword. Use RegIZ.
795 * i386-tbl.h: Re-generate.
797 2018-08-03 Jan Beulich <jbeulich@suse.com>
799 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
800 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
801 vpmovzxdq, vpmovzxwd): Remove NoRex64.
802 * i386-tbl.h: Re-generate.
804 2018-08-03 Jan Beulich <jbeulich@suse.com>
806 * i386-gen.c (operand_types): Remove Mem field.
807 * i386-opc.h (union i386_operand_type): Remove mem field.
808 * i386-init.h, i386-tbl.h: Re-generate.
810 2018-08-01 Alan Modra <amodra@gmail.com>
812 * po/POTFILES.in: Regenerate.
814 2018-07-31 Nick Clifton <nickc@redhat.com>
816 * po/sv.po: Updated Swedish translation.
818 2018-07-31 Jan Beulich <jbeulich@suse.com>
820 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
821 * i386-init.h, i386-tbl.h: Re-generate.
823 2018-07-31 Jan Beulich <jbeulich@suse.com>
825 * i386-opc.h (ZEROING_MASKING) Rename to ...
826 (DYNAMIC_MASKING): ... this. Adjust comment.
827 * i386-opc.tbl (MaskingMorZ): Define.
828 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
829 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
830 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
831 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
832 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
833 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
834 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
835 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
836 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
838 2018-07-31 Jan Beulich <jbeulich@suse.com>
840 * i386-opc.tbl: Use element rather than vector size for AVX512*
841 scatter/gather insns.
842 * i386-tbl.h: Re-generate.
844 2018-07-31 Jan Beulich <jbeulich@suse.com>
846 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
847 (cpu_flags): Drop CpuVREX.
848 * i386-opc.h (CpuVREX): Delete.
849 (union i386_cpu_flags): Remove cpuvrex.
850 * i386-init.h, i386-tbl.h: Re-generate.
852 2018-07-30 Jim Wilson <jimw@sifive.com>
854 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
856 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
858 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
860 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
861 * Makefile.in: Regenerated.
862 * configure.ac: Add C-SKY.
863 * configure: Regenerated.
864 * csky-dis.c: New file.
865 * csky-opc.h: New file.
866 * disassemble.c (ARCH_csky): Define.
867 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
868 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
870 2018-07-27 Alan Modra <amodra@gmail.com>
872 * ppc-opc.c (insert_sprbat): Correct function parameter and
874 (extract_sprbat): Likewise, variable too.
876 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
877 Alan Modra <amodra@gmail.com>
879 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
880 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
881 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
882 support disjointed BAT.
883 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
884 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
885 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
887 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
888 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
890 * i386-gen.c (adjust_broadcast_modifier): New function.
891 (process_i386_opcode_modifier): Add an argument for operands.
892 Adjust the Broadcast value based on operands.
893 (output_i386_opcode): Pass operand_types to
894 process_i386_opcode_modifier.
895 (process_i386_opcodes): Pass NULL as operands to
896 process_i386_opcode_modifier.
897 * i386-opc.h (BYTE_BROADCAST): New.
898 (WORD_BROADCAST): Likewise.
899 (DWORD_BROADCAST): Likewise.
900 (QWORD_BROADCAST): Likewise.
901 (i386_opcode_modifier): Expand broadcast to 3 bits.
902 * i386-tbl.h: Regenerated.
904 2018-07-24 Alan Modra <amodra@gmail.com>
907 * or1k-desc.h: Regenerate.
909 2018-07-24 Jan Beulich <jbeulich@suse.com>
911 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
912 vcvtusi2ss, and vcvtusi2sd.
913 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
914 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
915 * i386-tbl.h: Re-generate.
917 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
919 * arc-opc.c (extract_w6): Fix extending the sign.
921 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
923 * arc-tbl.h (vewt): Allow it for ARC EM family.
925 2018-07-23 Alan Modra <amodra@gmail.com>
928 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
929 opcode variants for mtspr/mfspr encodings.
931 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
932 Maciej W. Rozycki <macro@mips.com>
934 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
935 loongson3a descriptors.
936 (parse_mips_ase_option): Handle -M loongson-mmi option.
937 (print_mips_disassembler_options): Document -M loongson-mmi.
938 * mips-opc.c (LMMI): New macro.
939 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
942 2018-07-19 Jan Beulich <jbeulich@suse.com>
944 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
945 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
946 IgnoreSize and [XYZ]MMword where applicable.
947 * i386-tbl.h: Re-generate.
949 2018-07-19 Jan Beulich <jbeulich@suse.com>
951 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
952 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
953 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
954 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
955 * i386-tbl.h: Re-generate.
957 2018-07-19 Jan Beulich <jbeulich@suse.com>
959 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
960 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
961 VPCLMULQDQ templates into their respective AVX512VL counterparts
962 where possible, using Disp8ShiftVL and CheckRegSize instead of
963 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
964 * i386-tbl.h: Re-generate.
966 2018-07-19 Jan Beulich <jbeulich@suse.com>
968 * i386-opc.tbl: Fold AVX512DQ templates into their respective
969 AVX512VL counterparts where possible, using Disp8ShiftVL and
970 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
971 IgnoreSize) as appropriate.
972 * i386-tbl.h: Re-generate.
974 2018-07-19 Jan Beulich <jbeulich@suse.com>
976 * i386-opc.tbl: Fold AVX512BW templates into their respective
977 AVX512VL counterparts where possible, using Disp8ShiftVL and
978 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
979 IgnoreSize) as appropriate.
980 * i386-tbl.h: Re-generate.
982 2018-07-19 Jan Beulich <jbeulich@suse.com>
984 * i386-opc.tbl: Fold AVX512CD templates into their respective
985 AVX512VL counterparts where possible, using Disp8ShiftVL and
986 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
987 IgnoreSize) as appropriate.
988 * i386-tbl.h: Re-generate.
990 2018-07-19 Jan Beulich <jbeulich@suse.com>
992 * i386-opc.h (DISP8_SHIFT_VL): New.
993 * i386-opc.tbl (Disp8ShiftVL): Define.
994 (various): Fold AVX512VL templates into their respective
995 AVX512F counterparts where possible, using Disp8ShiftVL and
996 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
997 IgnoreSize) as appropriate.
998 * i386-tbl.h: Re-generate.
1000 2018-07-19 Jan Beulich <jbeulich@suse.com>
1002 * Makefile.am: Change dependencies and rule for
1003 $(srcdir)/i386-init.h.
1004 * Makefile.in: Re-generate.
1005 * i386-gen.c (process_i386_opcodes): New local variable
1006 "marker". Drop opening of input file. Recognize marker and line
1008 * i386-opc.tbl (OPCODE_I386_H): Define.
1009 (i386-opc.h): Include it.
1012 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1015 * i386-opc.h (Byte): Update comments.
1021 (Xmmword): Likewise.
1022 (Ymmword): Likewise.
1023 (Zmmword): Likewise.
1024 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1026 * i386-tbl.h: Regenerated.
1028 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1030 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1031 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1032 * aarch64-asm-2.c: Regenerate.
1033 * aarch64-dis-2.c: Regenerate.
1034 * aarch64-opc-2.c: Regenerate.
1036 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1039 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1040 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1041 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1042 sqdmulh, sqrdmulh): Use Em16.
1044 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1046 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1047 csdb together with them.
1048 (thumb32_opcodes): Likewise.
1050 2018-07-11 Jan Beulich <jbeulich@suse.com>
1052 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1053 requiring 32-bit registers as operands 2 and 3. Improve
1055 (mwait, mwaitx): Fold templates. Improve comments.
1056 OPERAND_TYPE_INOUTPORTREG.
1057 * i386-tbl.h: Re-generate.
1059 2018-07-11 Jan Beulich <jbeulich@suse.com>
1061 * i386-gen.c (operand_type_init): Remove
1062 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1063 OPERAND_TYPE_INOUTPORTREG.
1064 * i386-init.h: Re-generate.
1066 2018-07-11 Jan Beulich <jbeulich@suse.com>
1068 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1069 (wrssq, wrussq): Add Qword.
1070 * i386-tbl.h: Re-generate.
1072 2018-07-11 Jan Beulich <jbeulich@suse.com>
1074 * i386-opc.h: Rename OTMax to OTNum.
1075 (OTNumOfUints): Adjust calculation.
1076 (OTUnused): Directly alias to OTNum.
1078 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1080 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1082 (lea_reg_xys): Likewise.
1083 (print_insn_loop_primitive): Rename `reg' local variable to
1086 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1089 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1091 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1094 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1095 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1097 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1100 * mips-dis.c (mips_option_arg_t): New enumeration.
1101 (mips_options): New variable.
1102 (disassembler_options_mips): New function.
1103 (print_mips_disassembler_options): Reimplement in terms of
1104 `disassembler_options_mips'.
1105 * arm-dis.c (disassembler_options_arm): Adapt to using the
1106 `disasm_options_and_args_t' structure.
1107 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1108 * s390-dis.c (disassembler_options_s390): Likewise.
1110 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1112 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1114 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1115 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1116 * testsuite/ld-arm/tls-longplt.d: Likewise.
1118 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1121 * aarch64-asm-2.c: Regenerate.
1122 * aarch64-dis-2.c: Likewise.
1123 * aarch64-opc-2.c: Likewise.
1124 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1125 * aarch64-opc.c (operand_general_constraint_met_p,
1126 aarch64_print_operand): Likewise.
1127 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1128 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1130 (AARCH64_OPERANDS): Add Em2.
1132 2018-06-26 Nick Clifton <nickc@redhat.com>
1134 * po/uk.po: Updated Ukranian translation.
1135 * po/de.po: Updated German translation.
1136 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1138 2018-06-26 Nick Clifton <nickc@redhat.com>
1140 * nfp-dis.c: Fix spelling mistake.
1142 2018-06-24 Nick Clifton <nickc@redhat.com>
1144 * configure: Regenerate.
1145 * po/opcodes.pot: Regenerate.
1147 2018-06-24 Nick Clifton <nickc@redhat.com>
1149 2.31 branch created.
1151 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1153 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1154 * aarch64-asm-2.c: Regenerate.
1155 * aarch64-dis-2.c: Likewise.
1157 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1159 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1160 `-M ginv' option description.
1162 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1165 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1168 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1170 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1171 * configure.ac: Remove AC_PREREQ.
1172 * Makefile.in: Re-generate.
1173 * aclocal.m4: Re-generate.
1174 * configure: Re-generate.
1176 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1178 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1179 mips64r6 descriptors.
1180 (parse_mips_ase_option): Handle -Mginv option.
1181 (print_mips_disassembler_options): Document -Mginv.
1182 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1184 (mips_opcodes): Define ginvi and ginvt.
1186 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1187 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1189 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1190 * mips-opc.c (CRC, CRC64): New macros.
1191 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1192 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1195 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1198 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1199 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1201 2018-06-06 Alan Modra <amodra@gmail.com>
1203 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1204 setjmp. Move init for some other vars later too.
1206 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1208 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1209 (dis_private): Add new fields for property section tracking.
1210 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1211 (xtensa_instruction_fits): New functions.
1212 (fetch_data): Bump minimal fetch size to 4.
1213 (print_insn_xtensa): Make struct dis_private static.
1214 Load and prepare property table on section change.
1215 Don't disassemble literals. Don't disassemble instructions that
1216 cross property table boundaries.
1218 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1220 * configure: Regenerated.
1222 2018-06-01 Jan Beulich <jbeulich@suse.com>
1224 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1225 * i386-tbl.h: Re-generate.
1227 2018-06-01 Jan Beulich <jbeulich@suse.com>
1229 * i386-opc.tbl (sldt, str): Add NoRex64.
1230 * i386-tbl.h: Re-generate.
1232 2018-06-01 Jan Beulich <jbeulich@suse.com>
1234 * i386-opc.tbl (invpcid): Add Oword.
1235 * i386-tbl.h: Re-generate.
1237 2018-06-01 Alan Modra <amodra@gmail.com>
1239 * sysdep.h (_bfd_error_handler): Don't declare.
1240 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1241 * rl78-decode.opc: Likewise.
1242 * msp430-decode.c: Regenerate.
1243 * rl78-decode.c: Regenerate.
1245 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1247 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1248 * i386-init.h : Regenerated.
1250 2018-05-25 Alan Modra <amodra@gmail.com>
1252 * Makefile.in: Regenerate.
1253 * po/POTFILES.in: Regenerate.
1255 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1257 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1258 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1259 (insert_bab, extract_bab, insert_btab, extract_btab,
1260 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1261 (BAT, BBA VBA RBS XB6S): Delete macros.
1262 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1263 (BB, BD, RBX, XC6): Update for new macros.
1264 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1265 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1266 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1267 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1269 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1271 * Makefile.am: Add support for s12z architecture.
1272 * configure.ac: Likewise.
1273 * disassemble.c: Likewise.
1274 * disassemble.h: Likewise.
1275 * Makefile.in: Regenerate.
1276 * configure: Regenerate.
1277 * s12z-dis.c: New file.
1280 2018-05-18 Alan Modra <amodra@gmail.com>
1282 * nfp-dis.c: Don't #include libbfd.h.
1283 (init_nfp3200_priv): Use bfd_get_section_contents.
1284 (nit_nfp6000_mecsr_sec): Likewise.
1286 2018-05-17 Nick Clifton <nickc@redhat.com>
1288 * po/zh_CN.po: Updated simplified Chinese translation.
1290 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1293 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1294 * aarch64-dis-2.c: Regenerate.
1296 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1299 * aarch64-asm.c (opintl.h): Include.
1300 (aarch64_ins_sysreg): Enforce read/write constraints.
1301 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1302 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1303 (F_REG_READ, F_REG_WRITE): New.
1304 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1305 AARCH64_OPND_SYSREG.
1306 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1307 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1308 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1309 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1310 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1311 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1312 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1313 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1314 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1315 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1316 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1317 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1318 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1319 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1320 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1321 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1322 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1324 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1327 * aarch64-dis.c (no_notes: New.
1328 (parse_aarch64_dis_option): Support notes.
1329 (aarch64_decode_insn, print_operands): Likewise.
1330 (print_aarch64_disassembler_options): Document notes.
1331 * aarch64-opc.c (aarch64_print_operand): Support notes.
1333 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1336 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1337 and take error struct.
1338 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1339 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1340 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1341 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1342 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1343 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1344 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1345 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1346 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1347 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1348 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1349 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1350 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1351 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1352 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1353 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1354 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1355 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1356 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1357 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1358 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1359 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1360 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1361 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1362 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1363 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1364 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1365 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1366 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1367 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1368 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1369 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1370 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1371 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1372 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1373 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1374 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1375 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1376 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1377 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1378 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1379 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1380 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1381 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1382 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1383 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1384 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1385 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1386 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1387 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1388 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1389 (determine_disassembling_preference, aarch64_decode_insn,
1390 print_insn_aarch64_word, print_insn_data): Take errors struct.
1391 (print_insn_aarch64): Use errors.
1392 * aarch64-asm-2.c: Regenerate.
1393 * aarch64-dis-2.c: Regenerate.
1394 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1395 boolean in aarch64_insert_operan.
1396 (print_operand_extractor): Likewise.
1397 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1399 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1401 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1403 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1405 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1407 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1409 * cr16-opc.c (cr16_instruction): Comment typo fix.
1410 * hppa-dis.c (print_insn_hppa): Likewise.
1412 2018-05-08 Jim Wilson <jimw@sifive.com>
1414 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1415 (match_c_slli64, match_srxi_as_c_srxi): New.
1416 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1417 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1418 <c.slli, c.srli, c.srai>: Use match_s_slli.
1419 <c.slli64, c.srli64, c.srai64>: New.
1421 2018-05-08 Alan Modra <amodra@gmail.com>
1423 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1424 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1425 partition opcode space for index lookup.
1427 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1429 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1430 <insn_length>: ...with this. Update usage.
1431 Remove duplicate call to *info->memory_error_func.
1433 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1434 H.J. Lu <hongjiu.lu@intel.com>
1436 * i386-dis.c (Gva): New.
1437 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1438 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1439 (prefix_table): New instructions (see prefix above).
1440 (mod_table): New instructions (see prefix above).
1441 (OP_G): Handle va_mode.
1442 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1443 CPU_MOVDIR64B_FLAGS.
1444 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1445 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1446 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1447 * i386-opc.tbl: Add movidir{i,64b}.
1448 * i386-init.h: Regenerated.
1449 * i386-tbl.h: Likewise.
1451 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1453 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1455 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1456 (AddrPrefixOpReg): This.
1457 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1458 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1460 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1462 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1463 (vle_num_opcodes): Likewise.
1464 (spe2_num_opcodes): Likewise.
1465 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1466 initialization loop.
1467 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1468 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1471 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1473 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1475 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1477 Makefile.am: Added nfp-dis.c.
1478 configure.ac: Added bfd_nfp_arch.
1479 disassemble.h: Added print_insn_nfp prototype.
1480 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1481 nfp-dis.c: New, for NFP support.
1482 po/POTFILES.in: Added nfp-dis.c to the list.
1483 Makefile.in: Regenerate.
1484 configure: Regenerate.
1486 2018-04-26 Jan Beulich <jbeulich@suse.com>
1488 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1489 templates into their base ones.
1490 * i386-tlb.h: Re-generate.
1492 2018-04-26 Jan Beulich <jbeulich@suse.com>
1494 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1495 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1496 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1497 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1498 * i386-init.h: Re-generate.
1500 2018-04-26 Jan Beulich <jbeulich@suse.com>
1502 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1503 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1504 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1505 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1507 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1509 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1511 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1512 cpuregzmm, and cpuregmask.
1513 * i386-init.h: Re-generate.
1514 * i386-tbl.h: Re-generate.
1516 2018-04-26 Jan Beulich <jbeulich@suse.com>
1518 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1519 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1520 * i386-init.h: Re-generate.
1522 2018-04-26 Jan Beulich <jbeulich@suse.com>
1524 * i386-gen.c (VexImmExt): Delete.
1525 * i386-opc.h (VexImmExt, veximmext): Delete.
1526 * i386-opc.tbl: Drop all VexImmExt uses.
1527 * i386-tlb.h: Re-generate.
1529 2018-04-25 Jan Beulich <jbeulich@suse.com>
1531 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1532 register-only forms.
1533 * i386-tlb.h: Re-generate.
1535 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1537 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1539 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1541 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1543 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1544 (cpu_flags): Add CpuCLDEMOTE.
1545 * i386-init.h: Regenerate.
1546 * i386-opc.h (enum): Add CpuCLDEMOTE,
1547 (i386_cpu_flags): Add cpucldemote.
1548 * i386-opc.tbl: Add cldemote.
1549 * i386-tbl.h: Regenerate.
1551 2018-04-16 Alan Modra <amodra@gmail.com>
1553 * Makefile.am: Remove sh5 and sh64 support.
1554 * configure.ac: Likewise.
1555 * disassemble.c: Likewise.
1556 * disassemble.h: Likewise.
1557 * sh-dis.c: Likewise.
1558 * sh64-dis.c: Delete.
1559 * sh64-opc.c: Delete.
1560 * sh64-opc.h: Delete.
1561 * Makefile.in: Regenerate.
1562 * configure: Regenerate.
1563 * po/POTFILES.in: Regenerate.
1565 2018-04-16 Alan Modra <amodra@gmail.com>
1567 * Makefile.am: Remove w65 support.
1568 * configure.ac: Likewise.
1569 * disassemble.c: Likewise.
1570 * disassemble.h: Likewise.
1571 * w65-dis.c: Delete.
1572 * w65-opc.h: Delete.
1573 * Makefile.in: Regenerate.
1574 * configure: Regenerate.
1575 * po/POTFILES.in: Regenerate.
1577 2018-04-16 Alan Modra <amodra@gmail.com>
1579 * configure.ac: Remove we32k support.
1580 * configure: Regenerate.
1582 2018-04-16 Alan Modra <amodra@gmail.com>
1584 * Makefile.am: Remove m88k support.
1585 * configure.ac: Likewise.
1586 * disassemble.c: Likewise.
1587 * disassemble.h: Likewise.
1588 * m88k-dis.c: Delete.
1589 * Makefile.in: Regenerate.
1590 * configure: Regenerate.
1591 * po/POTFILES.in: Regenerate.
1593 2018-04-16 Alan Modra <amodra@gmail.com>
1595 * Makefile.am: Remove i370 support.
1596 * configure.ac: Likewise.
1597 * disassemble.c: Likewise.
1598 * disassemble.h: Likewise.
1599 * i370-dis.c: Delete.
1600 * i370-opc.c: Delete.
1601 * Makefile.in: Regenerate.
1602 * configure: Regenerate.
1603 * po/POTFILES.in: Regenerate.
1605 2018-04-16 Alan Modra <amodra@gmail.com>
1607 * Makefile.am: Remove h8500 support.
1608 * configure.ac: Likewise.
1609 * disassemble.c: Likewise.
1610 * disassemble.h: Likewise.
1611 * h8500-dis.c: Delete.
1612 * h8500-opc.h: Delete.
1613 * Makefile.in: Regenerate.
1614 * configure: Regenerate.
1615 * po/POTFILES.in: Regenerate.
1617 2018-04-16 Alan Modra <amodra@gmail.com>
1619 * configure.ac: Remove tahoe support.
1620 * configure: Regenerate.
1622 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1624 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1626 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1628 * i386-tbl.h: Regenerated.
1630 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1632 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1633 PREFIX_MOD_1_0FAE_REG_6.
1635 (OP_E_register): Use va_mode.
1636 * i386-dis-evex.h (prefix_table):
1637 New instructions (see prefixes above).
1638 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1639 (cpu_flags): Likewise.
1640 * i386-opc.h (enum): Likewise.
1641 (i386_cpu_flags): Likewise.
1642 * i386-opc.tbl: Add umonitor, umwait, tpause.
1643 * i386-init.h: Regenerate.
1644 * i386-tbl.h: Likewise.
1646 2018-04-11 Alan Modra <amodra@gmail.com>
1648 * opcodes/i860-dis.c: Delete.
1649 * opcodes/i960-dis.c: Delete.
1650 * Makefile.am: Remove i860 and i960 support.
1651 * configure.ac: Likewise.
1652 * disassemble.c: Likewise.
1653 * disassemble.h: Likewise.
1654 * Makefile.in: Regenerate.
1655 * configure: Regenerate.
1656 * po/POTFILES.in: Regenerate.
1658 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1661 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1663 (print_insn): Clear vex instead of vex.evex.
1665 2018-04-04 Nick Clifton <nickc@redhat.com>
1667 * po/es.po: Updated Spanish translation.
1669 2018-03-28 Jan Beulich <jbeulich@suse.com>
1671 * i386-gen.c (opcode_modifiers): Delete VecESize.
1672 * i386-opc.h (VecESize): Delete.
1673 (struct i386_opcode_modifier): Delete vecesize.
1674 * i386-opc.tbl: Drop VecESize.
1675 * i386-tlb.h: Re-generate.
1677 2018-03-28 Jan Beulich <jbeulich@suse.com>
1679 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1680 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1681 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1682 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1683 * i386-tlb.h: Re-generate.
1685 2018-03-28 Jan Beulich <jbeulich@suse.com>
1687 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1689 * i386-tlb.h: Re-generate.
1691 2018-03-28 Jan Beulich <jbeulich@suse.com>
1693 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1694 (vex_len_table): Drop Y for vcvt*2si.
1695 (putop): Replace plain 'Y' handling by abort().
1697 2018-03-28 Nick Clifton <nickc@redhat.com>
1700 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1701 instructions with only a base address register.
1702 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1703 handle AARHC64_OPND_SVE_ADDR_R.
1704 (aarch64_print_operand): Likewise.
1705 * aarch64-asm-2.c: Regenerate.
1706 * aarch64_dis-2.c: Regenerate.
1707 * aarch64-opc-2.c: Regenerate.
1709 2018-03-22 Jan Beulich <jbeulich@suse.com>
1711 * i386-opc.tbl: Drop VecESize from register only insn forms and
1712 memory forms not allowing broadcast.
1713 * i386-tlb.h: Re-generate.
1715 2018-03-22 Jan Beulich <jbeulich@suse.com>
1717 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1718 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1719 sha256*): Drop Disp<N>.
1721 2018-03-22 Jan Beulich <jbeulich@suse.com>
1723 * i386-dis.c (EbndS, bnd_swap_mode): New.
1724 (prefix_table): Use EbndS.
1725 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1726 * i386-opc.tbl (bndmov): Move misplaced Load.
1727 * i386-tlb.h: Re-generate.
1729 2018-03-22 Jan Beulich <jbeulich@suse.com>
1731 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1732 templates allowing memory operands and folded ones for register
1734 * i386-tlb.h: Re-generate.
1736 2018-03-22 Jan Beulich <jbeulich@suse.com>
1738 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1739 256-bit templates. Drop redundant leftover Disp<N>.
1740 * i386-tlb.h: Re-generate.
1742 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1744 * riscv-opc.c (riscv_insn_types): New.
1746 2018-03-13 Nick Clifton <nickc@redhat.com>
1748 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1750 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1752 * i386-opc.tbl: Add Optimize to clr.
1753 * i386-tbl.h: Regenerated.
1755 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1757 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1758 * i386-opc.h (OldGcc): Removed.
1759 (i386_opcode_modifier): Remove oldgcc.
1760 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1761 instructions for old (<= 2.8.1) versions of gcc.
1762 * i386-tbl.h: Regenerated.
1764 2018-03-08 Jan Beulich <jbeulich@suse.com>
1766 * i386-opc.h (EVEXDYN): New.
1767 * i386-opc.tbl: Fold various AVX512VL templates.
1768 * i386-tlb.h: Re-generate.
1770 2018-03-08 Jan Beulich <jbeulich@suse.com>
1772 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1773 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1774 vpexpandd, vpexpandq): Fold AFX512VF templates.
1775 * i386-tlb.h: Re-generate.
1777 2018-03-08 Jan Beulich <jbeulich@suse.com>
1779 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1780 Fold 128- and 256-bit VEX-encoded templates.
1781 * i386-tlb.h: Re-generate.
1783 2018-03-08 Jan Beulich <jbeulich@suse.com>
1785 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1786 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1787 vpexpandd, vpexpandq): Fold AVX512F templates.
1788 * i386-tlb.h: Re-generate.
1790 2018-03-08 Jan Beulich <jbeulich@suse.com>
1792 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1793 64-bit templates. Drop Disp<N>.
1794 * i386-tlb.h: Re-generate.
1796 2018-03-08 Jan Beulich <jbeulich@suse.com>
1798 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1799 and 256-bit templates.
1800 * i386-tlb.h: Re-generate.
1802 2018-03-08 Jan Beulich <jbeulich@suse.com>
1804 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1805 * i386-tlb.h: Re-generate.
1807 2018-03-08 Jan Beulich <jbeulich@suse.com>
1809 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1811 * i386-tlb.h: Re-generate.
1813 2018-03-08 Jan Beulich <jbeulich@suse.com>
1815 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1816 * i386-tlb.h: Re-generate.
1818 2018-03-08 Jan Beulich <jbeulich@suse.com>
1820 * i386-gen.c (opcode_modifiers): Delete FloatD.
1821 * i386-opc.h (FloatD): Delete.
1822 (struct i386_opcode_modifier): Delete floatd.
1823 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1825 * i386-tlb.h: Re-generate.
1827 2018-03-08 Jan Beulich <jbeulich@suse.com>
1829 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1831 2018-03-08 Jan Beulich <jbeulich@suse.com>
1833 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1834 * i386-tlb.h: Re-generate.
1836 2018-03-08 Jan Beulich <jbeulich@suse.com>
1838 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1840 * i386-tlb.h: Re-generate.
1842 2018-03-07 Alan Modra <amodra@gmail.com>
1844 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1846 * disassemble.h (print_insn_rs6000): Delete.
1847 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1848 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1849 (print_insn_rs6000): Delete.
1851 2018-03-03 Alan Modra <amodra@gmail.com>
1853 * sysdep.h (opcodes_error_handler): Define.
1854 (_bfd_error_handler): Declare.
1855 * Makefile.am: Remove stray #.
1856 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1858 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1859 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1860 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1861 opcodes_error_handler to print errors. Standardize error messages.
1862 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1863 and include opintl.h.
1864 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1865 * i386-gen.c: Standardize error messages.
1866 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1867 * Makefile.in: Regenerate.
1868 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1869 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1870 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1871 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1872 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1873 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1874 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1875 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1876 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1877 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1878 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1879 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1880 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1882 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1884 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1885 vpsub[bwdq] instructions.
1886 * i386-tbl.h: Regenerated.
1888 2018-03-01 Alan Modra <amodra@gmail.com>
1890 * configure.ac (ALL_LINGUAS): Sort.
1891 * configure: Regenerate.
1893 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1895 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1896 macro by assignements.
1898 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1901 * i386-gen.c (opcode_modifiers): Add Optimize.
1902 * i386-opc.h (Optimize): New enum.
1903 (i386_opcode_modifier): Add optimize.
1904 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1905 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1906 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1907 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1908 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1910 * i386-tbl.h: Regenerated.
1912 2018-02-26 Alan Modra <amodra@gmail.com>
1914 * crx-dis.c (getregliststring): Allocate a large enough buffer
1915 to silence false positive gcc8 warning.
1917 2018-02-22 Shea Levy <shea@shealevy.com>
1919 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1921 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1923 * i386-opc.tbl: Add {rex},
1924 * i386-tbl.h: Regenerated.
1926 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1928 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1929 (mips16_opcodes): Replace `M' with `m' for "restore".
1931 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1933 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1935 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1937 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1938 variable to `function_index'.
1940 2018-02-13 Nick Clifton <nickc@redhat.com>
1943 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1944 about truncation of printing.
1946 2018-02-12 Henry Wong <henry@stuffedcow.net>
1948 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1950 2018-02-05 Nick Clifton <nickc@redhat.com>
1952 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1954 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1956 * i386-dis.c (enum): Add pconfig.
1957 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1958 (cpu_flags): Add CpuPCONFIG.
1959 * i386-opc.h (enum): Add CpuPCONFIG.
1960 (i386_cpu_flags): Add cpupconfig.
1961 * i386-opc.tbl: Add PCONFIG instruction.
1962 * i386-init.h: Regenerate.
1963 * i386-tbl.h: Likewise.
1965 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1967 * i386-dis.c (enum): Add PREFIX_0F09.
1968 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1969 (cpu_flags): Add CpuWBNOINVD.
1970 * i386-opc.h (enum): Add CpuWBNOINVD.
1971 (i386_cpu_flags): Add cpuwbnoinvd.
1972 * i386-opc.tbl: Add WBNOINVD instruction.
1973 * i386-init.h: Regenerate.
1974 * i386-tbl.h: Likewise.
1976 2018-01-17 Jim Wilson <jimw@sifive.com>
1978 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1980 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1982 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1983 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1984 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1985 (cpu_flags): Add CpuIBT, CpuSHSTK.
1986 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1987 (i386_cpu_flags): Add cpuibt, cpushstk.
1988 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1989 * i386-init.h: Regenerate.
1990 * i386-tbl.h: Likewise.
1992 2018-01-16 Nick Clifton <nickc@redhat.com>
1994 * po/pt_BR.po: Updated Brazilian Portugese translation.
1995 * po/de.po: Updated German translation.
1997 2018-01-15 Jim Wilson <jimw@sifive.com>
1999 * riscv-opc.c (match_c_nop): New.
2000 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2002 2018-01-15 Nick Clifton <nickc@redhat.com>
2004 * po/uk.po: Updated Ukranian translation.
2006 2018-01-13 Nick Clifton <nickc@redhat.com>
2008 * po/opcodes.pot: Regenerated.
2010 2018-01-13 Nick Clifton <nickc@redhat.com>
2012 * configure: Regenerate.
2014 2018-01-13 Nick Clifton <nickc@redhat.com>
2016 2.30 branch created.
2018 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2020 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2021 * i386-tbl.h: Regenerate.
2023 2018-01-10 Jan Beulich <jbeulich@suse.com>
2025 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2026 * i386-tbl.h: Re-generate.
2028 2018-01-10 Jan Beulich <jbeulich@suse.com>
2030 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2031 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2032 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2033 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2034 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2035 Disp8MemShift of AVX512VL forms.
2036 * i386-tbl.h: Re-generate.
2038 2018-01-09 Jim Wilson <jimw@sifive.com>
2040 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2041 then the hi_addr value is zero.
2043 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2045 * arm-dis.c (arm_opcodes): Add csdb.
2046 (thumb32_opcodes): Add csdb.
2048 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2050 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2051 * aarch64-asm-2.c: Regenerate.
2052 * aarch64-dis-2.c: Regenerate.
2053 * aarch64-opc-2.c: Regenerate.
2055 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2058 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2059 Remove AVX512 vmovd with 64-bit operands.
2060 * i386-tbl.h: Regenerated.
2062 2018-01-05 Jim Wilson <jimw@sifive.com>
2064 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2067 2018-01-03 Alan Modra <amodra@gmail.com>
2069 Update year range in copyright notice of all files.
2071 2018-01-02 Jan Beulich <jbeulich@suse.com>
2073 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2074 and OPERAND_TYPE_REGZMM entries.
2076 For older changes see ChangeLog-2017
2078 Copyright (C) 2018 Free Software Foundation, Inc.
2080 Copying and distribution of this file, with or without modification,
2081 are permitted in any medium without royalty provided the copyright
2082 notice and this notice are preserved.
2088 version-control: never