opcodes/ChangeLog

   1 2014-10-31  Andrew Pinski  <apinski@cavium.com>
   2             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
   3
   4         * mips-dis.c (mips_arch_choices): Add octeon3.
   5         * mips-opc.c (IOCT): Include INSN_OCTEON3.
   6         (IOCT2): Likewise.
   7         (IOCT3): New define.
   8         (IVIRT): New define.
   9         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
  10         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
  11         IVIRT instructions.
  12         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
  13         operand for IOCT3.
  14
  15 2014-10-29  Nick Clifton  <nickc@redhat.com>
  16
  17         * po/de.po: Updated German translation.
  18
  19 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
  20
  21         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
  22         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
  23         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
  24         size and format initializers.  Merge 'b' arguments into 'j'.
  25         (NIOS2_NUM_OPCODES): Adjust definition.
  26         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
  27         (nios2_opcodes): Adjust.
  28         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
  29         * nios2-dis.c (INSNLEN): Update comment.
  30         (nios2_hash_init, nios2_hash): Delete.
  31         (OPCODE_HASH_SIZE): New.
  32         (nios2_r1_extract_opcode): New.
  33         (nios2_disassembler_state): New.
  34         (nios2_r1_disassembler_state): New.
  35         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
  36         (nios2_find_opcode_hash): Use state object.
  37         (bad_opcode): New.
  38         (nios2_print_insn_arg): Add op parameter.  Use it to access
  39         format.  Remove 'b' case.
  40         (nios2_disassemble): Remove special case for nop.  Remove
  41         hard-coded instruction size.
  42
  43 2014-10-21  Jan Beulich  <jbeulich@suse.com>
  44
  45         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
  46
  47 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
  48
  49         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
  50         entries.
  51         Annotate several instructions with the HWCAP2_VIS3B hwcap.
  52
  53 2014-10-15  Tristan Gingold  <gingold@adacore.com>
  54
  55         * configure: Regenerate.
  56
  57 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
  58
  59         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
  60         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
  61         Annotate table with HWCAP2 bits.
  62         Add instructions xmontmul, xmontsqr, xmpmul.
  63         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
  64         r,i,%mwait' and `rd %mwait,r' instructions.
  65         Add rd/wr instructions for accessing the %mcdper ancillary state
  66         register.
  67         (sparc-opcodes): Add sparc5/vis4.0 instructions:
  68         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
  69         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
  70         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
  71         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
  72         fpsubus16, and faligndatai.
  73         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
  74         ancillary state register to the table.
  75         (print_insn_sparc): Handle the %mcdper ancillary state register.
  76         (print_insn_sparc): Handle new operand type '}'.
  77
  78 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
  79
  80         * i386-dis.c (MOD_0F20): Removed.
  81         (MOD_0F21): Likewise.
  82         (MOD_0F22): Likewise.
  83         (MOD_0F23): Likewise.
  84         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
  85         MOD_0F23 with "movZ".
  86         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
  87         (OP_R): Check mod/rm byte and call OP_E_register.
  88
  89 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
  90
  91         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
  92         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
  93         keyword_aridxi): Add audio ISA extension.
  94         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
  95         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
  96         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
  97         for nds32-dis.c using.
  98         (build_opcode_syntax): Remove dead code.
  99         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 100         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 101         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 102         operand parser.
 103         * nds32-asm.h: Declare.
 104         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 105         decoding by switch.
 106
 107 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 108             Matthew Fortune  <matthew.fortune@imgtec.com>
 109
 110         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 111         mips64r6.
 112         (parse_mips_dis_option): Allow MSA and virtualization support for
 113         mips64r6.
 114         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 115         (mips_seen_register): New function.
 116         (print_insn_arg): Refactored code to use mips_seen_register
 117         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 118         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 119         the register rather than aborting.
 120         (print_insn_args): Add length argument.  Add code to correctly
 121         calculate the instruction address for pc relative instructions.
 122         (validate_insn_args): New static function.
 123         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 124         validate_insn_args.
 125         (print_insn_micromips): Use validate_insn_args.
 126         all the arguments are valid.
 127         * mips-formats.h (PREV_CHECK): New define.
 128         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 129         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 130         (RD_pc): New define.
 131         (FS): New define.
 132         (I37): New define.
 133         (I69): New define.
 134         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 135         MIPS R6 instructions from MIPS R2 instructions.
 136
 137 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 140         (putop): Handle "%LP".
 141
 142 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 143
 144         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 145         * aarch64-dis-2.c: Update auto-generated file.
 146
 147 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 148
 149         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 150         (aarch64_feature_lse): New feature added.
 151         (LSE): New Added.
 152         (aarch64_opcode_table): New LSE instructions added.  Improve
 153         descriptions for ldarb/ldarh/ldar.
 154         (aarch64_opcode_table): Describe PAIRREG.
 155         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 156         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 157         (aarch64_print_operand): Recognize PAIRREG.
 158         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 159         instructions.
 160         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 161         (do_special_decoding): Recognize F_LSE_SZ.
 162         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 163
 164 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 165
 166         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 167         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 168         "sdbbp", "syscall" and "wait".
 169
 170 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 171             Maciej W. Rozycki  <macro@codesourcery.com>
 172
 173         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 174         returned if the U bit is set.
 175
 176 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 177
 178         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 179         48-bit "li" encoding.
 180
 181 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 182
 183         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 184         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 185         static functions, code was moved from...
 186         (print_insn_s390): ...here.
 187         (s390_extract_operand): Adjust comment.  Change type of first
 188         parameter from 'unsigned char *' to 'const bfd_byte *'.
 189         (union operand_value): New.
 190         (s390_extract_operand): Change return type to union operand_value.
 191         Also avoid integer overflow in sign-extension.
 192         (s390_print_insn_with_opcode): Adjust to changed return value from
 193         s390_extract_operand().  Change "%i" printf format to "%u" for
 194         unsigned values.
 195         (init_disasm): Simplify initialization of opc_index[].  This also
 196         fixes an access after the last element of s390_opcodes[].
 197         (print_insn_s390): Simplify the opcode search loop.
 198         Check architecture mask against all searched opcodes, not just the
 199         first matching one.
 200         (s390_print_insn_with_opcode): Drop function pointer dereferences
 201         without effect.
 202         (print_insn_s390): Likewise.
 203         (s390_insn_length): Simplify formula for return value.
 204         (s390_print_insn_with_opcode): Avoid special handling for the
 205         separator before the first operand.  Use new local variable
 206         'flags' in place of 'operand->flags'.
 207
 208 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 209
 210         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 211         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 212         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 213         Change assignment of 1 to priv->comment to TRUE.
 214         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 215         assignment of 0/1 with priv comment and parallel and legal
 216         to FALSE/TRUE.
 217
 218 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 219
 220         * bfin-dis.c (OUT): Define.
 221         (decode_CC2stat_0): Declare new op_names array.
 222         Replace multiple if statements with a single one.
 223
 224 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 225
 226         * bfin-dis.c (struct private): Add iw0.
 227         (_print_insn_bfin): Assign iw0 to priv.iw0.
 228         (print_insn_bfin): Drop ifetch and use priv.iw0.
 229
 230 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 231
 232         * bfin-dis.c (comment, parallel): Move from global scope ...
 233         (struct private): ... to this new struct.
 234         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 235         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 236         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 237         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 238         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 239         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 240         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 241         print_insn_bfin): Declare private struct.  Use priv's comment and
 242         parallel members.
 243
 244 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 245
 246         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 247         (_print_insn_bfin): Add check for unaligned pc.
 248
 249 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 250
 251         * bfin-dis.c (ifetch): New function.
 252         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 253         -1 when it errors.
 254
 255 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 256
 257         * micromips-opc.c (COD): Rename throughout to...
 258         (CM): New define, update to use INSN_COPROC_MOVE.
 259         (LCD): Rename throughout to...
 260         (LC): New define, update to use INSN_LOAD_COPROC.
 261         * mips-opc.c: Likewise.
 262
 263 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 264
 265         * micromips-opc.c (COD, LCD) New macros.
 266         (cfc1, ctc1): Remove FP_S attribute.
 267         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 268         (dmtc1, mtc1, mthc1): Add COD attribute.
 269         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 270
 271 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 272             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 273             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 274             Sergey Lega  <sergey.s.lega@intel.com>
 275             Anna Tikhonova  <anna.tikhonova@intel.com>
 276             Ilya Tocar  <ilya.tocar@intel.com>
 277             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 278             Ilya Verbin  <ilya.verbin@intel.com>
 279             Kirill Yukhin  <kirill.yukhin@intel.com>
 280             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 281
 282         * i386-dis-evex.h: Updated.
 283         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 284         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 285         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 286         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 287         PREFIX_EVEX_0F3A67.
 288         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 289         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 290         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 291         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 292         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 293         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 294         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 295         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 296         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 297         (prefix_table): Add entries for new instructions.
 298         (vex_len_table): Ditto.
 299         (vex_w_table): Ditto.
 300         (OP_E_memory): Update xmmq_mode handling.
 301         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 302         (cpu_flags): Add CpuAVX512DQ.
 303         * i386-init.h: Regenerared.
 304         * i386-opc.h (CpuAVX512DQ): New.
 305         (i386_cpu_flags): Add cpuavx512dq.
 306         * i386-opc.tbl: Add AVX512DQ instructions.
 307         * i386-tbl.h: Regenerate.
 308
 309 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 310             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 311             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 312             Sergey Lega  <sergey.s.lega@intel.com>
 313             Anna Tikhonova  <anna.tikhonova@intel.com>
 314             Ilya Tocar  <ilya.tocar@intel.com>
 315             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 316             Ilya Verbin  <ilya.verbin@intel.com>
 317             Kirill Yukhin  <kirill.yukhin@intel.com>
 318             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 319
 320         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 321         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 322         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 323         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 324         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 325         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 326         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 327         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 328         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 329         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 330         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 331         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 332         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 333         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 334         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 335         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 336         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 337         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 338         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 339         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 340         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 341         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 342         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 343         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 344         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 345         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 346         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 347         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 348         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 349         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 350         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 351         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 352         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 353         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 354         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 355         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 356         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 357         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 358         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 359         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 360         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 361         (prefix_table): Add entries for new instructions.
 362         (vex_table) : Ditto.
 363         (vex_len_table): Ditto.
 364         (vex_w_table): Ditto.
 365         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 366         mask_bd_mode handling.
 367         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 368         handling.
 369         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 370         handling.
 371         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 372         (OP_EX): Add dqw_swap_mode handling.
 373         (OP_VEX): Add mask_bd_mode handling.
 374         (OP_Mask): Add mask_bd_mode handling.
 375         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 376         (cpu_flags): Add CpuAVX512BW.
 377         * i386-init.h: Regenerated.
 378         * i386-opc.h (CpuAVX512BW): New.
 379         (i386_cpu_flags): Add cpuavx512bw.
 380         * i386-opc.tbl: Add AVX512BW instructions.
 381         * i386-tbl.h: Regenerate.
 382
 383 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 384             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 385             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 386             Sergey Lega  <sergey.s.lega@intel.com>
 387             Anna Tikhonova  <anna.tikhonova@intel.com>
 388             Ilya Tocar  <ilya.tocar@intel.com>
 389             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 390             Ilya Verbin  <ilya.verbin@intel.com>
 391             Kirill Yukhin  <kirill.yukhin@intel.com>
 392             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 393
 394         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 395         * i386-tbl.h: Regenerate.
 396
 397 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 398             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 399             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 400             Sergey Lega  <sergey.s.lega@intel.com>
 401             Anna Tikhonova  <anna.tikhonova@intel.com>
 402             Ilya Tocar  <ilya.tocar@intel.com>
 403             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 404             Ilya Verbin  <ilya.verbin@intel.com>
 405             Kirill Yukhin  <kirill.yukhin@intel.com>
 406             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 407
 408         * i386-dis.c (intel_operand_size): Support 128/256 length in
 409         vex_vsib_q_w_dq_mode.
 410         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 411         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 412         (cpu_flags): Add CpuAVX512VL.
 413         * i386-init.h: Regenerated.
 414         * i386-opc.h (CpuAVX512VL): New.
 415         (i386_cpu_flags): Add cpuavx512vl.
 416         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 417         * i386-opc.tbl: Add AVX512VL instructions.
 418         * i386-tbl.h: Regenerate.
 419
 420 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 421
 422         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 423         * or1k-opinst.c: Regenerate.
 424
 425 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 426
 427         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 428         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 429
 430 2014-07-04  Alan Modra  <amodra@gmail.com>
 431
 432         * configure.ac: Rename from configure.in.
 433         * Makefile.in: Regenerate.
 434         * config.in: Regenerate.
 435
 436 2014-07-04  Alan Modra  <amodra@gmail.com>
 437
 438         * configure.in: Include bfd/version.m4.
 439         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 440         (BFD_VERSION): Delete.
 441         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 442         * configure: Regenerate.
 443         * Makefile.in: Regenerate.
 444
 445 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 446             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 447             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 448             Soundararajan  <Sounderarajan.D@atmel.com>
 449
 450         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 451         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 452         machine is not avrtiny.
 453
 454 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 455
 456         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 457         constants.
 458
 459 2014-06-12  Alan Modra  <amodra@gmail.com>
 460
 461         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 462         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 463
 464 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 465
 466         * i386-dis.c (fwait_prefix): New.
 467         (ckprefix): Set fwait_prefix.
 468         (print_insn): Properly print prefixes before fwait.
 469
 470 2014-06-07  Alan Modra  <amodra@gmail.com>
 471
 472         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 473
 474 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 475
 476         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 477         bfd's development.sh.
 478         * Makefile.in, configure: Regenerate.
 479
 480 2014-06-03  Nick Clifton  <nickc@redhat.com>
 481
 482         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 483         decide when extended addressing is being used.
 484
 485 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 486
 487         * sparc-opc.c (cas): Disable for LEON.
 488         (casl): Likewise.
 489
 490 2014-05-20  Alan Modra  <amodra@gmail.com>
 491
 492         * m68k-dis.c: Don't include setjmp.h.
 493
 494 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 495
 496         * i386-dis.c (ADDR16_PREFIX): Removed.
 497         (ADDR32_PREFIX): Likewise.
 498         (DATA16_PREFIX): Likewise.
 499         (DATA32_PREFIX): Likewise.
 500         (prefix_name): Updated.
 501         (print_insn): Simplify data and address size prefixes processing.
 502
 503 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 504
 505         * or1k-desc.c: Regenerated.
 506         * or1k-desc.h: Likewise.
 507         * or1k-opc.c: Likewise.
 508         * or1k-opc.h: Likewise.
 509         * or1k-opinst.c: Likewise.
 510
 511 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 512
 513         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 514         (I34): New define.
 515         (I36): New define.
 516         (I66): New define.
 517         (I68): New define.
 518         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 519         mips64r5.
 520         (parse_mips_dis_option): Update MSA and virtualization support to
 521         allow mips64r3 and mips64r5.
 522
 523 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 524
 525         * mips-opc.c (G3): Remove I4.
 526
 527 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         PR binutils/16893
 530         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 531         (end_codep): Likewise.
 532         (mandatory_prefix): Likewise.
 533         (active_seg_prefix): Likewise.
 534         (ckprefix): Set active_seg_prefix to the active segment register
 535         prefix.
 536         (seg_prefix): Removed.
 537         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 538         for prefix index.  Ignore the index if it is invalid and the
 539         mandatory prefix isn't required.
 540         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 541         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 542         in used_prefixes here.  Don't print unused prefixes.  Check
 543         active_seg_prefix for the active segment register prefix.
 544         Restore the DFLAG bit in sizeflag if the data size prefix is
 545         unused.  Check the unused mandatory PREFIX_XXX prefixes
 546         (append_seg): Only print the segment register which gets used.
 547         (OP_E_memory): Check active_seg_prefix for the segment register
 548         prefix.
 549         (OP_OFF): Likewise.
 550         (OP_OFF64): Likewise.
 551         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 552
 553 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 554
 555         PR binutils/16886
 556         * config.in: Regenerated.
 557         * configure: Likewise.
 558         * configure.in: Check if sigsetjmp is available.
 559         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 560         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 561         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 562         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 563         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 564         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 565         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 566         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 567         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 568         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 569         (OPCODES_SIGSETJMP): Likewise.
 570         (OPCODES_SIGLONGJMP): Likewise.
 571         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 572         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 573         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 574         * xtensa-dis.c (dis_private): Replace jmp_buf with
 575         OPCODES_SIGJMP_BUF.
 576         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 577         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 578         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 579         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 580         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 581
 582 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 583
 584         PR binutils/16891
 585         * i386-dis.c (print_insn): Handle prefixes before fwait.
 586
 587 2014-04-26  Alan Modra  <amodra@gmail.com>
 588
 589         * po/POTFILES.in: Regenerate.
 590
 591 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 592
 593         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 594         to allow the MIPS XPA ASE.
 595         (parse_mips_dis_option): Process the -Mxpa option.
 596         * mips-opc.c (XPA): New define.
 597         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 598         locations of the ctc0 and cfc0 instructions.
 599
 600 2014-04-22  Christian Svensson  <blue@cmd.nu>
 601
 602         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 603         * configure.in: Likewise.
 604         * disassemble.c: Likewise.
 605         * or1k-asm.c: New file.
 606         * or1k-desc.c: New file.
 607         * or1k-desc.h: New file.
 608         * or1k-dis.c: New file.
 609         * or1k-ibld.c: New file.
 610         * or1k-opc.c: New file.
 611         * or1k-opc.h: New file.
 612         * or1k-opinst.c: New file.
 613         * Makefile.in: Regenerate.
 614         * configure: Regenerate.
 615         * openrisc-asm.c: Delete.
 616         * openrisc-desc.c: Delete.
 617         * openrisc-desc.h: Delete.
 618         * openrisc-dis.c: Delete.
 619         * openrisc-ibld.c: Delete.
 620         * openrisc-opc.c: Delete.
 621         * openrisc-opc.h: Delete.
 622         * or32-dis.c: Delete.
 623         * or32-opc.c: Delete.
 624
 625 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 626
 627         * i386-dis.c (rm_table): Add encls, enclu.
 628         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 629         (cpu_flags): Add CpuSE1.
 630         * i386-opc.h (enum): Add CpuSE1.
 631         (i386_cpu_flags): Add cpuse1.
 632         * i386-opc.tbl: Add encls, enclu.
 633         * i386-init.h: Regenerated.
 634         * i386-tbl.h: Likewise.
 635
 636 2014-04-02  Anthony Green  <green@moxielogic.com>
 637
 638         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 639         instructions, sex.b and sex.s.
 640
 641 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 642
 643         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 644         instructions.
 645
 646 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 647
 648         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 649         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 650         vscatterqps.
 651         * i386-tbl.h: Regenerate.
 652
 653 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 654
 655         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 656         %hstick_enable added.
 657
 658 2014-03-19  Nick Clifton  <nickc@redhat.com>
 659
 660         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 661         field of 3.
 662         (sbwl, ubwl, SCALE): Likewise.
 663         * rx-decode.c: Regenerate.
 664
 665 2014-03-12  Alan Modra  <amodra@gmail.com>
 666
 667         * Makefile.in: Regenerate.
 668
 669 2014-03-05  Alan Modra  <amodra@gmail.com>
 670
 671         Update copyright years.
 672
 673 2014-03-04  Heiher  <r@hev.cc>
 674
 675         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 676
 677 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 678
 679         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 680         so that they come after the Loongson extensions.
 681
 682 2014-03-03  Alan Modra  <amodra@gmail.com>
 683
 684         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 685
 686 2014-02-28  Alan Modra  <amodra@gmail.com>
 687
 688         * msp430-decode.c: Regenerate.
 689
 690 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 691
 692         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 693         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 694
 695 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 696
 697         * aarch64-opc.c (print_register_offset_address): Call
 698         get_int_reg_name to prepare the register name.
 699
 700 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 701
 702         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 703         * i386-tbl.h: Regenerate.
 704
 705 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 706
 707         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 708         (cpu_flags): Add CpuPREFETCHWT1.
 709         * i386-init.h: Regenerate.
 710         * i386-opc.h (CpuPREFETCHWT1): New.
 711         (i386_cpu_flags): Add cpuprefetchwt1.
 712         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 713         * i386-tbl.h: Regenerate.
 714
 715 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 716
 717         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 718         to CpuAVX512F.
 719         * i386-tbl.h: Regenerate.
 720
 721 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 724         (output_opcode_modifier): Likewise.
 725         (output_operand_type): Likewise.
 726         * i386-init.h: Regenerated.
 727         * i386-tbl.h: Likewise.
 728
 729 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 730
 731         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 732         MOD_0FC7_REG_5.
 733         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 734         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 735         (prefix_table): Add clflusopt.
 736         (mod_table): Add xrstors, xsavec, xsaves.
 737         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 738         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 739         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 740         * i386-init.h: Regenerate.
 741         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 742         xsaves64, xsavec, xsavec64.
 743         * i386-tbl.h: Regenerate.
 744
 745 2014-02-10  Alan Modra  <amodra@gmail.com>
 746
 747         * po/POTFILES.in: Regenerate.
 748         * po/opcodes.pot: Regenerate.
 749
 750 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 751             Jan Beulich  <jbeulich@suse.com>
 752
 753         PR binutils/16490
 754         * i386-dis.c (OP_E_memory): Fix shift computation for
 755         vex_vsib_q_w_dq_mode.
 756
 757 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 758             Roland McGrath  <mcgrathr@google.com>
 759
 760         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 761         last_rex_prefix is -1.
 762
 763 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 764
 765         * i386-gen.c (process_copyright): Update copyright year to 2014.
 766
 767 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 768
 769         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 770
 771 For older changes see ChangeLog-2013
 772 \f
 773 Copyright (C) 2014 Free Software Foundation, Inc.
 774
 775 Copying and distribution of this file, with or without modification,
 776 are permitted in any medium without royalty provided the copyright
 777 notice and this notice are preserved.
 778
 779 Local Variables:
 780 mode: change-log
 781 left-margin: 8
 782 fill-column: 74
 783 version-control: never
 784 End: