opcodes/ChangeLog

   1 2021-04-06  Alan Modra  <amodra@gmail.com>
   2
   3         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
   4         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
   5         symbol_at_address_func.
   6
   7 2021-04-05  Alan Modra  <amodra@gmail.com>
   8
   9         * configure.ac: Don't check for limits.h, string.h, strings.h or
  10         stdlib.h.
  11         (AC_ISC_POSIX): Don't invoke.
  12         * sysdep.h: Include stdlib.h and string.h unconditionally.
  13         * i386-opc.h: Include limits.h unconditionally.
  14         * wasm32-dis.c: Likewise.
  15         * cgen-opc.c: Don't include alloca-conf.h.
  16         * config.in: Regenerate.
  17         * configure: Regenerate.
  18
  19 2021-04-01  Martin Liska  <mliska@suse.cz>
  20
  21         * arm-dis.c (strneq): Remove strneq and use startswith.
  22         * cr16-dis.c (print_insn_cr16): Likewise.
  23         * score-dis.c (streq): Likewise.
  24         (strneq): Likewise.
  25         * score7-dis.c (strneq): Likewise.
  26
  27 2021-04-01  Alan Modra  <amodra@gmail.com>
  28
  29         PR 27675
  30         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
  31
  32 2021-03-31  Alan Modra  <amodra@gmail.com>
  33
  34         * sysdep.h (POISON_BFD_BOOLEAN): Define.
  35         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
  36         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
  37         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
  38         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
  39         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
  40         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
  41         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
  42         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
  43         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
  44         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
  45         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
  46         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
  47         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
  48         and TRUE with true throughout.
  49
  50 2021-03-31  Alan Modra  <amodra@gmail.com>
  51
  52         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
  53         * aarch64-dis.h: Likewise.
  54         * aarch64-opc.c: Likewise.
  55         * avr-dis.c: Likewise.
  56         * csky-dis.c: Likewise.
  57         * nds32-asm.c: Likewise.
  58         * nds32-dis.c: Likewise.
  59         * nfp-dis.c: Likewise.
  60         * riscv-dis.c: Likewise.
  61         * s12z-dis.c: Likewise.
  62         * wasm32-dis.c: Likewise.
  63
  64 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
  67         (i386_seg_prefixes): New.
  68         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
  69         (i386_seg_prefixes): Declare.
  70
  71 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
  74
  75 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  76
  77         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
  78         * i386-reg.tbl (st): Move down.
  79         (st(0)): Delete. Extend comment.
  80         * i386-tbl.h: Re-generate.
  81
  82 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
  85         (cmpsd): Move next to cmps.
  86         (movsd): Move next to movs.
  87         (cmpxchg16b): Move to separate section.
  88         (fisttp, fisttpll): Likewise.
  89         (monitor, mwait): Likewise.
  90         * i386-tbl.h: Re-generate.
  91
  92 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-opc.tbl (psadbw): Add <sse2:comm>.
  95         (vpsadbw): Add C.
  96         * i386-tbl.h: Re-generate.
  97
  98 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  99
 100         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 101         pclmul, gfni): New templates. Use them wherever possible. Move
 102         SSE4.1 pextrw into respective section.
 103         * i386-tbl.h: Re-generate.
 104
 105 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 108         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 109         "length".
 110         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 111         Convert all of their uses to representation in opcode.
 112
 113 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 114
 115         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 116         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 117         value of None. Shrink operands to 3 bits.
 118
 119 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-gen.c (process_i386_opcode_modifier): New parameter
 122         "space".
 123         (output_i386_opcode): New local variable "space". Adjust
 124         process_i386_opcode_modifier() invocation.
 125         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 126         invocation.
 127         * i386-tbl.h: Re-generate.
 128
 129 2021-03-29  Alan Modra  <amodra@gmail.com>
 130
 131         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 132         (fp_qualifier_p, get_data_pattern): Likewise.
 133         (aarch64_get_operand_modifier_from_value): Likewise.
 134         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 135         (operand_variant_qualifier_p): Likewise.
 136         (qualifier_value_in_range_constraint_p): Likewise.
 137         (aarch64_get_qualifier_esize): Likewise.
 138         (aarch64_get_qualifier_nelem): Likewise.
 139         (aarch64_get_qualifier_standard_value): Likewise.
 140         (get_lower_bound, get_upper_bound): Likewise.
 141         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 142         (aarch64_print_operand): Likewise.
 143         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 144         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 145         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 146         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 147         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 148         (print_insn_tic6x): Likewise.
 149
 150 2021-03-29  Alan Modra  <amodra@gmail.com>
 151
 152         * arc-dis.c (extract_operand_value): Correct NULL cast.
 153         * frv-opc.h: Regenerate.
 154
 155 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 158         MMX form.
 159         * i386-tbl.h: Re-generate.
 160
 161 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 162
 163         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 164         immediate in br.n instruction.
 165
 166 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-dis.c (XMGatherD, VexGatherD): New.
 169         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 170         (print_insn): Check masking for S/G insns.
 171         (OP_E_memory): New local variable check_gather. Extend mandatory
 172         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 173         Extend check for disallowed 16-bit addressing.
 174         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 175         if()s to switch(). Check register conflicts for (VEX-encoded)
 176         gathers. Drop no longer reachable cases.
 177         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 178         vgatherdp*.
 179
 180 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 183         zeroing-masking without masking.
 184
 185 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 188         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 189         single-operand forms as deprecated.
 190         * i386-tbl.h: Re-generate.
 191
 192 2021-03-25  Alan Modra  <amodra@gmail.com>
 193
 194         PR 27647
 195         * ppc-opc.c (XLOCB_MASK): Delete.
 196         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 197         XLBH_MASK.
 198         (powerpc_opcodes): Accept a BH field on all extended forms of
 199         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 200
 201 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-gen.c (output_i386_opcode): Drop processing of
 204         opcode_length. Calculate length from base_opcode. Adjust prefix
 205         encoding determination.
 206         (process_i386_opcodes): Drop output of fake opcode_length.
 207         * i386-opc.h (struct insn_template): Drop opcode_length field.
 208         * i386-opc.tbl: Drop opcode length field from all templates.
 209         * i386-tbl.h: Re-generate.
 210
 211 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 214         parameter "prefix". Drop local variable "regular_encoding".
 215         Record prefix setting / check for consistency.
 216         (output_i386_opcode): Parse opcode_length and base_opcode
 217         earlier. Derive prefix encoding. Drop no longer applicable
 218         consistency checking. Adjust process_i386_opcode_modifier()
 219         invocation.
 220         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 221         invocation.
 222         * i386-tbl.h: Re-generate.
 223
 224 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 225
 226         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 227         check.
 228         * i386-opc.h (Prefix_*): Move #define-s.
 229         * i386-opc.tbl: Move pseudo prefix enumerator values to
 230         extension opcode field. Introduce pseudopfx template.
 231         * i386-tbl.h: Re-generate.
 232
 233 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 236         comment.
 237         * i386-tbl.h: Re-generate.
 238
 239 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 240
 241         * i386-opc.h (struct insn_template): Move cpu_flags field past
 242         opcode_modifier one.
 243         * i386-tbl.h: Re-generate.
 244
 245 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 248         * i386-opc.h (OpcodeSpace): New enumerator.
 249         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 250         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 251         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 252         (struct i386_opcode_modifier): New field opcodespace. Shrink
 253         opcodeprefix field.
 254         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 255         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 256         OpcodePrefix uses.
 257         * i386-tbl.h: Re-generate.
 258
 259 2021-03-22  Martin Liska  <mliska@suse.cz>
 260
 261         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 262         * arc-dis.c (parse_option): Likewise.
 263         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 264         * cris-dis.c (print_with_operands): Likewise.
 265         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 266         * i386-dis.c (print_insn): Likewise.
 267         * ia64-gen.c (fetch_insn_class): Likewise.
 268         (parse_resource_users): Likewise.
 269         (in_iclass): Likewise.
 270         (lookup_specifier): Likewise.
 271         (insert_opcode_dependencies): Likewise.
 272         * mips-dis.c (parse_mips_ase_option): Likewise.
 273         (parse_mips_dis_option): Likewise.
 274         * s390-dis.c (disassemble_init_s390): Likewise.
 275         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 276
 277 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 278
 279         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 280
 281 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 282
 283         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 284         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 285
 286 2021-03-12  Alan Modra  <amodra@gmail.com>
 287
 288         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 289
 290 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-dis.c (OP_XMM): Re-order checks.
 293
 294 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-dis.c (putop): Drop need_vex check when also checking
 297         vex.evex.
 298         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 299         checking vex.b.
 300
 301 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 304         checks. Move case label past broadcast check.
 305
 306 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 307
 308         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 309         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 310         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 311         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 312         EVEX_W_0F38C7_M_0_L_2): Delete.
 313         (REG_EVEX_0F38C7_M_0_L_2): New.
 314         (intel_operand_size): Handle VEX and EVEX the same for
 315         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 316         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 317         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 318         vex_vsib_q_w_d_mode uses.
 319         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 320         0F38A1, and 0F38A3 entries.
 321         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 322         entry.
 323         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 324         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 325         0F38A3 entries.
 326
 327 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 328
 329         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 330         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 331         MOD_VEX_0FXOP_09_12): Rename to ...
 332         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 333         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 334         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 335         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 336         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 337         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 338         (reg_table): Adjust comments.
 339         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 340         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 341         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 342         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 343         (vex_len_table): Adjust opcode 0A_12 entry.
 344         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 345         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 346         (rm_table): Move hreset entry.
 347
 348 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 349
 350         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 351         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 352         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 353         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 354         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 355         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 356         (get_valid_dis386): Also handle 512-bit vector length when
 357         vectoring into vex_len_table[].
 358         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 359         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 360         entries.
 361         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 362         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 363         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 364         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 365         entries.
 366
 367 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 368
 369         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 370         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 371         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 372         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 373         entries.
 374         * i386-dis-evex-len.h (evex_len_table): Likewise.
 375         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 376
 377 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 378
 379         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 380         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 381         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 382         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 383         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 384         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 385         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 386         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 387         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 388         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 389         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 390         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 391         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 392         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 393         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 394         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 395         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 396         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 397         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 398         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 399         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 400         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 401         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 402         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 403         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 404         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 405         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 406         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 407         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 408         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 409         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 410         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 411         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 412         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 413         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 414         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 415         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 416         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 417         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 418         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 419         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 420         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 421         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 422         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 423         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 424         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 425         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 426         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 427         EVEX_W_0F3A43_L_n): New.
 428         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 429         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 430         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 431         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 432         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 433         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 434         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 435         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 436         0F385B, 0F38C6, and 0F38C7 entries.
 437         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 438         0F38C6 and 0F38C7.
 439         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 440         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 441         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 442         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 443
 444 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 445
 446         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 447         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 448         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 449         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 450         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 451         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 452         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 453         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 454         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 455         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 456         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 457         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 458         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 459         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 460         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 461         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 462         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 463         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 464         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 465         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 466         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 467         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 468         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 469         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 470         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 471         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 472         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 473         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 474         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 475         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 476         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 477         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 478         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 479         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 480         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 481         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 482         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 483         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 484         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 485         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 486         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 487         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 488         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 489         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 490         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 491         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 492         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 493         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 494         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 495         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 496         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 497         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 498         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 499         VEX_W_0F99_P_2_LEN_0): Delete.
 500         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 501         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 502         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 503         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 504         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 505         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 506         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 507         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 508         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 509         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 510         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 511         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 512         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 513         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 514         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 515         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 516         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 517         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 518         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 519         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 520         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 521         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 522         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 523         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 524         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 525         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 526         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 527         (prefix_table): No longer link to vex_len_table[] for opcodes
 528         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 529         0F92, 0F93, 0F98, and 0F99.
 530         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 531         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 532         0F98, and 0F99.
 533         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 534         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 535         0F98, and 0F99.
 536         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 537         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 538         0F98, and 0F99.
 539         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 540         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 541         0F98, and 0F99.
 542
 543 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 544
 545         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 546         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 547         REG_VEX_0F73_M_0 respectively.
 548         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 549         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 550         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 551         MOD_VEX_0F73_REG_7): Delete.
 552         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 553         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 554         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 555         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 556         PREFIX_VEX_0F3AF0_L_0 respectively.
 557         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 558         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 559         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 560         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 561         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 562         VEX_LEN_0F38F7): New.
 563         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 564         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 565         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 566         0F38F3.
 567         (prefix_table): No longer link to vex_len_table[] for opcodes
 568         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 569         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 570         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 571         0F38F6, 0F38F7, and 0F3AF0.
 572         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 573         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 574         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 575         0F73.
 576
 577 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 578
 579         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 580         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 581         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 582         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 583         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 584         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 585         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 586         73.
 587         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 588         0F72, and 0F73.
 589         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 590         0F73.
 591
 592 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 593
 594         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 595         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 596         (reg_table): Don't link to mod_table[] where not needed. Add
 597         PREFIX_IGNORED to nop entries.
 598         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 599         (mod_table): Add nop entries next to prefetch ones. Drop
 600         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 601         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 602         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 603         PREFIX_OPCODE from endbr* entries.
 604         (get_valid_dis386): Also consider entry's name when zapping
 605         vindex.
 606         (print_insn): Handle PREFIX_IGNORED.
 607
 608 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 609
 610         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 611         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 612         element.
 613         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 614         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 615         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 616         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 617         (struct i386_opcode_modifier): Delete notrackprefixok,
 618         islockable, hleprefixok, and repprefixok fields. Add prefixok
 619         field.
 620         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 621         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 622         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 623         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 624         Replace HLEPrefixOk.
 625         * opcodes/i386-tbl.h: Re-generate.
 626
 627 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 628
 629         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 630         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 631         64-bit form.
 632         * opcodes/i386-tbl.h: Re-generate.
 633
 634 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 635
 636         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 637         for {} instead of {0}. Don't look for '0'.
 638         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 639         size specifiers.
 640
 641 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 642
 643         PR 27158
 644         * riscv-dis.c (print_insn_args): Updated encoding macros.
 645         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 646         (match_c_addi16sp): Updated encoding macros.
 647         (match_c_lui): Likewise.
 648         (match_c_lui_with_hint): Likewise.
 649         (match_c_addi4spn): Likewise.
 650         (match_c_slli): Likewise.
 651         (match_slli_as_c_slli): Likewise.
 652         (match_c_slli64): Likewise.
 653         (match_srxi_as_c_srxi): Likewise.
 654         (riscv_insn_types): Added .insn css/cl/cs.
 655
 656 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 657
 658         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 659         (default_priv_spec): Updated type to riscv_spec_class.
 660         (parse_riscv_dis_option): Updated.
 661         * riscv-opc.c: Moved stuff and make the file tidy.
 662
 663 2021-02-17  Alan Modra  <amodra@gmail.com>
 664
 665         * wasm32-dis.c: Include limits.h.
 666         (CHAR_BIT): Provide backup define.
 667         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 668         Correct signed overflow checking.
 669
 670 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 673         * i386-tbl.h: Re-generate.
 674
 675 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 676
 677         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 678         Oword.
 679         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 680
 681 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 682
 683         * s390-mkopc.c (main): Accept arch14 as cpu string.
 684         * s390-opc.txt: Add new arch14 instructions.
 685
 686 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 687
 688         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 689         favour of LIBINTL.
 690         * configure: Regenerated.
 691
 692 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 693
 694         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 695         * tic54x-opc.c (regs): Rename to ...
 696         (tic54x_regs): ... this.
 697         (mmregs): Rename to ...
 698         (tic54x_mmregs): ... this.
 699         (condition_codes): Rename to ...
 700         (tic54x_condition_codes): ... this.
 701         (cc2_codes): Rename to ...
 702         (tic54x_cc2_codes): ... this.
 703         (cc3_codes): Rename to ...
 704         (tic54x_cc3_codes): ... this.
 705         (status_bits): Rename to ...
 706         (tic54x_status_bits): ... this.
 707         (misc_symbols): Rename to ...
 708         (tic54x_misc_symbols): ... this.
 709
 710 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 711
 712         * riscv-opc.c (MASK_RVB_IMM): Removed.
 713         (riscv_opcodes): Removed zb* instructions.
 714         (riscv_ext_version_table): Removed versions for zb*.
 715
 716 2021-01-26  Alan Modra  <amodra@gmail.com>
 717
 718         * i386-gen.c (parse_template): Ensure entire template_instance
 719         is initialised.
 720
 721 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 722
 723         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 724         (riscv_fpr_names_abi): Likewise.
 725         (riscv_opcodes): Likewise.
 726         (riscv_insn_types): Likewise.
 727
 728 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 729
 730         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 731
 732 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 733
 734         * riscv-dis.c: Comments tidy and improvement.
 735         * riscv-opc.c: Likewise.
 736
 737 2021-01-13  Alan Modra  <amodra@gmail.com>
 738
 739         * Makefile.in: Regenerate.
 740
 741 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 742
 743         PR binutils/26792
 744         * configure.ac: Use GNU_MAKE_JOBSERVER.
 745         * aclocal.m4: Regenerated.
 746         * configure: Likewise.
 747
 748 2021-01-12  Nick Clifton  <nickc@redhat.com>
 749
 750         * po/sr.po: Updated Serbian translation.
 751
 752 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 753
 754         PR ld/27173
 755         * configure: Regenerated.
 756
 757 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 758
 759         * aarch64-asm-2.c: Regenerate.
 760         * aarch64-dis-2.c: Likewise.
 761         * aarch64-opc-2.c: Likewise.
 762         * aarch64-opc.c (aarch64_print_operand):
 763         Delete handling of AARCH64_OPND_CSRE_CSR.
 764         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 765         (CSRE): Likewise.
 766         (_CSRE_INSN): Likewise.
 767         (aarch64_opcode_table): Delete csr.
 768
 769 2021-01-11  Nick Clifton  <nickc@redhat.com>
 770
 771         * po/de.po: Updated German translation.
 772         * po/fr.po: Updated French translation.
 773         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 774         * po/sv.po: Updated Swedish translation.
 775         * po/uk.po: Updated Ukranian translation.
 776
 777 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 778
 779         * configure: Regenerated.
 780
 781 2021-01-09  Nick Clifton  <nickc@redhat.com>
 782
 783         * configure: Regenerate.
 784         * po/opcodes.pot: Regenerate.
 785
 786 2021-01-09  Nick Clifton  <nickc@redhat.com>
 787
 788         * 2.36 release branch crated.
 789
 790 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 791
 792         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 793         (DW, (XRC_MASK): Define.
 794         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 795
 796 2021-01-09  Alan Modra  <amodra@gmail.com>
 797
 798         * configure: Regenerate.
 799
 800 2021-01-08  Nick Clifton  <nickc@redhat.com>
 801
 802         * po/sv.po: Updated Swedish translation.
 803
 804 2021-01-08  Nick Clifton  <nickc@redhat.com>
 805
 806         PR 27129
 807         * aarch64-dis.c (determine_disassembling_preference): Move call to
 808         aarch64_match_operands_constraint outside of the assertion.
 809         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 810         Replace with a return of FALSE.
 811
 812         PR 27139
 813         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 814         core system register.
 815
 816 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 817
 818         * configure: Regenerate.
 819
 820 2021-01-07  Nick Clifton  <nickc@redhat.com>
 821
 822         * po/fr.po: Updated French translation.
 823
 824 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 825
 826         * m68k-opc.c (chkl): Change minimum architecture requirement to
 827         m68020.
 828
 829 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 830
 831         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 832
 833 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 834             Jim Wilson  <jimw@sifive.com>
 835             Andrew Waterman  <andrew@sifive.com>
 836             Maxim Blinov  <maxim.blinov@embecosm.com>
 837             Kito Cheng  <kito.cheng@sifive.com>
 838             Nelson Chu  <nelson.chu@sifive.com>
 839
 840         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 841         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 842
 843 2021-01-01  Alan Modra  <amodra@gmail.com>
 844
 845         Update year range in copyright notice of all files.
 846
 847 For older changes see ChangeLog-2020
 848 \f
 849 Copyright (C) 2021 Free Software Foundation, Inc.
 850
 851 Copying and distribution of this file, with or without modification,
 852 are permitted in any medium without royalty provided the copyright
 853 notice and this notice are preserved.
 854
 855 Local Variables:
 856 mode: change-log
 857 left-margin: 8
 858 fill-column: 74
 859 version-control: never
 860 End: