opcodes/ChangeLog

   1 2021-03-22  Martin Liska  <mliska@suse.cz>
   2
   3         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
   4         * arc-dis.c (parse_option): Likewise.
   5         * arm-dis.c (parse_arm_disassembler_options): Likewise.
   6         * cris-dis.c (print_with_operands): Likewise.
   7         * h8300-dis.c (bfd_h8_disassemble): Likewise.
   8         * i386-dis.c (print_insn): Likewise.
   9         * ia64-gen.c (fetch_insn_class): Likewise.
  10         (parse_resource_users): Likewise.
  11         (in_iclass): Likewise.
  12         (lookup_specifier): Likewise.
  13         (insert_opcode_dependencies): Likewise.
  14         * mips-dis.c (parse_mips_ase_option): Likewise.
  15         (parse_mips_dis_option): Likewise.
  16         * s390-dis.c (disassemble_init_s390): Likewise.
  17         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
  18
  19 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
  20
  21         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
  22
  23 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  24
  25         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
  26         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
  27
  28 2021-03-12  Alan Modra  <amodra@gmail.com>
  29
  30         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
  31
  32 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-dis.c (OP_XMM): Re-order checks.
  35
  36 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-dis.c (putop): Drop need_vex check when also checking
  39         vex.evex.
  40         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
  41         checking vex.b.
  42
  43 2021-03-11  Jan Beulich  <jbeulich@suse.com>
  44
  45         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
  46         checks. Move case label past broadcast check.
  47
  48 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  49
  50         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
  51         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
  52         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
  53         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
  54         EVEX_W_0F38C7_M_0_L_2): Delete.
  55         (REG_EVEX_0F38C7_M_0_L_2): New.
  56         (intel_operand_size): Handle VEX and EVEX the same for
  57         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
  58         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
  59         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
  60         vex_vsib_q_w_d_mode uses.
  61         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
  62         0F38A1, and 0F38A3 entries.
  63         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
  64         entry.
  65         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
  66         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
  67         0F38A3 entries.
  68
  69 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  70
  71         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
  72         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
  73         MOD_VEX_0FXOP_09_12): Rename to ...
  74         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
  75         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
  76         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
  77         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
  78         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
  79         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
  80         (reg_table): Adjust comments.
  81         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
  82         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
  83         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
  84         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
  85         (vex_len_table): Adjust opcode 0A_12 entry.
  86         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
  87         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
  88         (rm_table): Move hreset entry.
  89
  90 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  91
  92         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
  93         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
  94         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
  95         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
  96         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
  97         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
  98         (get_valid_dis386): Also handle 512-bit vector length when
  99         vectoring into vex_len_table[].
 100         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 101         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 102         entries.
 103         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 104         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 105         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 106         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 107         entries.
 108
 109 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 110
 111         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 112         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 113         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 114         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 115         entries.
 116         * i386-dis-evex-len.h (evex_len_table): Likewise.
 117         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 118
 119 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 120
 121         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 122         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 123         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 124         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 125         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 126         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 127         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 128         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 129         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 130         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 131         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 132         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 133         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 134         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 135         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 136         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 137         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 138         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 139         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 140         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 141         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 142         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 143         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 144         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 145         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 146         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 147         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 148         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 149         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 150         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 151         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 152         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 153         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 154         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 155         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 156         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 157         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 158         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 159         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 160         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 161         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 162         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 163         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 164         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 165         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 166         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 167         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 168         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 169         EVEX_W_0F3A43_L_n): New.
 170         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 171         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 172         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 173         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 174         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 175         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 176         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 177         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 178         0F385B, 0F38C6, and 0F38C7 entries.
 179         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 180         0F38C6 and 0F38C7.
 181         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 182         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 183         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 184         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 185
 186 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 187
 188         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 189         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 190         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 191         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 192         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 193         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 194         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 195         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 196         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 197         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 198         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 199         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 200         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 201         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 202         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 203         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 204         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 205         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 206         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 207         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 208         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 209         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 210         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 211         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 212         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 213         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 214         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 215         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 216         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 217         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 218         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 219         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 220         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 221         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 222         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 223         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 224         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 225         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 226         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 227         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 228         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 229         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 230         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 231         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 232         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 233         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 234         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 235         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 236         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 237         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 238         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 239         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 240         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 241         VEX_W_0F99_P_2_LEN_0): Delete.
 242         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 243         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 244         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 245         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 246         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 247         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 248         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 249         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 250         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 251         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 252         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 253         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 254         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 255         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 256         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 257         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 258         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 259         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 260         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 261         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 262         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 263         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 264         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 265         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 266         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 267         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 268         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 269         (prefix_table): No longer link to vex_len_table[] for opcodes
 270         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 271         0F92, 0F93, 0F98, and 0F99.
 272         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 273         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 274         0F98, and 0F99.
 275         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 276         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 277         0F98, and 0F99.
 278         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 279         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 280         0F98, and 0F99.
 281         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 282         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 283         0F98, and 0F99.
 284
 285 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 286
 287         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 288         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 289         REG_VEX_0F73_M_0 respectively.
 290         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 291         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 292         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 293         MOD_VEX_0F73_REG_7): Delete.
 294         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 295         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 296         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 297         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 298         PREFIX_VEX_0F3AF0_L_0 respectively.
 299         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 300         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 301         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 302         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 303         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 304         VEX_LEN_0F38F7): New.
 305         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 306         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 307         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 308         0F38F3.
 309         (prefix_table): No longer link to vex_len_table[] for opcodes
 310         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 311         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 312         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 313         0F38F6, 0F38F7, and 0F3AF0.
 314         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 315         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 316         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 317         0F73.
 318
 319 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 320
 321         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 322         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 323         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 324         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 325         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 326         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 327         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 328         73.
 329         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 330         0F72, and 0F73.
 331         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 332         0F73.
 333
 334 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 335
 336         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 337         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 338         (reg_table): Don't link to mod_table[] where not needed. Add
 339         PREFIX_IGNORED to nop entries.
 340         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 341         (mod_table): Add nop entries next to prefetch ones. Drop
 342         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 343         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 344         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 345         PREFIX_OPCODE from endbr* entries.
 346         (get_valid_dis386): Also consider entry's name when zapping
 347         vindex.
 348         (print_insn): Handle PREFIX_IGNORED.
 349
 350 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 351
 352         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 353         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 354         element.
 355         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 356         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 357         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 358         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 359         (struct i386_opcode_modifier): Delete notrackprefixok,
 360         islockable, hleprefixok, and repprefixok fields. Add prefixok
 361         field.
 362         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 363         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 364         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 365         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 366         Replace HLEPrefixOk.
 367         * opcodes/i386-tbl.h: Re-generate.
 368
 369 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 370
 371         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 372         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 373         64-bit form.
 374         * opcodes/i386-tbl.h: Re-generate.
 375
 376 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 379         for {} instead of {0}. Don't look for '0'.
 380         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 381         size specifiers.
 382
 383 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 384
 385         PR 27158
 386         * riscv-dis.c (print_insn_args): Updated encoding macros.
 387         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 388         (match_c_addi16sp): Updated encoding macros.
 389         (match_c_lui): Likewise.
 390         (match_c_lui_with_hint): Likewise.
 391         (match_c_addi4spn): Likewise.
 392         (match_c_slli): Likewise.
 393         (match_slli_as_c_slli): Likewise.
 394         (match_c_slli64): Likewise.
 395         (match_srxi_as_c_srxi): Likewise.
 396         (riscv_insn_types): Added .insn css/cl/cs.
 397
 398 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 399
 400         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 401         (default_priv_spec): Updated type to riscv_spec_class.
 402         (parse_riscv_dis_option): Updated.
 403         * riscv-opc.c: Moved stuff and make the file tidy.
 404
 405 2021-02-17  Alan Modra  <amodra@gmail.com>
 406
 407         * wasm32-dis.c: Include limits.h.
 408         (CHAR_BIT): Provide backup define.
 409         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 410         Correct signed overflow checking.
 411
 412 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 413
 414         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 415         * i386-tbl.h: Re-generate.
 416
 417 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 418
 419         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 420         Oword.
 421         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 422
 423 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 424
 425         * s390-mkopc.c (main): Accept arch14 as cpu string.
 426         * s390-opc.txt: Add new arch14 instructions.
 427
 428 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 429
 430         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 431         favour of LIBINTL.
 432         * configure: Regenerated.
 433
 434 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 435
 436         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 437         * tic54x-opc.c (regs): Rename to ...
 438         (tic54x_regs): ... this.
 439         (mmregs): Rename to ...
 440         (tic54x_mmregs): ... this.
 441         (condition_codes): Rename to ...
 442         (tic54x_condition_codes): ... this.
 443         (cc2_codes): Rename to ...
 444         (tic54x_cc2_codes): ... this.
 445         (cc3_codes): Rename to ...
 446         (tic54x_cc3_codes): ... this.
 447         (status_bits): Rename to ...
 448         (tic54x_status_bits): ... this.
 449         (misc_symbols): Rename to ...
 450         (tic54x_misc_symbols): ... this.
 451
 452 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 453
 454         * riscv-opc.c (MASK_RVB_IMM): Removed.
 455         (riscv_opcodes): Removed zb* instructions.
 456         (riscv_ext_version_table): Removed versions for zb*.
 457
 458 2021-01-26  Alan Modra  <amodra@gmail.com>
 459
 460         * i386-gen.c (parse_template): Ensure entire template_instance
 461         is initialised.
 462
 463 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 464
 465         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 466         (riscv_fpr_names_abi): Likewise.
 467         (riscv_opcodes): Likewise.
 468         (riscv_insn_types): Likewise.
 469
 470 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 471
 472         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 473
 474 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 475
 476         * riscv-dis.c: Comments tidy and improvement.
 477         * riscv-opc.c: Likewise.
 478
 479 2021-01-13  Alan Modra  <amodra@gmail.com>
 480
 481         * Makefile.in: Regenerate.
 482
 483 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 484
 485         PR binutils/26792
 486         * configure.ac: Use GNU_MAKE_JOBSERVER.
 487         * aclocal.m4: Regenerated.
 488         * configure: Likewise.
 489
 490 2021-01-12  Nick Clifton  <nickc@redhat.com>
 491
 492         * po/sr.po: Updated Serbian translation.
 493
 494 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 495
 496         PR ld/27173
 497         * configure: Regenerated.
 498
 499 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 500
 501         * aarch64-asm-2.c: Regenerate.
 502         * aarch64-dis-2.c: Likewise.
 503         * aarch64-opc-2.c: Likewise.
 504         * aarch64-opc.c (aarch64_print_operand):
 505         Delete handling of AARCH64_OPND_CSRE_CSR.
 506         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 507         (CSRE): Likewise.
 508         (_CSRE_INSN): Likewise.
 509         (aarch64_opcode_table): Delete csr.
 510
 511 2021-01-11  Nick Clifton  <nickc@redhat.com>
 512
 513         * po/de.po: Updated German translation.
 514         * po/fr.po: Updated French translation.
 515         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 516         * po/sv.po: Updated Swedish translation.
 517         * po/uk.po: Updated Ukranian translation.
 518
 519 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 520
 521         * configure: Regenerated.
 522
 523 2021-01-09  Nick Clifton  <nickc@redhat.com>
 524
 525         * configure: Regenerate.
 526         * po/opcodes.pot: Regenerate.
 527
 528 2021-01-09  Nick Clifton  <nickc@redhat.com>
 529
 530         * 2.36 release branch crated.
 531
 532 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 533
 534         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 535         (DW, (XRC_MASK): Define.
 536         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 537
 538 2021-01-09  Alan Modra  <amodra@gmail.com>
 539
 540         * configure: Regenerate.
 541
 542 2021-01-08  Nick Clifton  <nickc@redhat.com>
 543
 544         * po/sv.po: Updated Swedish translation.
 545
 546 2021-01-08  Nick Clifton  <nickc@redhat.com>
 547
 548         PR 27129
 549         * aarch64-dis.c (determine_disassembling_preference): Move call to
 550         aarch64_match_operands_constraint outside of the assertion.
 551         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 552         Replace with a return of FALSE.
 553
 554         PR 27139
 555         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 556         core system register.
 557
 558 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 559
 560         * configure: Regenerate.
 561
 562 2021-01-07  Nick Clifton  <nickc@redhat.com>
 563
 564         * po/fr.po: Updated French translation.
 565
 566 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 567
 568         * m68k-opc.c (chkl): Change minimum architecture requirement to
 569         m68020.
 570
 571 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 572
 573         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 574
 575 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 576             Jim Wilson  <jimw@sifive.com>
 577             Andrew Waterman  <andrew@sifive.com>
 578             Maxim Blinov  <maxim.blinov@embecosm.com>
 579             Kito Cheng  <kito.cheng@sifive.com>
 580             Nelson Chu  <nelson.chu@sifive.com>
 581
 582         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 583         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 584
 585 2021-01-01  Alan Modra  <amodra@gmail.com>
 586
 587         Update year range in copyright notice of all files.
 588
 589 For older changes see ChangeLog-2020
 590 \f
 591 Copyright (C) 2021 Free Software Foundation, Inc.
 592
 593 Copying and distribution of this file, with or without modification,
 594 are permitted in any medium without royalty provided the copyright
 595 notice and this notice are preserved.
 596
 597 Local Variables:
 598 mode: change-log
 599 left-margin: 8
 600 fill-column: 74
 601 version-control: never
 602 End: