1 2020-10-26 Cooper Qu <cooper.qu@linux.alibaba.com>
3 * csky-dis.c (csky_output_operand): Add handler for
4 OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
5 * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
6 (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add
7 some instructions for VDSPV1.
9 2020-10-26 Lili Cui <lili.cui@intel.com>
11 * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix.
13 2020-10-22 H.J. Lu <hongjiu.lu@intel.com>
15 * po/es.po: Remove the duplicated entry.
17 2020-10-20 Dr. David Alan Gilbert <dgilbert@redhat.com>
19 * po/es.po: Fix printf format.
21 2020-10-20 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
23 * i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
24 * i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
25 CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
27 (cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
28 * i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
29 * i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
31 * i386-init.h: Re-generated.
32 * i386-tbl.h: Re-generated.
34 2020-10-16 Lili Cui <lili.cui@intel.com>
36 * i386-opc.tbl: Rename CpuVEX_PREFIX to PseudoVexPrefix
37 and move it from cpu_flags to opcode_modifiers.
38 Use VexW0 and VexVVVV in the AVX-VNNI instructions.
39 * i386-gen.c: Likewise.
40 * i386-opc.h: Likewise.
41 * i386-opc.h: Likewise.
42 * i386-init.h: Regenerated.
43 * i386-tbl.h: Likewise.
45 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
46 Lili Cui <lili.cui@intel.com>
48 * i386-dis.c (PREFIX_VEX_0F3850): New.
49 (PREFIX_VEX_0F3851): Likewise.
50 (PREFIX_VEX_0F3852): Likewise.
51 (PREFIX_VEX_0F3853): Likewise.
52 (VEX_W_0F3850_P_2): Likewise.
53 (VEX_W_0F3851_P_2): Likewise.
54 (VEX_W_0F3852_P_2): Likewise.
55 (VEX_W_0F3853_P_2): Likewise.
56 (prefix_table): Add PREFIX_VEX_0F3850, PREFIX_VEX_0F3851,
57 PREFIX_VEX_0F3852 and PREFIX_VEX_0F3853.
58 (vex_table): Add VEX_W_0F3850_P_2, VEX_W_0F3851_P_2,
59 VEX_W_0F3852_P_2 and VEX_W_0F3853_P_2.
60 (putop): Add support for "XV" to print "{vex3}" pseudo prefix.
61 * i386-gen.c (cpu_flag_init): Clear the CpuAVX_VNNI bit in
62 CPU_UNKNOWN_FLAGS. Add CPU_AVX_VNNI_FLAGS and
63 CPU_ANY_AVX_VNNI_FLAGS.
64 (cpu_flags): Add CpuAVX_VNNI and CpuVEX_PREFIX.
65 * i386-opc.h (CpuAVX_VNNI): New.
66 (CpuVEX_PREFIX): Likewise.
67 (i386_cpu_flags): Add cpuavx_vnni and cpuvex_prefix.
68 * i386-opc.tbl: Add Intel AVX VNNI instructions.
69 * i386-init.h: Regenerated.
70 * i386-tbl.h: Likewise.
72 2020-10-14 Lili Cui <lili.cui@intel.com>
73 H.J. Lu <hongjiu.lu@intel.com>
75 * i386-dis.c (PREFIX_0F3A0F): New.
76 (MOD_0F3A0F_PREFIX_1): Likewise.
77 (REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
78 (RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
79 (prefix_table): Add PREFIX_0F3A0F.
80 (mod_table): Add MOD_0F3A0F_PREFIX_1.
81 (reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
82 (rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
83 * i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
85 (cpu_flags): Add CpuHRESET.
86 (output_i386_opcode): Allow 4 byte base_opcode.
87 * i386-opc.h (enum): Add CpuHRESET.
88 (i386_cpu_flags): Add cpuhreset.
89 * i386-opc.tbl: Add Intel HRESET instruction.
90 * i386-init.h: Regenerate.
91 * i386-tbl.h: Likewise.
93 2020-10-14 Lili Cui <lili.cui@intel.com>
95 * i386-dis.c (enum): Add
96 PREFIX_MOD_3_0F01_REG_5_RM_4,
97 PREFIX_MOD_3_0F01_REG_5_RM_5,
98 PREFIX_MOD_3_0F01_REG_5_RM_6,
99 PREFIX_MOD_3_0F01_REG_5_RM_7,
100 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
101 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
102 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
103 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
104 X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
105 (prefix_table): New instructions (see prefixes above).
107 * i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
109 (cpu_flags): Add CpuUINTR.
110 * i386-opc.h (enum): Add CpuUINTR.
111 (i386_cpu_flags): Add cpuuintr.
112 * i386-opc.tbl: Add UINTR insns.
113 * i386-init.h: Regenerate.
114 * i386-tbl.h: Likewise.
116 2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
118 * i386-gen.c (process_i386_opcode_modifier): Return 1 for
119 non-VEX/EVEX/prefix encoding.
120 (output_i386_opcode): Fail if non-VEX/EVEX/prefix base_opcode
122 * i386-opc.tbl: Replace the prefix byte in non-VEX/EVEX
123 base_opcode with PREFIX_0X66, PREFIX_0XF2 or PREFIX_0XF3.
124 * i386-tbl.h: Regenerated.
126 2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
128 * i386-gen.c (opcode_modifiers): Replace VexOpcode with
130 * i386-opc.h (VexOpcode): Renamed to ...
131 (OpcodePrefix): This.
133 (PREFIX_0X66): Likewise.
134 (PREFIX_0XF2): Likewise.
135 (PREFIX_0XF3): Likewise.
136 * i386-opc.tbl (Prefix_0X66): New.
137 (Prefix_0XF2): Likewise.
138 (Prefix_0XF3): Likewise.
139 Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
140 Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
141 * i386-tbl.h: Regenerated.
143 2020-10-05 Samanta Navarro <ferivoz@riseup.net>
145 * cgen-asm.c: Fix spelling mistakes.
146 * cgen-dis.c: Fix spelling mistakes.
147 * tic30-dis.c: Fix spelling mistakes.
149 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
152 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
154 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
157 * i386-dis.c (print_insn): Clear modrm if not needed.
158 (putop): Check need_modrm for modrm.mod != 3. Don't check
159 need_modrm for modrm.mod == 3.
161 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
163 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
164 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
165 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
166 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
167 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
168 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
169 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
170 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
171 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
172 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
173 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
174 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
175 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
176 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
178 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
180 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
182 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
184 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
185 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
187 2020-09-26 Alan Modra <amodra@gmail.com>
189 * csky-opc.h: Formatting.
190 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
191 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
193 (get_register_number): Likewise.
194 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
196 2020-09-24 Lili Cui <lili.cui@intel.com>
199 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
201 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
203 * csky-dis.c (csky_output_operand): Enclose body of if in curly
206 2020-09-24 Lili Cui <lili.cui@intel.com>
208 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
209 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
210 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
211 X86_64_0F01_REG_1_RM_7_P_2.
212 (prefix_table): Likewise.
213 (x86_64_table): Likewise.
214 (rm_table): Likewise.
215 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
216 and CPU_ANY_TDX_FLAGS.
217 (cpu_flags): Add CpuTDX.
218 * i386-opc.h (enum): Add CpuTDX.
219 (i386_cpu_flags): Add cputdx.
220 * i386-opc.tbl: Add TDX insns.
221 * i386-init.h: Regenerate.
222 * i386-tbl.h: Likewise.
224 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
226 * csky-dis.c (using_abi): New.
227 (parse_csky_dis_options): New function.
228 (get_gr_name): New function.
229 (get_cr_name): New function.
230 (csky_output_operand): Use get_gr_name and get_cr_name to
231 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
232 (print_insn_csky): Parse disassembler options.
233 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
234 (GENARAL_REG_BANK): Define.
235 (REG_SUPPORT_ALL): Define.
236 (REG_SUPPORT_ALL): New.
238 (REG_SUPPORT_A): Define.
239 (REG_SUPPORT_B): Define.
240 (REG_SUPPORT_C): Define.
241 (REG_SUPPORT_D): Define.
242 (REG_SUPPORT_E): Define.
243 (csky_abiv1_general_regs): New.
244 (csky_abiv1_control_regs): New.
245 (csky_abiv2_general_regs): New.
246 (csky_abiv2_control_regs): New.
247 (get_register_name): New function.
248 (get_register_number): New function.
249 (csky_get_general_reg_name): New function.
250 (csky_get_general_regno): New function.
251 (csky_get_control_reg_name): New function.
252 (csky_get_control_regno): New function.
253 (csky_v2_opcodes): Prefer two oprerans format for bclri and
254 bseti, strengthen the operands legality check of addc, zext
257 2020-09-23 Lili Cui <lili.cui@intel.com>
259 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
260 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
261 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
262 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
263 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
264 (reg_table): New instructions (see prefixes above).
265 (prefix_table): Likewise.
266 (three_byte_table): Likewise.
267 (mod_table): Likewise
268 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
269 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
270 (cpu_flags): Likewise.
271 (operand_type_init): Likewise.
272 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
273 (i386_cpu_flags): Add cpukl and cpuwide_kl.
274 * i386-opc.tbl: Add KL and WIDE_KL insns.
275 * i386-init.h: Regenerate.
276 * i386-tbl.h: Likewise.
278 2020-09-21 Alan Modra <amodra@gmail.com>
280 * rx-dis.c (flag_names): Add missing comma.
281 (register_names, flag_names, double_register_names),
282 (double_register_high_names, double_register_low_names),
283 (double_control_register_names, double_condition_names): Remove
286 2020-09-18 David Faust <david.faust@oracle.com>
288 * bpf-desc.c: Regenerate.
289 * bpf-desc.h: Likewise.
290 * bpf-opc.c: Likewise.
291 * bpf-opc.h: Likewise.
293 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
295 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
298 2020-09-16 Alan Modra <amodra@gmail.com>
300 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
302 2020-09-10 Nick Clifton <nickc@redhat.com>
304 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
305 for hidden, local, no-type symbols.
306 (disassemble_init_powerpc): Point the symbol_is_valid field in the
307 info structure at the new function.
309 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
311 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
312 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
315 2020-09-10 Nick Clifton <nickc@redhat.com>
317 * csky-dis.c (csky_output_operand): Coerce the immediate values to
318 long before printing.
320 2020-09-10 Alan Modra <amodra@gmail.com>
322 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
324 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
326 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
329 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
331 * csky-dis.c (csky_output_operand): Add handlers for
332 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
333 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
334 to support FPUV3 instructions.
335 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
336 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
337 OPRND_TYPE_DFLOAT_FMOVI.
338 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
339 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
340 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
341 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
342 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
343 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
344 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
345 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
346 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
347 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
348 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
349 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
350 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
351 (csky_v2_opcodes): Add FPUV3 instructions.
353 2020-09-08 Alex Coplan <alex.coplan@arm.com>
355 * aarch64-dis.c (print_operands): Pass CPU features to
356 aarch64_print_operand().
357 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
358 preferred disassembly of system registers.
359 (SR_RNG): Refactor to use new SR_FEAT2 macro.
365 (SR_EXPAND_ELx): New.
366 (SR_EXPAND_EL12): New.
367 (aarch64_sys_regs): Specify which registers are only on
368 A-profile, add R-profile system registers.
372 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
375 2020-09-08 Alex Coplan <alex.coplan@arm.com>
377 * aarch64-tbl.h (aarch64_feature_v8_r): New.
380 (aarch64_opcode_table): Add dfb.
381 * aarch64-opc-2.c: Regenerate.
382 * aarch64-asm-2.c: Regenerate.
383 * aarch64-dis-2.c: Regenerate.
385 2020-09-08 Alex Coplan <alex.coplan@arm.com>
387 * aarch64-dis.c (arch_variant): New.
388 (determine_disassembling_preference): Disassemble according to
390 (select_aarch64_variant): New.
391 (print_insn_aarch64): Set feature set.
393 2020-09-02 Alan Modra <amodra@gmail.com>
395 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
396 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
397 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
398 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
399 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
400 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
401 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
402 for value parameter and update code to suit.
403 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
404 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
406 2020-09-02 Alan Modra <amodra@gmail.com>
408 * i386-dis.c (OP_E_memory): Don't cast to signed type when
410 (get32, get32s): Use unsigned types in shift expressions.
412 2020-09-02 Alan Modra <amodra@gmail.com>
414 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
416 2020-09-02 Alan Modra <amodra@gmail.com>
418 * crx-dis.c: Whitespace.
419 (print_arg): Use unsigned type for longdisp and mask variables,
420 and for left shift constant.
422 2020-09-02 Alan Modra <amodra@gmail.com>
424 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
425 * bpf-ibld.c: Regenerate.
426 * epiphany-ibld.c: Regenerate.
427 * fr30-ibld.c: Regenerate.
428 * frv-ibld.c: Regenerate.
429 * ip2k-ibld.c: Regenerate.
430 * iq2000-ibld.c: Regenerate.
431 * lm32-ibld.c: Regenerate.
432 * m32c-ibld.c: Regenerate.
433 * m32r-ibld.c: Regenerate.
434 * mep-ibld.c: Regenerate.
435 * mt-ibld.c: Regenerate.
436 * or1k-ibld.c: Regenerate.
437 * xc16x-ibld.c: Regenerate.
438 * xstormy16-ibld.c: Regenerate.
440 2020-09-02 Alan Modra <amodra@gmail.com>
442 * bfin-dis.c (MASKBITS): Use SIGNBIT.
444 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
446 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
447 to CSKYV2_ISA_3E3R3 instruction set.
449 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
451 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
453 2020-09-01 Alan Modra <amodra@gmail.com>
455 * mep-ibld.c: Regenerate.
457 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
459 * csky-dis.c (csky_output_operand): Assign dis_info.value for
462 2020-08-30 Alan Modra <amodra@gmail.com>
464 * cr16-dis.c: Formatting.
465 (parameter): Delete struct typedef. Use dwordU instead
467 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
469 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
471 2020-08-29 Alan Modra <amodra@gmail.com>
474 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
475 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
477 2020-08-28 Alan Modra <amodra@gmail.com>
481 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
482 (extract_normal): Likewise.
483 (insert_normal): Likewise, and move past zero length test.
484 (put_insn_int_value): Handle mask for zero length, use 1UL.
485 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
486 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
487 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
488 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
490 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
492 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
493 (csky_dis_info): Add member isa.
494 (csky_find_inst_info): Skip instructions that do not belong to
496 (csky_get_disassembler): Get infomation from attribute section.
497 (print_insn_csky): Set defualt ISA flag.
498 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
499 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
500 isa_flag32'type to unsigned 64 bits.
502 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
504 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
506 2020-08-26 David Faust <david.faust@oracle.com>
508 * bpf-desc.c: Regenerate.
509 * bpf-desc.h: Likewise.
510 * bpf-opc.c: Likewise.
511 * bpf-opc.h: Likewise.
512 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
513 ISA when appropriate.
515 2020-08-25 Alan Modra <amodra@gmail.com>
518 * vax-dis.c (parse_disassembler_options): Always add at least one
519 to entry_addr_total_slots.
521 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
523 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
524 in other CPUs to speed up disassembling.
525 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
526 Change plsli.u16 to plsli.16, change sync's operand format.
528 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
530 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
532 2020-08-21 Nick Clifton <nickc@redhat.com>
534 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
537 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
539 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
541 2020-08-19 Alan Modra <amodra@gmail.com>
543 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
546 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
548 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
549 <xvcvbf16spn>: ...to this.
551 2020-08-12 Alex Coplan <alex.coplan@arm.com>
553 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
555 2020-08-12 Nick Clifton <nickc@redhat.com>
557 * po/sr.po: Updated Serbian translation.
559 2020-08-11 Alan Modra <amodra@gmail.com>
561 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
563 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
565 * aarch64-opc.c (aarch64_print_operand):
566 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
567 (aarch64_sys_reg_supported_p): Function removed.
568 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
569 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
572 2020-08-10 Alan Modra <amodra@gmail.com>
574 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
577 2020-08-10 Alan Modra <amodra@gmail.com>
579 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
580 Enable icbt for power5, miso for power8.
582 2020-08-10 Alan Modra <amodra@gmail.com>
584 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
585 mtvsrd, and similarly for mfvsrd.
587 2020-08-04 Christian Groessler <chris@groessler.org>
588 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
590 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
591 opcodes (special "out" to absolute address).
592 * z8k-opc.h: Regenerate.
594 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
597 * i386-opc.h (Prefix_Disp8): New.
598 (Prefix_Disp16): Likewise.
599 (Prefix_Disp32): Likewise.
600 (Prefix_Load): Likewise.
601 (Prefix_Store): Likewise.
602 (Prefix_VEX): Likewise.
603 (Prefix_VEX3): Likewise.
604 (Prefix_EVEX): Likewise.
605 (Prefix_REX): Likewise.
606 (Prefix_NoOptimize): Likewise.
607 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
608 * i386-tbl.h: Regenerated.
610 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
612 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
613 default case with abort() instead of printing an error message and
614 continuing, to avoid a maybe-uninitialized warning.
616 2020-07-24 Nick Clifton <nickc@redhat.com>
618 * po/de.po: Updated German translation.
620 2020-07-21 Jan Beulich <jbeulich@suse.com>
622 * i386-dis.c (OP_E_memory): Revert previous change.
624 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
627 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
628 without base nor index registers.
630 2020-07-15 Jan Beulich <jbeulich@suse.com>
632 * i386-dis.c (putop): Move 'V' and 'W' handling.
634 2020-07-15 Jan Beulich <jbeulich@suse.com>
636 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
637 construct for push/pop of register.
638 (putop): Honor cond when handling 'P'. Drop handling of plain
641 2020-07-15 Jan Beulich <jbeulich@suse.com>
643 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
644 description. Drop '&' description. Use P for push of immediate,
645 pushf/popf, enter, and leave. Use %LP for lret/retf.
646 (dis386_twobyte): Use P for push/pop of fs/gs.
647 (reg_table): Use P for push/pop. Use @ for near call/jmp.
648 (x86_64_table): Use P for far call/jmp.
649 (putop): Drop handling of 'U' and '&'. Move and adjust handling
650 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
652 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
653 and dqw_mode (unconditional).
655 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
658 * i386-dis.c (OP_E_memory): Without base nor index registers,
659 32-bit displacement to 64 bits.
661 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
663 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
664 faulty double register pair is detected.
666 2020-07-14 Jan Beulich <jbeulich@suse.com>
668 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
670 2020-07-14 Jan Beulich <jbeulich@suse.com>
672 * i386-dis.c (OP_R, Rm): Delete.
673 (MOD_0F24, MOD_0F26): Rename to ...
674 (X86_64_0F24, X86_64_0F26): ... respectively.
675 (dis386): Update 'L' and 'Z' comments.
676 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
678 (mod_table): Move opcode 0F24 and 0F26 entries ...
679 (x86_64_table): ... here.
680 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
683 2020-07-14 Jan Beulich <jbeulich@suse.com>
685 * i386-dis.c (Rd, Rdq, MaskR): Delete.
686 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
687 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
688 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
689 MOD_EVEX_0F387C): New enumerators.
690 (reg_table): Use Edq for rdssp.
691 (prefix_table): Use Edq for incssp.
692 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
693 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
694 ktest*, and kshift*. Use Edq / MaskE for kmov*.
695 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
696 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
697 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
698 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
699 0F3828_P_1 and 0F3838_P_1.
700 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
701 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
703 2020-07-14 Jan Beulich <jbeulich@suse.com>
705 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
706 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
707 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
708 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
709 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
710 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
711 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
712 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
713 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
714 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
715 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
716 (reg_table, prefix_table, three_byte_table, vex_table,
717 vex_len_table, mod_table, rm_table): Replace / remove respective
719 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
720 of PREFIX_DATA in used_prefixes.
722 2020-07-14 Jan Beulich <jbeulich@suse.com>
724 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
725 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
726 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
727 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
728 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
729 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
730 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
731 VEX_W_0F3A33_L_0): Delete.
732 (dis386): Adjust "BW" description.
733 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
734 0F3A31, 0F3A32, and 0F3A33.
735 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
737 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
740 2020-07-14 Jan Beulich <jbeulich@suse.com>
742 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
743 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
744 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
745 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
746 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
747 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
748 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
749 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
750 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
751 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
752 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
753 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
754 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
755 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
756 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
757 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
758 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
759 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
760 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
761 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
762 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
763 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
764 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
765 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
766 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
767 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
768 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
769 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
770 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
771 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
772 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
773 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
774 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
775 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
776 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
777 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
778 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
779 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
780 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
781 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
782 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
783 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
784 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
785 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
786 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
787 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
788 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
789 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
790 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
791 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
792 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
793 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
794 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
795 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
796 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
797 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
798 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
799 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
800 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
801 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
802 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
803 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
804 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
805 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
806 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
807 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
808 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
809 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
810 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
811 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
812 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
813 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
814 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
815 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
816 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
817 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
818 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
819 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
820 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
821 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
822 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
823 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
824 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
825 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
826 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
827 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
828 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
829 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
830 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
831 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
832 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
833 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
834 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
835 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
836 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
837 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
838 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
839 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
840 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
841 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
842 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
843 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
844 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
845 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
846 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
847 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
848 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
849 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
850 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
851 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
852 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
853 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
854 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
855 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
856 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
857 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
858 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
859 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
860 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
861 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
862 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
863 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
864 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
865 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
866 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
867 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
868 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
869 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
870 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
871 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
872 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
873 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
874 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
875 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
876 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
877 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
878 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
879 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
880 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
881 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
882 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
883 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
884 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
885 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
886 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
887 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
888 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
889 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
890 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
891 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
892 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
893 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
894 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
895 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
896 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
897 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
898 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
899 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
900 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
901 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
902 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
903 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
904 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
905 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
906 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
907 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
908 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
909 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
910 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
911 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
912 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
913 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
914 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
915 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
916 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
917 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
918 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
919 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
920 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
921 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
922 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
923 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
924 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
925 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
926 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
927 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
928 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
929 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
930 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
931 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
932 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
933 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
934 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
935 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
936 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
937 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
938 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
939 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
940 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
941 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
942 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
943 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
944 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
945 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
946 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
947 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
948 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
949 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
950 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
951 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
952 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
953 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
954 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
955 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
956 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
957 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
958 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
959 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
960 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
961 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
962 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
963 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
964 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
965 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
966 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
967 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
968 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
969 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
970 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
971 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
972 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
973 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
974 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
975 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
976 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
977 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
978 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
979 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
980 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
981 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
982 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
983 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
984 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
985 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
986 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
987 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
988 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
989 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
990 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
991 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
992 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
993 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
994 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
995 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
996 EVEX_W_0F3A72_P_2): Rename to ...
997 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
998 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
999 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
1000 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
1001 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
1002 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
1003 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
1004 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
1005 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
1006 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
1007 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
1008 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
1009 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
1010 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
1011 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
1012 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
1013 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
1014 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
1015 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
1016 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
1017 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
1018 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1019 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1020 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1021 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
1022 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
1023 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
1024 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
1025 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
1026 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
1027 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
1028 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
1029 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
1030 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
1031 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
1032 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1033 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
1034 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
1035 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
1036 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
1037 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1038 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
1039 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
1040 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1041 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
1042 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
1043 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
1044 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
1045 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
1046 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
1047 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
1048 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
1049 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
1050 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
1051 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
1052 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
1053 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
1054 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
1055 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
1056 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
1057 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
1058 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
1059 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
1060 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
1061 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
1062 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
1063 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
1064 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
1065 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
1066 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
1067 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
1068 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
1070 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
1071 vex_w_table, mod_table): Replace / remove respective entries.
1072 (print_insn): Move up dp->prefix_requirement handling. Handle
1074 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
1075 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
1076 Replace / remove respective entries.
1078 2020-07-14 Jan Beulich <jbeulich@suse.com>
1080 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
1081 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
1082 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
1083 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
1084 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
1086 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1087 0F2C, 0F2D, 0F2E, and 0F2F.
1088 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
1091 2020-07-14 Jan Beulich <jbeulich@suse.com>
1093 * i386-dis.c (OP_VexR, VexScalarR): New.
1094 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
1095 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
1096 need_vex_reg): Delete.
1097 (prefix_table): Replace VexScalar by VexScalarR and
1098 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1099 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1100 (vex_len_table): Replace EXqVexScalarS by EXqS.
1101 (get_valid_dis386): Don't set need_vex_reg.
1102 (print_insn): Don't initialize need_vex_reg.
1103 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
1104 q_scalar_swap_mode cases.
1105 (OP_EX): Don't check for d_scalar_swap_mode and
1107 (OP_VEX): Done check need_vex_reg.
1108 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
1109 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
1110 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
1112 2020-07-14 Jan Beulich <jbeulich@suse.com>
1114 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
1115 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
1116 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
1117 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
1118 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
1119 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
1120 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
1121 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
1122 (vex_table): Replace Vex128 by Vex.
1123 (vex_len_table): Likewise. Adjust referenced enum names.
1124 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
1125 referenced enum names.
1126 (OP_VEX): Drop vex128_mode and vex256_mode cases.
1127 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
1129 2020-07-14 Jan Beulich <jbeulich@suse.com>
1131 * i386-dis.c (dis386): "LW" description now applies to "DQ".
1132 (putop): Handle "DQ". Don't handle "LW" anymore.
1133 (prefix_table, mod_table): Replace %LW by %DQ.
1134 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
1136 2020-07-14 Jan Beulich <jbeulich@suse.com>
1138 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
1139 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
1140 d_scalar_swap_mode case handling. Move shift adjsutment into
1141 the case its applicable to.
1143 2020-07-14 Jan Beulich <jbeulich@suse.com>
1145 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
1146 (EXbScalar, EXwScalar): Fold to ...
1147 (EXbwUnit): ... this.
1148 (b_scalar_mode, w_scalar_mode): Fold to ...
1149 (bw_unit_mode): ... this.
1150 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1151 w_scalar_mode handling by bw_unit_mode one.
1152 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1154 * i386-dis-evex-prefix.h: ... here.
1156 2020-07-14 Jan Beulich <jbeulich@suse.com>
1158 * i386-dis.c (PCMPESTR_Fixup): Delete.
1159 (dis386): Adjust "LQ" description.
1160 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1161 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1162 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1163 vpcmpestrm, and vpcmpestri.
1164 (putop): Honor "cond" when handling LQ.
1165 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1166 vcvtsi2ss and vcvtusi2ss.
1167 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1168 vcvtsi2sd and vcvtusi2sd.
1170 2020-07-14 Jan Beulich <jbeulich@suse.com>
1172 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1173 (simd_cmp_op): Add const.
1174 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1175 (CMP_Fixup): Handle VEX case.
1176 (prefix_table): Replace VCMP by CMP.
1177 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1179 2020-07-14 Jan Beulich <jbeulich@suse.com>
1181 * i386-dis.c (MOVBE_Fixup): Delete.
1183 (prefix_table): Use Mv for movbe entries.
1185 2020-07-14 Jan Beulich <jbeulich@suse.com>
1187 * i386-dis.c (CRC32_Fixup): Delete.
1188 (prefix_table): Use Eb/Ev for crc32 entries.
1190 2020-07-14 Jan Beulich <jbeulich@suse.com>
1192 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1193 Conditionalize invocations of "USED_REX (0)".
1195 2020-07-14 Jan Beulich <jbeulich@suse.com>
1197 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1198 CH, DH, BH, AX, DX): Delete.
1199 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1200 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1201 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1203 2020-07-10 Lili Cui <lili.cui@intel.com>
1205 * i386-dis.c (TMM): New.
1208 (MVexSIBMEM): Likewise.
1209 (tmm_mode): Likewise.
1210 (vex_sibmem_mode): Likewise.
1211 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1212 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1213 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1214 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1215 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1216 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1217 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1218 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1219 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1220 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1221 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1222 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1223 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1224 (PREFIX_VEX_0F3849_X86_64): Likewise.
1225 (PREFIX_VEX_0F384B_X86_64): Likewise.
1226 (PREFIX_VEX_0F385C_X86_64): Likewise.
1227 (PREFIX_VEX_0F385E_X86_64): Likewise.
1228 (X86_64_VEX_0F3849): Likewise.
1229 (X86_64_VEX_0F384B): Likewise.
1230 (X86_64_VEX_0F385C): Likewise.
1231 (X86_64_VEX_0F385E): Likewise.
1232 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1233 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1234 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1235 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1236 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1237 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1238 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1239 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1240 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1241 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1242 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1243 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1244 (VEX_W_0F3849_X86_64_P_0): Likewise.
1245 (VEX_W_0F3849_X86_64_P_2): Likewise.
1246 (VEX_W_0F3849_X86_64_P_3): Likewise.
1247 (VEX_W_0F384B_X86_64_P_1): Likewise.
1248 (VEX_W_0F384B_X86_64_P_2): Likewise.
1249 (VEX_W_0F384B_X86_64_P_3): Likewise.
1250 (VEX_W_0F385C_X86_64_P_1): Likewise.
1251 (VEX_W_0F385E_X86_64_P_0): Likewise.
1252 (VEX_W_0F385E_X86_64_P_1): Likewise.
1253 (VEX_W_0F385E_X86_64_P_2): Likewise.
1254 (VEX_W_0F385E_X86_64_P_3): Likewise.
1255 (names_tmm): Likewise.
1256 (att_names_tmm): Likewise.
1257 (intel_operand_size): Handle void_mode.
1258 (OP_XMM): Handle tmm_mode.
1261 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1262 CpuAMX_BF16 and CpuAMX_TILE.
1263 (operand_type_shorthands): Add RegTMM.
1264 (operand_type_init): Likewise.
1265 (operand_types): Add Tmmword.
1266 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1267 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1268 * i386-opc.h (CpuAMX_INT8): New.
1269 (CpuAMX_BF16): Likewise.
1270 (CpuAMX_TILE): Likewise.
1272 (Tmmword): Likewise.
1273 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1274 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1275 (i386_operand_type): Add tmmword.
1276 * i386-opc.tbl: Add AMX instructions.
1277 * i386-reg.tbl: Add AMX registers.
1278 * i386-init.h: Regenerated.
1279 * i386-tbl.h: Likewise.
1281 2020-07-08 Jan Beulich <jbeulich@suse.com>
1283 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1284 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1286 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1287 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1289 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1290 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1291 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1292 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1293 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1294 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1295 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1296 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1297 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1298 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1299 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1300 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1301 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1302 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1303 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1304 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1305 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1306 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1307 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1308 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1309 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1310 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1311 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1312 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1313 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1314 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1315 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1316 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1317 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1318 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1319 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1320 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1321 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1322 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1323 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1324 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1325 (reg_table): Re-order XOP entries. Adjust their operands.
1326 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1327 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1328 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1329 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1330 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1331 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1332 entries by references ...
1333 (vex_len_table): ... to resepctive new entries here. For several
1334 new and existing entries reference ...
1335 (vex_w_table): ... new entries here.
1336 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1338 2020-07-08 Jan Beulich <jbeulich@suse.com>
1340 * i386-dis.c (XMVexScalarI4): Define.
1341 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1342 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1343 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1344 (vex_len_table): Move scalar FMA4 entries ...
1345 (prefix_table): ... here.
1346 (OP_REG_VexI4): Handle scalar_mode.
1347 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1348 * i386-tbl.h: Re-generate.
1350 2020-07-08 Jan Beulich <jbeulich@suse.com>
1352 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1353 Vex_2src_2): Delete.
1354 (OP_VexW, VexW): New.
1355 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1356 for shifts and rotates by register.
1358 2020-07-08 Jan Beulich <jbeulich@suse.com>
1360 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1361 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1362 OP_EX_VexReg): Delete.
1363 (OP_VexI4, VexI4): New.
1364 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1365 (prefix_table): ... here.
1366 (print_insn): Drop setting of vex_w_done.
1368 2020-07-08 Jan Beulich <jbeulich@suse.com>
1370 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1371 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1372 (xop_table): Replace operands of 4-operand insns.
1373 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1375 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1377 * arc-opc.c (insert_rbd): New function.
1380 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1383 2020-07-07 Jan Beulich <jbeulich@suse.com>
1385 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1386 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1387 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1388 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1390 (putop): Handle "BW".
1391 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1392 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1394 * i386-dis-evex-prefix.h: ... here.
1396 2020-07-06 Jan Beulich <jbeulich@suse.com>
1398 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1399 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1400 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1401 VEX_W_0FXOP_09_83): New enumerators.
1402 (xop_table): Reference the above.
1403 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1404 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1405 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1406 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1408 2020-07-06 Jan Beulich <jbeulich@suse.com>
1410 * i386-dis.c (EVEX_W_0F3838_P_1,
1411 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1412 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1413 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1414 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1415 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1416 (putop): Centralize management of last[]. Delete SAVE_LAST.
1417 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1418 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1419 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1420 * i386-dis-evex-prefix.h: here.
1422 2020-07-06 Jan Beulich <jbeulich@suse.com>
1424 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1425 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1426 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1427 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1429 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1430 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1431 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1432 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1433 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1434 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1435 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1436 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1437 these, respectively.
1438 * i386-dis-evex-len.h: Adjust comments.
1439 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1440 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1441 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1442 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1443 MOD_EVEX_0F385B_P_2_W_1 table entries.
1444 * i386-dis-evex-w.h: Reference mod_table[] for
1445 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1448 2020-07-06 Jan Beulich <jbeulich@suse.com>
1450 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1451 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1453 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1454 Likewise. Mark 256-bit entries invalid.
1456 2020-07-06 Jan Beulich <jbeulich@suse.com>
1458 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1459 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1460 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1461 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1462 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1463 PREFIX_EVEX_0F382B): Delete.
1464 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1465 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1466 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1467 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1468 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1470 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1471 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1472 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1473 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1475 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1476 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1477 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1478 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1479 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1480 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1481 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1482 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1483 PREFIX_EVEX_0F382B): Remove table entries.
1484 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1485 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1486 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1488 2020-07-06 Jan Beulich <jbeulich@suse.com>
1490 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1491 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1493 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1494 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1495 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1496 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1499 2020-07-06 Jan Beulich <jbeulich@suse.com>
1501 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1502 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1503 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1504 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1505 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1506 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1507 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1508 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1509 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1512 2020-07-06 Jan Beulich <jbeulich@suse.com>
1514 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1515 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1516 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1518 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1520 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1522 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1524 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1526 2020-07-06 Jan Beulich <jbeulich@suse.com>
1528 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1529 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1530 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1531 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1532 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1533 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1534 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1535 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1536 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1537 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1538 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1539 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1540 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1541 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1542 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1543 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1544 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1545 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1546 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1547 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1548 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1549 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1550 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1551 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1552 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1553 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1554 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1555 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1556 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1557 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1558 (prefix_table): Add EXxEVexR to FMA table entries.
1559 (OP_Rounding): Move abort() invocation.
1560 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1561 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1562 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1563 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1564 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1565 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1566 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1567 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1568 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1569 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1571 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1572 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1573 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1574 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1575 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1576 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1577 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1578 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1579 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1580 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1581 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1582 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1583 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1584 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1585 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1586 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1587 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1588 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1589 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1590 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1591 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1592 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1593 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1594 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1595 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1596 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1597 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1598 Delete table entries.
1599 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1600 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1601 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1604 2020-07-06 Jan Beulich <jbeulich@suse.com>
1606 * i386-dis.c (EXqScalarS): Delete.
1607 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1608 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1610 2020-07-06 Jan Beulich <jbeulich@suse.com>
1612 * i386-dis.c (safe-ctype.h): Include.
1613 (EXdScalar, EXqScalar): Delete.
1614 (d_scalar_mode, q_scalar_mode): Delete.
1615 (prefix_table, vex_len_table): Use EXxmm_md in place of
1616 EXdScalar and EXxmm_mq in place of EXqScalar.
1617 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1618 d_scalar_mode and q_scalar_mode.
1619 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1620 (vmovsd): Use EXxmm_mq.
1622 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1625 * arc-dis.c: Fix spelling mistake.
1626 * po/opcodes.pot: Regenerate.
1628 2020-07-06 Nick Clifton <nickc@redhat.com>
1630 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1631 * po/uk.po: Updated Ukranian translation.
1633 2020-07-04 Nick Clifton <nickc@redhat.com>
1635 * configure: Regenerate.
1636 * po/opcodes.pot: Regenerate.
1638 2020-07-04 Nick Clifton <nickc@redhat.com>
1640 Binutils 2.35 branch created.
1642 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1644 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1645 * i386-opc.h (VexSwapSources): New.
1646 (i386_opcode_modifier): Add vexswapsources.
1647 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1648 with two source operands swapped.
1649 * i386-tbl.h: Regenerated.
1651 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1653 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1654 unprivileged CSR can also be initialized.
1656 2020-06-29 Alan Modra <amodra@gmail.com>
1658 * arm-dis.c: Use C style comments.
1659 * cr16-opc.c: Likewise.
1660 * ft32-dis.c: Likewise.
1661 * moxie-opc.c: Likewise.
1662 * tic54x-dis.c: Likewise.
1663 * s12z-opc.c: Remove useless comment.
1664 * xgate-dis.c: Likewise.
1666 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1668 * i386-opc.tbl: Add a blank line.
1670 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1672 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1673 (VecSIB128): Renamed to ...
1675 (VecSIB256): Renamed to ...
1677 (VecSIB512): Renamed to ...
1679 (VecSIB): Renamed to ...
1681 (i386_opcode_modifier): Replace vecsib with sib.
1682 * i386-opc.tbl (VecSIB128): New.
1683 (VecSIB256): Likewise.
1684 (VecSIB512): Likewise.
1685 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1686 and VecSIB512, respectively.
1688 2020-06-26 Jan Beulich <jbeulich@suse.com>
1690 * i386-dis.c: Adjust description of I macro.
1691 (x86_64_table): Drop use of I.
1692 (float_mem): Replace use of I.
1693 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1695 2020-06-26 Jan Beulich <jbeulich@suse.com>
1697 * i386-dis.c: (print_insn): Avoid straight assignment to
1698 priv.orig_sizeflag when processing -M sub-options.
1700 2020-06-25 Jan Beulich <jbeulich@suse.com>
1702 * i386-dis.c: Adjust description of J macro.
1703 (dis386, x86_64_table, mod_table): Replace J.
1704 (putop): Remove handling of J.
1706 2020-06-25 Jan Beulich <jbeulich@suse.com>
1708 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1710 2020-06-25 Jan Beulich <jbeulich@suse.com>
1712 * i386-dis.c: Adjust description of "LQ" macro.
1713 (dis386_twobyte): Use LQ for sysret.
1714 (putop): Adjust handling of LQ.
1716 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1718 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1719 * riscv-dis.c: Include elfxx-riscv.h.
1721 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1723 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1725 2020-06-17 Lili Cui <lili.cui@intel.com>
1727 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1729 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1732 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1733 * i386-opc.tbl: Likewise.
1734 * i386-tbl.h: Regenerated.
1736 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1738 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1740 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1742 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1743 (SR_CORE): Likewise.
1744 (SR_FEAT): Likewise.
1746 (SR_V8_1): Likewise.
1747 (SR_V8_2): Likewise.
1748 (SR_V8_3): Likewise.
1749 (SR_V8_4): Likewise.
1752 (SR_SSBS): Likewise.
1754 (SR_ID_PFR2): Likewise.
1755 (SR_PROFILE): Likewise.
1756 (SR_MEMTAG): Likewise.
1757 (SR_SCXTNUM): Likewise.
1758 (aarch64_sys_regs): Refactor to store feature information in the table.
1759 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1760 that now describe their own features.
1761 (aarch64_pstatefield_supported_p): Likewise.
1763 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1765 * i386-dis.c (prefix_table): Fix a typo in comments.
1767 2020-06-09 Jan Beulich <jbeulich@suse.com>
1769 * i386-dis.c (rex_ignored): Delete.
1770 (ckprefix): Drop rex_ignored initialization.
1771 (get_valid_dis386): Drop setting of rex_ignored.
1772 (print_insn): Drop checking of rex_ignored. Don't record data
1773 size prefix as used with VEX-and-alike encodings.
1775 2020-06-09 Jan Beulich <jbeulich@suse.com>
1777 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1778 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1779 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1780 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1781 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1782 VEX_0F12, and VEX_0F16.
1783 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1784 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1785 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1786 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1787 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1788 MOD_VEX_0F16_PREFIX_2 entries.
1790 2020-06-09 Jan Beulich <jbeulich@suse.com>
1792 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1793 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1794 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1795 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1796 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1797 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1798 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1799 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1800 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1801 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1802 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1803 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1804 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1805 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1806 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1807 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1808 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1809 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1810 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1811 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1812 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1813 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1814 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1815 EVEX_W_0FC6_P_2): Delete.
1816 (print_insn): Add EVEX.W vs embedded prefix consistency check
1817 to prefix validation.
1818 * i386-dis-evex.h (evex_table): Don't further descend for
1819 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1820 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1822 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1823 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1824 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1825 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1826 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1827 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1828 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1829 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1830 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1831 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1832 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1833 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1834 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1835 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1836 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1837 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1838 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1839 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1840 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1841 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1842 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1843 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1844 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1845 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1846 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1847 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1848 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1850 2020-06-09 Jan Beulich <jbeulich@suse.com>
1852 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1853 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1854 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1856 (print_insn): Drop pointless check against bad_opcode. Split
1857 prefix validation into legacy and VEX-and-alike parts.
1858 (putop): Re-work 'X' macro handling.
1860 2020-06-09 Jan Beulich <jbeulich@suse.com>
1862 * i386-dis.c (MOD_0F51): Rename to ...
1863 (MOD_0F50): ... this.
1865 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1867 * arm-dis.c (arm_opcodes): Add dfb.
1868 (thumb32_opcodes): Add dfb.
1870 2020-06-08 Jan Beulich <jbeulich@suse.com>
1872 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1874 2020-06-06 Alan Modra <amodra@gmail.com>
1876 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1878 2020-06-05 Alan Modra <amodra@gmail.com>
1880 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1881 size is large enough.
1883 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1885 * disassemble.c (disassemble_init_for_target): Set endian_code for
1887 * bpf-desc.c: Regenerate.
1888 * bpf-opc.c: Likewise.
1889 * bpf-dis.c: Likewise.
1891 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1893 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1894 (cgen_put_insn_value): Likewise.
1895 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1896 * cgen-dis.in (print_insn): Likewise.
1897 * cgen-ibld.in (insert_1): Likewise.
1898 (insert_1): Likewise.
1899 (insert_insn_normal): Likewise.
1900 (extract_1): Likewise.
1901 * bpf-dis.c: Regenerate.
1902 * bpf-ibld.c: Likewise.
1903 * bpf-ibld.c: Likewise.
1904 * cgen-dis.in: Likewise.
1905 * cgen-ibld.in: Likewise.
1906 * cgen-opc.c: Likewise.
1907 * epiphany-dis.c: Likewise.
1908 * epiphany-ibld.c: Likewise.
1909 * fr30-dis.c: Likewise.
1910 * fr30-ibld.c: Likewise.
1911 * frv-dis.c: Likewise.
1912 * frv-ibld.c: Likewise.
1913 * ip2k-dis.c: Likewise.
1914 * ip2k-ibld.c: Likewise.
1915 * iq2000-dis.c: Likewise.
1916 * iq2000-ibld.c: Likewise.
1917 * lm32-dis.c: Likewise.
1918 * lm32-ibld.c: Likewise.
1919 * m32c-dis.c: Likewise.
1920 * m32c-ibld.c: Likewise.
1921 * m32r-dis.c: Likewise.
1922 * m32r-ibld.c: Likewise.
1923 * mep-dis.c: Likewise.
1924 * mep-ibld.c: Likewise.
1925 * mt-dis.c: Likewise.
1926 * mt-ibld.c: Likewise.
1927 * or1k-dis.c: Likewise.
1928 * or1k-ibld.c: Likewise.
1929 * xc16x-dis.c: Likewise.
1930 * xc16x-ibld.c: Likewise.
1931 * xstormy16-dis.c: Likewise.
1932 * xstormy16-ibld.c: Likewise.
1934 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1936 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1937 (print_insn_): Handle instruction endian.
1938 * bpf-dis.c: Regenerate.
1939 * bpf-desc.c: Regenerate.
1940 * epiphany-dis.c: Likewise.
1941 * epiphany-desc.c: Likewise.
1942 * fr30-dis.c: Likewise.
1943 * fr30-desc.c: Likewise.
1944 * frv-dis.c: Likewise.
1945 * frv-desc.c: Likewise.
1946 * ip2k-dis.c: Likewise.
1947 * ip2k-desc.c: Likewise.
1948 * iq2000-dis.c: Likewise.
1949 * iq2000-desc.c: Likewise.
1950 * lm32-dis.c: Likewise.
1951 * lm32-desc.c: Likewise.
1952 * m32c-dis.c: Likewise.
1953 * m32c-desc.c: Likewise.
1954 * m32r-dis.c: Likewise.
1955 * m32r-desc.c: Likewise.
1956 * mep-dis.c: Likewise.
1957 * mep-desc.c: Likewise.
1958 * mt-dis.c: Likewise.
1959 * mt-desc.c: Likewise.
1960 * or1k-dis.c: Likewise.
1961 * or1k-desc.c: Likewise.
1962 * xc16x-dis.c: Likewise.
1963 * xc16x-desc.c: Likewise.
1964 * xstormy16-dis.c: Likewise.
1965 * xstormy16-desc.c: Likewise.
1967 2020-06-03 Nick Clifton <nickc@redhat.com>
1969 * po/sr.po: Updated Serbian translation.
1971 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1973 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1974 (riscv_get_priv_spec_class): Likewise.
1976 2020-06-01 Alan Modra <amodra@gmail.com>
1978 * bpf-desc.c: Regenerate.
1980 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1981 David Faust <david.faust@oracle.com>
1983 * bpf-desc.c: Regenerate.
1984 * bpf-opc.h: Likewise.
1985 * bpf-opc.c: Likewise.
1986 * bpf-dis.c: Likewise.
1988 2020-05-28 Alan Modra <amodra@gmail.com>
1990 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1993 2020-05-28 Alan Modra <amodra@gmail.com>
1995 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1997 (print_insn_ns32k): Revert last change.
1999 2020-05-28 Nick Clifton <nickc@redhat.com>
2001 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
2004 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
2006 Fix extraction of signed constants in nios2 disassembler (again).
2008 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
2009 extractions of signed fields.
2011 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2013 * s390-opc.txt: Relocate vector load/store instructions with
2014 additional alignment parameter and change architecture level
2015 constraint from z14 to z13.
2017 2020-05-21 Alan Modra <amodra@gmail.com>
2019 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
2020 * sparc-dis.c: Likewise.
2021 * tic4x-dis.c: Likewise.
2022 * xtensa-dis.c: Likewise.
2023 * bpf-desc.c: Regenerate.
2024 * epiphany-desc.c: Regenerate.
2025 * fr30-desc.c: Regenerate.
2026 * frv-desc.c: Regenerate.
2027 * ip2k-desc.c: Regenerate.
2028 * iq2000-desc.c: Regenerate.
2029 * lm32-desc.c: Regenerate.
2030 * m32c-desc.c: Regenerate.
2031 * m32r-desc.c: Regenerate.
2032 * mep-asm.c: Regenerate.
2033 * mep-desc.c: Regenerate.
2034 * mt-desc.c: Regenerate.
2035 * or1k-desc.c: Regenerate.
2036 * xc16x-desc.c: Regenerate.
2037 * xstormy16-desc.c: Regenerate.
2039 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
2041 * riscv-opc.c (riscv_ext_version_table): The table used to store
2042 all information about the supported spec and the corresponding ISA
2043 versions. Currently, only Zicsr is supported to verify the
2044 correctness of Z sub extension settings. Others will be supported
2045 in the future patches.
2046 (struct isa_spec_t, isa_specs): List for all supported ISA spec
2047 classes and the corresponding strings.
2048 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
2049 spec class by giving a ISA spec string.
2050 * riscv-opc.c (struct priv_spec_t): New structure.
2051 (struct priv_spec_t priv_specs): List for all supported privilege spec
2052 classes and the corresponding strings.
2053 (riscv_get_priv_spec_class): New function. Get the corresponding
2054 privilege spec class by giving a spec string.
2055 (riscv_get_priv_spec_name): New function. Get the corresponding
2056 privilege spec string by giving a CSR version class.
2057 * riscv-dis.c: Updated since DECLARE_CSR is changed.
2058 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
2059 according to the chosen version. Build a hash table riscv_csr_hash to
2060 store the valid CSR for the chosen pirv verison. Dump the direct
2061 CSR address rather than it's name if it is invalid.
2062 (parse_riscv_dis_option_without_args): New function. Parse the options
2064 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
2065 parse the options without arguments first, and then handle the options
2066 with arguments. Add the new option -Mpriv-spec, which has argument.
2067 * riscv-dis.c (print_riscv_disassembler_options): Add description
2068 about the new OBJDUMP option.
2070 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
2072 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
2073 WC values on POWER10 sync, dcbf and wait instructions.
2074 (insert_pl, extract_pl): New functions.
2075 (L2OPT, LS, WC): Use insert_ls and extract_ls.
2076 (LS3): New , 3-bit L for sync.
2077 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
2078 (SC2, PL): New, 2-bit SC and PL for sync and wait.
2079 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
2080 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
2081 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
2082 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
2083 <wait>: Enable PL operand on POWER10.
2084 <dcbf>: Enable L3OPT operand on POWER10.
2085 <sync>: Enable SC2 operand on POWER10.
2087 2020-05-19 Stafford Horne <shorne@gmail.com>
2090 * or1k-asm.c: Regenerate.
2091 * or1k-desc.c: Regenerate.
2092 * or1k-desc.h: Regenerate.
2093 * or1k-dis.c: Regenerate.
2094 * or1k-ibld.c: Regenerate.
2095 * or1k-opc.c: Regenerate.
2096 * or1k-opc.h: Regenerate.
2097 * or1k-opinst.c: Regenerate.
2099 2020-05-11 Alan Modra <amodra@gmail.com>
2101 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
2104 2020-05-11 Alan Modra <amodra@gmail.com>
2106 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
2107 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
2109 2020-05-11 Alan Modra <amodra@gmail.com>
2111 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
2113 2020-05-11 Alan Modra <amodra@gmail.com>
2115 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
2116 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
2118 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2120 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
2123 2020-05-11 Alan Modra <amodra@gmail.com>
2125 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
2126 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
2127 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
2128 (prefix_opcodes): Add xxeval.
2130 2020-05-11 Alan Modra <amodra@gmail.com>
2132 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
2133 xxgenpcvwm, xxgenpcvdm.
2135 2020-05-11 Alan Modra <amodra@gmail.com>
2137 * ppc-opc.c (MP, VXVAM_MASK): Define.
2138 (VXVAPS_MASK): Use VXVA_MASK.
2139 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
2140 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
2141 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
2142 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
2144 2020-05-11 Alan Modra <amodra@gmail.com>
2145 Peter Bergner <bergner@linux.ibm.com>
2147 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2149 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2150 YMSK2, XA6a, XA6ap, XB6a entries.
2151 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2152 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2154 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2155 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2156 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2157 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2158 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2159 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2160 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2161 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2162 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2163 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2164 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2165 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2166 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2167 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2169 2020-05-11 Alan Modra <amodra@gmail.com>
2171 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2172 (insert_xts, extract_xts): New functions.
2173 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2174 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2175 (VXRC_MASK, VXSH_MASK): Define.
2176 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2177 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2178 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2179 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2180 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2181 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2182 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2184 2020-05-11 Alan Modra <amodra@gmail.com>
2186 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2187 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2188 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2189 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2190 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2192 2020-05-11 Alan Modra <amodra@gmail.com>
2194 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2195 (XTP, DQXP, DQXP_MASK): Define.
2196 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2197 (prefix_opcodes): Add plxvp and pstxvp.
2199 2020-05-11 Alan Modra <amodra@gmail.com>
2201 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2202 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2203 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2205 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2207 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2209 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2211 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2213 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2215 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2217 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2219 2020-05-11 Alan Modra <amodra@gmail.com>
2221 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2223 2020-05-11 Alan Modra <amodra@gmail.com>
2225 * ppc-dis.c (ppc_opts): Add "power10" entry.
2226 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2227 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2229 2020-05-11 Nick Clifton <nickc@redhat.com>
2231 * po/fr.po: Updated French translation.
2233 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2235 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2236 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2237 (operand_general_constraint_met_p): validate
2238 AARCH64_OPND_UNDEFINED.
2239 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2241 * aarch64-asm-2.c: Regenerated.
2242 * aarch64-dis-2.c: Regenerated.
2243 * aarch64-opc-2.c: Regenerated.
2245 2020-04-29 Nick Clifton <nickc@redhat.com>
2248 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2251 2020-04-29 Nick Clifton <nickc@redhat.com>
2253 * po/sv.po: Updated Swedish translation.
2255 2020-04-29 Nick Clifton <nickc@redhat.com>
2258 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2259 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2260 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2263 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2266 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2267 cmpi only on m68020up and cpu32.
2269 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2271 * aarch64-asm.c (aarch64_ins_none): New.
2272 * aarch64-asm.h (ins_none): New declaration.
2273 * aarch64-dis.c (aarch64_ext_none): New.
2274 * aarch64-dis.h (ext_none): New declaration.
2275 * aarch64-opc.c (aarch64_print_operand): Update case for
2276 AARCH64_OPND_BARRIER_PSB.
2277 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2278 (AARCH64_OPERANDS): Update inserter/extracter for
2279 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2280 * aarch64-asm-2.c: Regenerated.
2281 * aarch64-dis-2.c: Regenerated.
2282 * aarch64-opc-2.c: Regenerated.
2284 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2286 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2287 (aarch64_feature_ras, RAS): Likewise.
2288 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2289 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2290 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2291 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2292 * aarch64-asm-2.c: Regenerated.
2293 * aarch64-dis-2.c: Regenerated.
2294 * aarch64-opc-2.c: Regenerated.
2296 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2298 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2299 (print_insn_neon): Support disassembly of conditional
2302 2020-02-16 David Faust <david.faust@oracle.com>
2304 * bpf-desc.c: Regenerate.
2305 * bpf-desc.h: Likewise.
2306 * bpf-opc.c: Regenerate.
2307 * bpf-opc.h: Likewise.
2309 2020-04-07 Lili Cui <lili.cui@intel.com>
2311 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2312 (prefix_table): New instructions (see prefixes above).
2313 (rm_table): Likewise
2314 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2315 CPU_ANY_TSXLDTRK_FLAGS.
2316 (cpu_flags): Add CpuTSXLDTRK.
2317 * i386-opc.h (enum): Add CpuTSXLDTRK.
2318 (i386_cpu_flags): Add cputsxldtrk.
2319 * i386-opc.tbl: Add XSUSPLDTRK insns.
2320 * i386-init.h: Regenerate.
2321 * i386-tbl.h: Likewise.
2323 2020-04-02 Lili Cui <lili.cui@intel.com>
2325 * i386-dis.c (prefix_table): New instructions serialize.
2326 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2327 CPU_ANY_SERIALIZE_FLAGS.
2328 (cpu_flags): Add CpuSERIALIZE.
2329 * i386-opc.h (enum): Add CpuSERIALIZE.
2330 (i386_cpu_flags): Add cpuserialize.
2331 * i386-opc.tbl: Add SERIALIZE insns.
2332 * i386-init.h: Regenerate.
2333 * i386-tbl.h: Likewise.
2335 2020-03-26 Alan Modra <amodra@gmail.com>
2337 * disassemble.h (opcodes_assert): Declare.
2338 (OPCODES_ASSERT): Define.
2339 * disassemble.c: Don't include assert.h. Include opintl.h.
2340 (opcodes_assert): New function.
2341 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2342 (bfd_h8_disassemble): Reduce size of data array. Correctly
2343 calculate maxlen. Omit insn decoding when insn length exceeds
2344 maxlen. Exit from nibble loop when looking for E, before
2345 accessing next data byte. Move processing of E outside loop.
2346 Replace tests of maxlen in loop with assertions.
2348 2020-03-26 Alan Modra <amodra@gmail.com>
2350 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2352 2020-03-25 Alan Modra <amodra@gmail.com>
2354 * z80-dis.c (suffix): Init mybuf.
2356 2020-03-22 Alan Modra <amodra@gmail.com>
2358 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2359 successflly read from section.
2361 2020-03-22 Alan Modra <amodra@gmail.com>
2363 * arc-dis.c (find_format): Use ISO C string concatenation rather
2364 than line continuation within a string. Don't access needs_limm
2365 before testing opcode != NULL.
2367 2020-03-22 Alan Modra <amodra@gmail.com>
2369 * ns32k-dis.c (print_insn_arg): Update comment.
2370 (print_insn_ns32k): Reduce size of index_offset array, and
2371 initialize, passing -1 to print_insn_arg for args that are not
2372 an index. Don't exit arg loop early. Abort on bad arg number.
2374 2020-03-22 Alan Modra <amodra@gmail.com>
2376 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2377 * s12z-opc.c: Formatting.
2378 (operands_f): Return an int.
2379 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2380 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2381 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2382 (exg_sex_discrim): Likewise.
2383 (create_immediate_operand, create_bitfield_operand),
2384 (create_register_operand_with_size, create_register_all_operand),
2385 (create_register_all16_operand, create_simple_memory_operand),
2386 (create_memory_operand, create_memory_auto_operand): Don't
2387 segfault on malloc failure.
2388 (z_ext24_decode): Return an int status, negative on fail, zero
2390 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2391 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2392 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2393 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2394 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2395 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2396 (loop_primitive_decode, shift_decode, psh_pul_decode),
2397 (bit_field_decode): Similarly.
2398 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2399 to return value, update callers.
2400 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2401 Don't segfault on NULL operand.
2402 (decode_operation): Return OP_INVALID on first fail.
2403 (decode_s12z): Check all reads, returning -1 on fail.
2405 2020-03-20 Alan Modra <amodra@gmail.com>
2407 * metag-dis.c (print_insn_metag): Don't ignore status from
2410 2020-03-20 Alan Modra <amodra@gmail.com>
2412 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2413 Initialize parts of buffer not written when handling a possible
2414 2-byte insn at end of section. Don't attempt decoding of such
2415 an insn by the 4-byte machinery.
2417 2020-03-20 Alan Modra <amodra@gmail.com>
2419 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2420 partially filled buffer. Prevent lookup of 4-byte insns when
2421 only VLE 2-byte insns are possible due to section size. Print
2422 ".word" rather than ".long" for 2-byte leftovers.
2424 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2427 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2429 2020-03-13 Jan Beulich <jbeulich@suse.com>
2431 * i386-dis.c (X86_64_0D): Rename to ...
2432 (X86_64_0E): ... this.
2434 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2436 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2437 * Makefile.in: Regenerated.
2439 2020-03-09 Jan Beulich <jbeulich@suse.com>
2441 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2443 * i386-tbl.h: Re-generate.
2445 2020-03-09 Jan Beulich <jbeulich@suse.com>
2447 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2448 vprot*, vpsha*, and vpshl*.
2449 * i386-tbl.h: Re-generate.
2451 2020-03-09 Jan Beulich <jbeulich@suse.com>
2453 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2454 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2455 * i386-tbl.h: Re-generate.
2457 2020-03-09 Jan Beulich <jbeulich@suse.com>
2459 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2460 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2461 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2462 * i386-tbl.h: Re-generate.
2464 2020-03-09 Jan Beulich <jbeulich@suse.com>
2466 * i386-gen.c (struct template_arg, struct template_instance,
2467 struct template_param, struct template, templates,
2468 parse_template, expand_templates): New.
2469 (process_i386_opcodes): Various local variables moved to
2470 expand_templates. Call parse_template and expand_templates.
2471 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2472 * i386-tbl.h: Re-generate.
2474 2020-03-06 Jan Beulich <jbeulich@suse.com>
2476 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2477 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2478 register and memory source templates. Replace VexW= by VexW*
2480 * i386-tbl.h: Re-generate.
2482 2020-03-06 Jan Beulich <jbeulich@suse.com>
2484 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2485 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2486 * i386-tbl.h: Re-generate.
2488 2020-03-06 Jan Beulich <jbeulich@suse.com>
2490 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2491 * i386-tbl.h: Re-generate.
2493 2020-03-06 Jan Beulich <jbeulich@suse.com>
2495 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2496 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2497 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2498 VexW0 on SSE2AVX variants.
2499 (vmovq): Drop NoRex64 from XMM/XMM variants.
2500 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2501 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2502 applicable use VexW0.
2503 * i386-tbl.h: Re-generate.
2505 2020-03-06 Jan Beulich <jbeulich@suse.com>
2507 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2508 * i386-opc.h (Rex64): Delete.
2509 (struct i386_opcode_modifier): Remove rex64 field.
2510 * i386-opc.tbl (crc32): Drop Rex64.
2511 Replace Rex64 with Size64 everywhere else.
2512 * i386-tbl.h: Re-generate.
2514 2020-03-06 Jan Beulich <jbeulich@suse.com>
2516 * i386-dis.c (OP_E_memory): Exclude recording of used address
2517 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2518 addressed memory operands for MPX insns.
2520 2020-03-06 Jan Beulich <jbeulich@suse.com>
2522 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2523 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2524 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2525 (ptwrite): Split into non-64-bit and 64-bit forms.
2526 * i386-tbl.h: Re-generate.
2528 2020-03-06 Jan Beulich <jbeulich@suse.com>
2530 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2532 * i386-tbl.h: Re-generate.
2534 2020-03-04 Jan Beulich <jbeulich@suse.com>
2536 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2537 (prefix_table): Move vmmcall here. Add vmgexit.
2538 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2539 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2540 (cpu_flags): Add CpuSEV_ES entry.
2541 * i386-opc.h (CpuSEV_ES): New.
2542 (union i386_cpu_flags): Add cpusev_es field.
2543 * i386-opc.tbl (vmgexit): New.
2544 * i386-init.h, i386-tbl.h: Re-generate.
2546 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2548 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2550 * i386-opc.h (IGNORESIZE): New.
2551 (DEFAULTSIZE): Likewise.
2552 (IgnoreSize): Removed.
2553 (DefaultSize): Likewise.
2554 (MnemonicSize): New.
2555 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2557 * i386-opc.tbl (IgnoreSize): New.
2558 (DefaultSize): Likewise.
2559 * i386-tbl.h: Regenerated.
2561 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2564 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2567 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2570 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2571 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2572 * i386-tbl.h: Regenerated.
2574 2020-02-26 Alan Modra <amodra@gmail.com>
2576 * aarch64-asm.c: Indent labels correctly.
2577 * aarch64-dis.c: Likewise.
2578 * aarch64-gen.c: Likewise.
2579 * aarch64-opc.c: Likewise.
2580 * alpha-dis.c: Likewise.
2581 * i386-dis.c: Likewise.
2582 * nds32-asm.c: Likewise.
2583 * nfp-dis.c: Likewise.
2584 * visium-dis.c: Likewise.
2586 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2588 * arc-regs.h (int_vector_base): Make it available for all ARC
2591 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2593 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2596 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2598 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2599 c.mv/c.li if rs1 is zero.
2601 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2603 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2604 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2606 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2607 * i386-opc.h (CpuABM): Removed.
2609 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2610 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2611 popcnt. Remove CpuABM from lzcnt.
2612 * i386-init.h: Regenerated.
2613 * i386-tbl.h: Likewise.
2615 2020-02-17 Jan Beulich <jbeulich@suse.com>
2617 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2618 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2619 VexW1 instead of open-coding them.
2620 * i386-tbl.h: Re-generate.
2622 2020-02-17 Jan Beulich <jbeulich@suse.com>
2624 * i386-opc.tbl (AddrPrefixOpReg): Define.
2625 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2626 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2627 templates. Drop NoRex64.
2628 * i386-tbl.h: Re-generate.
2630 2020-02-17 Jan Beulich <jbeulich@suse.com>
2633 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2634 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2635 into Intel syntax instance (with Unpsecified) and AT&T one
2637 (vcvtneps2bf16): Likewise, along with folding the two so far
2639 * i386-tbl.h: Re-generate.
2641 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2643 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2644 CPU_ANY_SSE4A_FLAGS.
2646 2020-02-17 Alan Modra <amodra@gmail.com>
2648 * i386-gen.c (cpu_flag_init): Correct last change.
2650 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2652 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2655 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2657 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2660 2020-02-14 Jan Beulich <jbeulich@suse.com>
2663 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2664 destination for Cpu64-only variant.
2665 (movzx): Fold patterns.
2666 * i386-tbl.h: Re-generate.
2668 2020-02-13 Jan Beulich <jbeulich@suse.com>
2670 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2671 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2672 CPU_ANY_SSE4_FLAGS entry.
2673 * i386-init.h: Re-generate.
2675 2020-02-12 Jan Beulich <jbeulich@suse.com>
2677 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2678 with Unspecified, making the present one AT&T syntax only.
2679 * i386-tbl.h: Re-generate.
2681 2020-02-12 Jan Beulich <jbeulich@suse.com>
2683 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2684 * i386-tbl.h: Re-generate.
2686 2020-02-12 Jan Beulich <jbeulich@suse.com>
2689 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2690 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2691 Amd64 and Intel64 templates.
2692 (call, jmp): Likewise for far indirect variants. Dro
2694 * i386-tbl.h: Re-generate.
2696 2020-02-11 Jan Beulich <jbeulich@suse.com>
2698 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2699 * i386-opc.h (ShortForm): Delete.
2700 (struct i386_opcode_modifier): Remove shortform field.
2701 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2702 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2703 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2704 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2706 * i386-tbl.h: Re-generate.
2708 2020-02-11 Jan Beulich <jbeulich@suse.com>
2710 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2711 fucompi): Drop ShortForm from operand-less templates.
2712 * i386-tbl.h: Re-generate.
2714 2020-02-11 Alan Modra <amodra@gmail.com>
2716 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2717 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2718 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2719 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2720 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2722 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2724 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2725 (cde_opcodes): Add VCX* instructions.
2727 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2728 Matthew Malcomson <matthew.malcomson@arm.com>
2730 * arm-dis.c (struct cdeopcode32): New.
2731 (CDE_OPCODE): New macro.
2732 (cde_opcodes): New disassembly table.
2733 (regnames): New option to table.
2734 (cde_coprocs): New global variable.
2735 (print_insn_cde): New
2736 (print_insn_thumb32): Use print_insn_cde.
2737 (parse_arm_disassembler_options): Parse coprocN args.
2739 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2742 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2744 * i386-opc.h (AMD64): Removed.
2745 (Intel64): Likewose.
2747 (INTEL64): Likewise.
2748 (INTEL64ONLY): Likewise.
2749 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2750 * i386-opc.tbl (Amd64): New.
2751 (Intel64): Likewise.
2752 (Intel64Only): Likewise.
2753 Replace AMD64 with Amd64. Update sysenter/sysenter with
2754 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2755 * i386-tbl.h: Regenerated.
2757 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2760 * z80-dis.c: Add support for GBZ80 opcodes.
2762 2020-02-04 Alan Modra <amodra@gmail.com>
2764 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2766 2020-02-03 Alan Modra <amodra@gmail.com>
2768 * m32c-ibld.c: Regenerate.
2770 2020-02-01 Alan Modra <amodra@gmail.com>
2772 * frv-ibld.c: Regenerate.
2774 2020-01-31 Jan Beulich <jbeulich@suse.com>
2776 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2777 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2778 (OP_E_memory): Replace xmm_mdq_mode case label by
2779 vex_scalar_w_dq_mode one.
2780 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2782 2020-01-31 Jan Beulich <jbeulich@suse.com>
2784 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2785 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2786 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2787 (intel_operand_size): Drop vex_w_dq_mode case label.
2789 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2791 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2792 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2794 2020-01-30 Alan Modra <amodra@gmail.com>
2796 * m32c-ibld.c: Regenerate.
2798 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2800 * bpf-opc.c: Regenerate.
2802 2020-01-30 Jan Beulich <jbeulich@suse.com>
2804 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2805 (dis386): Use them to replace C2/C3 table entries.
2806 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2807 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2808 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2809 * i386-tbl.h: Re-generate.
2811 2020-01-30 Jan Beulich <jbeulich@suse.com>
2813 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2815 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2817 * i386-tbl.h: Re-generate.
2819 2020-01-30 Alan Modra <amodra@gmail.com>
2821 * tic4x-dis.c (tic4x_dp): Make unsigned.
2823 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2824 Jan Beulich <jbeulich@suse.com>
2827 * i386-dis.c (MOVSXD_Fixup): New function.
2828 (movsxd_mode): New enum.
2829 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2830 (intel_operand_size): Handle movsxd_mode.
2831 (OP_E_register): Likewise.
2833 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2834 register on movsxd. Add movsxd with 16-bit destination register
2835 for AMD64 and Intel64 ISAs.
2836 * i386-tbl.h: Regenerated.
2838 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2841 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2842 * aarch64-asm-2.c: Regenerate
2843 * aarch64-dis-2.c: Likewise.
2844 * aarch64-opc-2.c: Likewise.
2846 2020-01-21 Jan Beulich <jbeulich@suse.com>
2848 * i386-opc.tbl (sysret): Drop DefaultSize.
2849 * i386-tbl.h: Re-generate.
2851 2020-01-21 Jan Beulich <jbeulich@suse.com>
2853 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2855 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2856 * i386-tbl.h: Re-generate.
2858 2020-01-20 Nick Clifton <nickc@redhat.com>
2860 * po/de.po: Updated German translation.
2861 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2862 * po/uk.po: Updated Ukranian translation.
2864 2020-01-20 Alan Modra <amodra@gmail.com>
2866 * hppa-dis.c (fput_const): Remove useless cast.
2868 2020-01-20 Alan Modra <amodra@gmail.com>
2870 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2872 2020-01-18 Nick Clifton <nickc@redhat.com>
2874 * configure: Regenerate.
2875 * po/opcodes.pot: Regenerate.
2877 2020-01-18 Nick Clifton <nickc@redhat.com>
2879 Binutils 2.34 branch created.
2881 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2883 * opintl.h: Fix spelling error (seperate).
2885 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2887 * i386-opc.tbl: Add {vex} pseudo prefix.
2888 * i386-tbl.h: Regenerated.
2890 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2893 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2894 (neon_opcodes): Likewise.
2895 (select_arm_features): Make sure we enable MVE bits when selecting
2896 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2899 2020-01-16 Jan Beulich <jbeulich@suse.com>
2901 * i386-opc.tbl: Drop stale comment from XOP section.
2903 2020-01-16 Jan Beulich <jbeulich@suse.com>
2905 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2906 (extractps): Add VexWIG to SSE2AVX forms.
2907 * i386-tbl.h: Re-generate.
2909 2020-01-16 Jan Beulich <jbeulich@suse.com>
2911 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2912 Size64 from and use VexW1 on SSE2AVX forms.
2913 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2914 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2915 * i386-tbl.h: Re-generate.
2917 2020-01-15 Alan Modra <amodra@gmail.com>
2919 * tic4x-dis.c (tic4x_version): Make unsigned long.
2920 (optab, optab_special, registernames): New file scope vars.
2921 (tic4x_print_register): Set up registernames rather than
2922 malloc'd registertable.
2923 (tic4x_disassemble): Delete optable and optable_special. Use
2924 optab and optab_special instead. Throw away old optab,
2925 optab_special and registernames when info->mach changes.
2927 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2930 * z80-dis.c (suffix): Use .db instruction to generate double
2933 2020-01-14 Alan Modra <amodra@gmail.com>
2935 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2936 values to unsigned before shifting.
2938 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2940 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2942 (print_insn_thumb16, print_insn_thumb32): Likewise.
2943 (print_insn): Initialize the insn info.
2944 * i386-dis.c (print_insn): Initialize the insn info fields, and
2947 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2949 * arc-opc.c (C_NE): Make it required.
2951 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2953 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2954 reserved register name.
2956 2020-01-13 Alan Modra <amodra@gmail.com>
2958 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2959 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2961 2020-01-13 Alan Modra <amodra@gmail.com>
2963 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2964 result of wasm_read_leb128 in a uint64_t and check that bits
2965 are not lost when copying to other locals. Use uint32_t for
2966 most locals. Use PRId64 when printing int64_t.
2968 2020-01-13 Alan Modra <amodra@gmail.com>
2970 * score-dis.c: Formatting.
2971 * score7-dis.c: Formatting.
2973 2020-01-13 Alan Modra <amodra@gmail.com>
2975 * score-dis.c (print_insn_score48): Use unsigned variables for
2976 unsigned values. Don't left shift negative values.
2977 (print_insn_score32): Likewise.
2978 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2980 2020-01-13 Alan Modra <amodra@gmail.com>
2982 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2984 2020-01-13 Alan Modra <amodra@gmail.com>
2986 * fr30-ibld.c: Regenerate.
2988 2020-01-13 Alan Modra <amodra@gmail.com>
2990 * xgate-dis.c (print_insn): Don't left shift signed value.
2991 (ripBits): Formatting, use 1u.
2993 2020-01-10 Alan Modra <amodra@gmail.com>
2995 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2996 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2998 2020-01-10 Alan Modra <amodra@gmail.com>
3000 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
3001 and XRREG value earlier to avoid a shift with negative exponent.
3002 * m10200-dis.c (disassemble): Similarly.
3004 2020-01-09 Nick Clifton <nickc@redhat.com>
3007 * z80-dis.c (ld_ii_ii): Use correct cast.
3009 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
3012 * z80-dis.c (ld_ii_ii): Use character constant when checking
3015 2020-01-09 Jan Beulich <jbeulich@suse.com>
3017 * i386-dis.c (SEP_Fixup): New.
3019 (dis386_twobyte): Use it for sysenter/sysexit.
3020 (enum x86_64_isa): Change amd64 enumerator to value 1.
3021 (OP_J): Compare isa64 against intel64 instead of amd64.
3022 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
3024 * i386-tbl.h: Re-generate.
3026 2020-01-08 Alan Modra <amodra@gmail.com>
3028 * z8k-dis.c: Include libiberty.h
3029 (instr_data_s): Make max_fetched unsigned.
3030 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
3031 Don't exceed byte_info bounds.
3032 (output_instr): Make num_bytes unsigned.
3033 (unpack_instr): Likewise for nibl_count and loop.
3034 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
3036 * z8k-opc.h: Regenerate.
3038 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
3040 * arc-tbl.h (llock): Use 'LLOCK' as class.
3042 (scond): Use 'SCOND' as class.
3044 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
3047 2020-01-06 Alan Modra <amodra@gmail.com>
3049 * m32c-ibld.c: Regenerate.
3051 2020-01-06 Alan Modra <amodra@gmail.com>
3054 * z80-dis.c (suffix): Don't use a local struct buffer copy.
3055 Peek at next byte to prevent recursion on repeated prefix bytes.
3056 Ensure uninitialised "mybuf" is not accessed.
3057 (print_insn_z80): Don't zero n_fetch and n_used here,..
3058 (print_insn_z80_buf): ..do it here instead.
3060 2020-01-04 Alan Modra <amodra@gmail.com>
3062 * m32r-ibld.c: Regenerate.
3064 2020-01-04 Alan Modra <amodra@gmail.com>
3066 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
3068 2020-01-04 Alan Modra <amodra@gmail.com>
3070 * crx-dis.c (match_opcode): Avoid shift left of signed value.
3072 2020-01-04 Alan Modra <amodra@gmail.com>
3074 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
3076 2020-01-03 Jan Beulich <jbeulich@suse.com>
3078 * aarch64-tbl.h (aarch64_opcode_table): Use
3079 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
3081 2020-01-03 Jan Beulich <jbeulich@suse.com>
3083 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
3084 forms of SUDOT and USDOT.
3086 2020-01-03 Jan Beulich <jbeulich@suse.com>
3088 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
3090 * aarch64-dis-2.c: Re-generate.
3092 2020-01-03 Jan Beulich <jbeulich@suse.com>
3094 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
3096 * aarch64-dis-2.c: Re-generate.
3098 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
3100 * z80-dis.c: Add support for eZ80 and Z80 instructions.
3102 2020-01-01 Alan Modra <amodra@gmail.com>
3104 Update year range in copyright notice of all files.
3106 For older changes see ChangeLog-2019
3108 Copyright (C) 2020 Free Software Foundation, Inc.
3110 Copying and distribution of this file, with or without modification,
3111 are permitted in any medium without royalty provided the copyright
3112 notice and this notice are preserved.
3118 version-control: never
projects / thirdparty / binutils-gdb.git / blob