opcodes/ChangeLog

   1 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
   2
   3         * arc-opc.c (extract_w6): Fix extending the sign.
   4
   5 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
   6
   7         * arc-tbl.h (vewt): Allow it for ARC EM family.
   8
   9 2018-07-23  Alan Modra  <amodra@gmail.com>
  10
  11         PR 23419
  12         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
  13         opcode variants for mtspr/mfspr encodings.
  14
  15 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
  16             Maciej W. Rozycki  <macro@mips.com>
  17
  18         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
  19         loongson3a descriptors.
  20         (parse_mips_ase_option): Handle -M loongson-mmi option.
  21         (print_mips_disassembler_options): Document -M loongson-mmi.
  22         * mips-opc.c (LMMI): New macro.
  23         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
  24         instructions.
  25
  26 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  29         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
  30         IgnoreSize and [XYZ]MMword where applicable.
  31         * i386-tbl.h: Re-generate.
  32
  33 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
  36         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
  37         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
  38         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
  39         * i386-tbl.h: Re-generate.
  40
  41 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
  44         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
  45         VPCLMULQDQ templates into their respective AVX512VL counterparts
  46         where possible, using Disp8ShiftVL and CheckRegSize instead of
  47         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
  48         * i386-tbl.h: Re-generate.
  49
  50 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-opc.tbl: Fold AVX512DQ templates into their respective
  53         AVX512VL counterparts where possible, using Disp8ShiftVL and
  54         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  55         IgnoreSize) as appropriate.
  56         * i386-tbl.h: Re-generate.
  57
  58 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-opc.tbl: Fold AVX512BW templates into their respective
  61         AVX512VL counterparts where possible, using Disp8ShiftVL and
  62         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  63         IgnoreSize) as appropriate.
  64         * i386-tbl.h: Re-generate.
  65
  66 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.tbl: Fold AVX512CD templates into their respective
  69         AVX512VL counterparts where possible, using Disp8ShiftVL and
  70         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  71         IgnoreSize) as appropriate.
  72         * i386-tbl.h: Re-generate.
  73
  74 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-opc.h (DISP8_SHIFT_VL): New.
  77         * i386-opc.tbl (Disp8ShiftVL):  Define.
  78         (various): Fold AVX512VL templates into their respective
  79         AVX512F counterparts where possible, using Disp8ShiftVL and
  80         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  81         IgnoreSize) as appropriate.
  82         * i386-tbl.h: Re-generate.
  83
  84 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  85
  86         * Makefile.am: Change dependencies and rule for
  87         $(srcdir)/i386-init.h.
  88         * Makefile.in: Re-generate.
  89         * i386-gen.c (process_i386_opcodes): New local variable
  90         "marker". Drop opening of input file. Recognize marker and line
  91         number directives.
  92         * i386-opc.tbl (OPCODE_I386_H): Define.
  93         (i386-opc.h): Include it.
  94         (None): Undefine.
  95
  96 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         PR gas/23418
  99         * i386-opc.h (Byte): Update comments.
 100         (Word): Likewise.
 101         (Dword): Likewise.
 102         (Fword): Likewise.
 103         (Qword): Likewise.
 104         (Tbyte): Likewise.
 105         (Xmmword): Likewise.
 106         (Ymmword): Likewise.
 107         (Zmmword): Likewise.
 108         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 109         vcvttps2uqq.
 110         * i386-tbl.h: Regenerated.
 111
 112 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 113
 114         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 115         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 116         * aarch64-asm-2.c: Regenerate.
 117         * aarch64-dis-2.c: Regenerate.
 118         * aarch64-opc-2.c: Regenerate.
 119
 120 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 121
 122         PR binutils/23192
 123         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 124         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 125         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 126         sqdmulh, sqrdmulh): Use Em16.
 127
 128 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 129
 130         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 131         csdb together with them.
 132         (thumb32_opcodes): Likewise.
 133
 134 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 135
 136         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 137         requiring 32-bit registers as operands 2 and 3. Improve
 138         comments.
 139         (mwait, mwaitx): Fold templates. Improve comments.
 140         OPERAND_TYPE_INOUTPORTREG.
 141         * i386-tbl.h: Re-generate.
 142
 143 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-gen.c (operand_type_init): Remove
 146         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 147         OPERAND_TYPE_INOUTPORTREG.
 148         * i386-init.h: Re-generate.
 149
 150 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 153         (wrssq, wrussq): Add Qword.
 154         * i386-tbl.h: Re-generate.
 155
 156 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-opc.h: Rename OTMax to OTNum.
 159         (OTNumOfUints): Adjust calculation.
 160         (OTUnused): Directly alias to OTNum.
 161
 162 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 163
 164         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 165         `reg_xys'.
 166         (lea_reg_xys): Likewise.
 167         (print_insn_loop_primitive): Rename `reg' local variable to
 168         `reg_dxy'.
 169
 170 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 171
 172         PR binutils/23242
 173         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 174
 175 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 176
 177         PR binutils/23369
 178         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 179         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 180
 181 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 182
 183         PR tdep/8282
 184         * mips-dis.c (mips_option_arg_t): New enumeration.
 185         (mips_options): New variable.
 186         (disassembler_options_mips): New function.
 187         (print_mips_disassembler_options): Reimplement in terms of
 188         `disassembler_options_mips'.
 189         * arm-dis.c (disassembler_options_arm): Adapt to using the
 190         `disasm_options_and_args_t' structure.
 191         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 192         * s390-dis.c (disassembler_options_s390): Likewise.
 193
 194 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 195
 196         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 197         expected result.
 198         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 199         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 200         * testsuite/ld-arm/tls-longplt.d: Likewise.
 201
 202 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 203
 204         PR binutils/23192
 205         * aarch64-asm-2.c: Regenerate.
 206         * aarch64-dis-2.c: Likewise.
 207         * aarch64-opc-2.c: Likewise.
 208         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 209         * aarch64-opc.c (operand_general_constraint_met_p,
 210         aarch64_print_operand): Likewise.
 211         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 212         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 213         fmlal2, fmlsl2.
 214         (AARCH64_OPERANDS): Add Em2.
 215
 216 2018-06-26  Nick Clifton  <nickc@redhat.com>
 217
 218         * po/uk.po: Updated Ukranian translation.
 219         * po/de.po: Updated German translation.
 220         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 221
 222 2018-06-26  Nick Clifton  <nickc@redhat.com>
 223
 224         * nfp-dis.c: Fix spelling mistake.
 225
 226 2018-06-24  Nick Clifton  <nickc@redhat.com>
 227
 228         * configure: Regenerate.
 229         * po/opcodes.pot: Regenerate.
 230
 231 2018-06-24  Nick Clifton  <nickc@redhat.com>
 232
 233         2.31 branch created.
 234
 235 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 236
 237         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 238         * aarch64-asm-2.c: Regenerate.
 239         * aarch64-dis-2.c: Likewise.
 240
 241 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 242
 243         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 244         `-M ginv' option description.
 245
 246 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 247
 248         PR gas/23305
 249         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 250         la and lla.
 251
 252 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 253
 254         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 255         * configure.ac: Remove AC_PREREQ.
 256         * Makefile.in: Re-generate.
 257         * aclocal.m4: Re-generate.
 258         * configure: Re-generate.
 259
 260 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 261
 262         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 263         mips64r6 descriptors.
 264         (parse_mips_ase_option): Handle -Mginv option.
 265         (print_mips_disassembler_options): Document -Mginv.
 266         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 267         (GINV): New macro.
 268         (mips_opcodes): Define ginvi and ginvt.
 269
 270 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 271             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 272
 273         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 274         * mips-opc.c (CRC, CRC64): New macros.
 275         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 276         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 277         crc32cd for CRC64.
 278
 279 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 280
 281         PR 20319
 282         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 283         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 284
 285 2018-06-06  Alan Modra  <amodra@gmail.com>
 286
 287         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 288         setjmp.  Move init for some other vars later too.
 289
 290 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 291
 292         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 293         (dis_private): Add new fields for property section tracking.
 294         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 295         (xtensa_instruction_fits): New functions.
 296         (fetch_data): Bump minimal fetch size to 4.
 297         (print_insn_xtensa): Make struct dis_private static.
 298         Load and prepare property table on section change.
 299         Don't disassemble literals. Don't disassemble instructions that
 300         cross property table boundaries.
 301
 302 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         * configure: Regenerated.
 305
 306 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 307
 308         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 309         * i386-tbl.h: Re-generate.
 310
 311 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 312
 313         * i386-opc.tbl (sldt, str): Add NoRex64.
 314         * i386-tbl.h: Re-generate.
 315
 316 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-opc.tbl (invpcid): Add Oword.
 319         * i386-tbl.h: Re-generate.
 320
 321 2018-06-01  Alan Modra  <amodra@gmail.com>
 322
 323         * sysdep.h (_bfd_error_handler): Don't declare.
 324         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 325         * rl78-decode.opc: Likewise.
 326         * msp430-decode.c: Regenerate.
 327         * rl78-decode.c: Regenerate.
 328
 329 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 330
 331         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 332         * i386-init.h : Regenerated.
 333
 334 2018-05-25  Alan Modra  <amodra@gmail.com>
 335
 336         * Makefile.in: Regenerate.
 337         * po/POTFILES.in: Regenerate.
 338
 339 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 340
 341         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 342         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 343         (insert_bab, extract_bab, insert_btab, extract_btab,
 344         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 345         (BAT, BBA VBA RBS XB6S): Delete macros.
 346         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 347         (BB, BD, RBX, XC6): Update for new macros.
 348         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 349         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 350         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 351         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 352
 353 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 354
 355         * Makefile.am: Add support for s12z architecture.
 356         * configure.ac: Likewise.
 357         * disassemble.c: Likewise.
 358         * disassemble.h: Likewise.
 359         * Makefile.in: Regenerate.
 360         * configure: Regenerate.
 361         * s12z-dis.c: New file.
 362         * s12z.h: New file.
 363
 364 2018-05-18  Alan Modra  <amodra@gmail.com>
 365
 366         * nfp-dis.c: Don't #include libbfd.h.
 367         (init_nfp3200_priv): Use bfd_get_section_contents.
 368         (nit_nfp6000_mecsr_sec): Likewise.
 369
 370 2018-05-17  Nick Clifton  <nickc@redhat.com>
 371
 372         * po/zh_CN.po: Updated simplified Chinese translation.
 373
 374 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 375
 376         PR binutils/23109
 377         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 378         * aarch64-dis-2.c: Regenerate.
 379
 380 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 381
 382         PR binutils/21446
 383         * aarch64-asm.c (opintl.h): Include.
 384         (aarch64_ins_sysreg): Enforce read/write constraints.
 385         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 386         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 387         (F_REG_READ, F_REG_WRITE): New.
 388         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 389         AARCH64_OPND_SYSREG.
 390         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 391         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 392         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 393         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 394         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 395         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 396         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 397         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 398         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 399         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 400         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 401         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 402         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 403         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 404         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 405         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 406         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 407
 408 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 409
 410         PR binutils/21446
 411         * aarch64-dis.c (no_notes: New.
 412         (parse_aarch64_dis_option): Support notes.
 413         (aarch64_decode_insn, print_operands): Likewise.
 414         (print_aarch64_disassembler_options): Document notes.
 415         * aarch64-opc.c (aarch64_print_operand): Support notes.
 416
 417 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 418
 419         PR binutils/21446
 420         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 421         and take error struct.
 422         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 423         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 424         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 425         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 426         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 427         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 428         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 429         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 430         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 431         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 432         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 433         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 434         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 435         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 436         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 437         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 438         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 439         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 440         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 441         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 442         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 443         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 444         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 445         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 446         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 447         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 448         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 449         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 450         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 451         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 452         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 453         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 454         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 455         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 456         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 457         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 458         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 459         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 460         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 461         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 462         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 463         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 464         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 465         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 466         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 467         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 468         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 469         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 470         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 471         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 472         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 473         (determine_disassembling_preference, aarch64_decode_insn,
 474         print_insn_aarch64_word, print_insn_data): Take errors struct.
 475         (print_insn_aarch64): Use errors.
 476         * aarch64-asm-2.c: Regenerate.
 477         * aarch64-dis-2.c: Regenerate.
 478         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 479         boolean in aarch64_insert_operan.
 480         (print_operand_extractor): Likewise.
 481         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 482
 483 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 484
 485         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 486
 487 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 488
 489         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 490
 491 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 492
 493         * cr16-opc.c (cr16_instruction): Comment typo fix.
 494         * hppa-dis.c (print_insn_hppa): Likewise.
 495
 496 2018-05-08  Jim Wilson  <jimw@sifive.com>
 497
 498         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 499         (match_c_slli64, match_srxi_as_c_srxi): New.
 500         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 501         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 502         <c.slli, c.srli, c.srai>: Use match_s_slli.
 503         <c.slli64, c.srli64, c.srai64>: New.
 504
 505 2018-05-08  Alan Modra  <amodra@gmail.com>
 506
 507         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 508         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 509         partition opcode space for index lookup.
 510
 511 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 512
 513         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 514         <insn_length>: ...with this.  Update usage.
 515         Remove duplicate call to *info->memory_error_func.
 516
 517 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 518             H.J. Lu  <hongjiu.lu@intel.com>
 519
 520         * i386-dis.c (Gva): New.
 521         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 522         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 523         (prefix_table): New instructions (see prefix above).
 524         (mod_table): New instructions (see prefix above).
 525         (OP_G): Handle va_mode.
 526         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 527         CPU_MOVDIR64B_FLAGS.
 528         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 529         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 530         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 531         * i386-opc.tbl: Add movidir{i,64b}.
 532         * i386-init.h: Regenerated.
 533         * i386-tbl.h: Likewise.
 534
 535 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 536
 537         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 538         AddrPrefixOpReg.
 539         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 540         (AddrPrefixOpReg): This.
 541         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 542         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 543
 544 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 545
 546         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 547         (vle_num_opcodes): Likewise.
 548         (spe2_num_opcodes): Likewise.
 549         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 550         initialization loop.
 551         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 552         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 553         only once.
 554
 555 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 556
 557         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 558
 559 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 560
 561         Makefile.am: Added nfp-dis.c.
 562         configure.ac: Added bfd_nfp_arch.
 563         disassemble.h: Added print_insn_nfp prototype.
 564         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 565         nfp-dis.c: New, for NFP support.
 566         po/POTFILES.in: Added nfp-dis.c to the list.
 567         Makefile.in: Regenerate.
 568         configure: Regenerate.
 569
 570 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 573         templates into their base ones.
 574         * i386-tlb.h: Re-generate.
 575
 576 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 577
 578         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 579         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 580         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 581         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 582         * i386-init.h: Re-generate.
 583
 584 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 587         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 588         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 589         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 590         comment.
 591         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 592         and CpuRegMask.
 593         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 594         CpuRegMask: Delete.
 595         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 596         cpuregzmm, and cpuregmask.
 597         * i386-init.h: Re-generate.
 598         * i386-tbl.h: Re-generate.
 599
 600 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 603         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 604         * i386-init.h: Re-generate.
 605
 606 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-gen.c (VexImmExt): Delete.
 609         * i386-opc.h (VexImmExt, veximmext): Delete.
 610         * i386-opc.tbl: Drop all VexImmExt uses.
 611         * i386-tlb.h: Re-generate.
 612
 613 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 616         register-only forms.
 617         * i386-tlb.h: Re-generate.
 618
 619 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 620
 621         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 622
 623 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 624
 625         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 626         PREFIX_0F1C.
 627         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 628         (cpu_flags): Add CpuCLDEMOTE.
 629         * i386-init.h: Regenerate.
 630         * i386-opc.h (enum): Add CpuCLDEMOTE,
 631         (i386_cpu_flags): Add cpucldemote.
 632         * i386-opc.tbl: Add cldemote.
 633         * i386-tbl.h: Regenerate.
 634
 635 2018-04-16  Alan Modra  <amodra@gmail.com>
 636
 637         * Makefile.am: Remove sh5 and sh64 support.
 638         * configure.ac: Likewise.
 639         * disassemble.c: Likewise.
 640         * disassemble.h: Likewise.
 641         * sh-dis.c: Likewise.
 642         * sh64-dis.c: Delete.
 643         * sh64-opc.c: Delete.
 644         * sh64-opc.h: Delete.
 645         * Makefile.in: Regenerate.
 646         * configure: Regenerate.
 647         * po/POTFILES.in: Regenerate.
 648
 649 2018-04-16  Alan Modra  <amodra@gmail.com>
 650
 651         * Makefile.am: Remove w65 support.
 652         * configure.ac: Likewise.
 653         * disassemble.c: Likewise.
 654         * disassemble.h: Likewise.
 655         * w65-dis.c: Delete.
 656         * w65-opc.h: Delete.
 657         * Makefile.in: Regenerate.
 658         * configure: Regenerate.
 659         * po/POTFILES.in: Regenerate.
 660
 661 2018-04-16  Alan Modra  <amodra@gmail.com>
 662
 663         * configure.ac: Remove we32k support.
 664         * configure: Regenerate.
 665
 666 2018-04-16  Alan Modra  <amodra@gmail.com>
 667
 668         * Makefile.am: Remove m88k support.
 669         * configure.ac: Likewise.
 670         * disassemble.c: Likewise.
 671         * disassemble.h: Likewise.
 672         * m88k-dis.c: Delete.
 673         * Makefile.in: Regenerate.
 674         * configure: Regenerate.
 675         * po/POTFILES.in: Regenerate.
 676
 677 2018-04-16  Alan Modra  <amodra@gmail.com>
 678
 679         * Makefile.am: Remove i370 support.
 680         * configure.ac: Likewise.
 681         * disassemble.c: Likewise.
 682         * disassemble.h: Likewise.
 683         * i370-dis.c: Delete.
 684         * i370-opc.c: Delete.
 685         * Makefile.in: Regenerate.
 686         * configure: Regenerate.
 687         * po/POTFILES.in: Regenerate.
 688
 689 2018-04-16  Alan Modra  <amodra@gmail.com>
 690
 691         * Makefile.am: Remove h8500 support.
 692         * configure.ac: Likewise.
 693         * disassemble.c: Likewise.
 694         * disassemble.h: Likewise.
 695         * h8500-dis.c: Delete.
 696         * h8500-opc.h: Delete.
 697         * Makefile.in: Regenerate.
 698         * configure: Regenerate.
 699         * po/POTFILES.in: Regenerate.
 700
 701 2018-04-16  Alan Modra  <amodra@gmail.com>
 702
 703         * configure.ac: Remove tahoe support.
 704         * configure: Regenerate.
 705
 706 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 707
 708         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 709         umwait.
 710         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 711         64-bit mode.
 712         * i386-tbl.h: Regenerated.
 713
 714 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 715
 716         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 717         PREFIX_MOD_1_0FAE_REG_6.
 718         (va_mode): New.
 719         (OP_E_register): Use va_mode.
 720         * i386-dis-evex.h (prefix_table):
 721         New instructions (see prefixes above).
 722         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 723         (cpu_flags): Likewise.
 724         * i386-opc.h (enum): Likewise.
 725         (i386_cpu_flags): Likewise.
 726         * i386-opc.tbl: Add umonitor, umwait, tpause.
 727         * i386-init.h: Regenerate.
 728         * i386-tbl.h: Likewise.
 729
 730 2018-04-11  Alan Modra  <amodra@gmail.com>
 731
 732         * opcodes/i860-dis.c: Delete.
 733         * opcodes/i960-dis.c: Delete.
 734         * Makefile.am: Remove i860 and i960 support.
 735         * configure.ac: Likewise.
 736         * disassemble.c: Likewise.
 737         * disassemble.h: Likewise.
 738         * Makefile.in: Regenerate.
 739         * configure: Regenerate.
 740         * po/POTFILES.in: Regenerate.
 741
 742 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 743
 744         PR binutils/23025
 745         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 746         to 0.
 747         (print_insn): Clear vex instead of vex.evex.
 748
 749 2018-04-04  Nick Clifton  <nickc@redhat.com>
 750
 751         * po/es.po: Updated Spanish translation.
 752
 753 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 754
 755         * i386-gen.c (opcode_modifiers): Delete VecESize.
 756         * i386-opc.h (VecESize): Delete.
 757         (struct i386_opcode_modifier): Delete vecesize.
 758         * i386-opc.tbl: Drop VecESize.
 759         * i386-tlb.h: Re-generate.
 760
 761 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 764         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 765         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 766         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 767         * i386-tlb.h: Re-generate.
 768
 769 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 772         Fold AVX512 forms
 773         * i386-tlb.h: Re-generate.
 774
 775 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 778         (vex_len_table): Drop Y for vcvt*2si.
 779         (putop): Replace plain 'Y' handling by abort().
 780
 781 2018-03-28  Nick Clifton  <nickc@redhat.com>
 782
 783         PR 22988
 784         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 785         instructions with only a base address register.
 786         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 787         handle AARHC64_OPND_SVE_ADDR_R.
 788         (aarch64_print_operand): Likewise.
 789         * aarch64-asm-2.c: Regenerate.
 790         * aarch64_dis-2.c: Regenerate.
 791         * aarch64-opc-2.c: Regenerate.
 792
 793 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-opc.tbl: Drop VecESize from register only insn forms and
 796         memory forms not allowing broadcast.
 797         * i386-tlb.h: Re-generate.
 798
 799 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 800
 801         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 802         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 803         sha256*): Drop Disp<N>.
 804
 805 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-dis.c (EbndS, bnd_swap_mode): New.
 808         (prefix_table): Use EbndS.
 809         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 810         * i386-opc.tbl (bndmov): Move misplaced Load.
 811         * i386-tlb.h: Re-generate.
 812
 813 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 814
 815         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 816         templates allowing memory operands and folded ones for register
 817         only flavors.
 818         * i386-tlb.h: Re-generate.
 819
 820 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 823         256-bit templates. Drop redundant leftover Disp<N>.
 824         * i386-tlb.h: Re-generate.
 825
 826 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 827
 828         * riscv-opc.c (riscv_insn_types): New.
 829
 830 2018-03-13  Nick Clifton  <nickc@redhat.com>
 831
 832         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 833
 834 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 835
 836         * i386-opc.tbl: Add Optimize to clr.
 837         * i386-tbl.h: Regenerated.
 838
 839 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 840
 841         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 842         * i386-opc.h (OldGcc): Removed.
 843         (i386_opcode_modifier): Remove oldgcc.
 844         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 845         instructions for old (<= 2.8.1) versions of gcc.
 846         * i386-tbl.h: Regenerated.
 847
 848 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.h (EVEXDYN): New.
 851         * i386-opc.tbl: Fold various AVX512VL templates.
 852         * i386-tlb.h: Re-generate.
 853
 854 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 857         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 858         vpexpandd, vpexpandq): Fold AFX512VF templates.
 859         * i386-tlb.h: Re-generate.
 860
 861 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 864         Fold 128- and 256-bit VEX-encoded templates.
 865         * i386-tlb.h: Re-generate.
 866
 867 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 870         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 871         vpexpandd, vpexpandq): Fold AVX512F templates.
 872         * i386-tlb.h: Re-generate.
 873
 874 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 875
 876         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 877         64-bit templates. Drop Disp<N>.
 878         * i386-tlb.h: Re-generate.
 879
 880 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 881
 882         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 883         and 256-bit templates.
 884         * i386-tlb.h: Re-generate.
 885
 886 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 887
 888         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 889         * i386-tlb.h: Re-generate.
 890
 891 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 894         Drop NoAVX.
 895         * i386-tlb.h: Re-generate.
 896
 897 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 898
 899         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 900         * i386-tlb.h: Re-generate.
 901
 902 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 903
 904         * i386-gen.c (opcode_modifiers): Delete FloatD.
 905         * i386-opc.h (FloatD): Delete.
 906         (struct i386_opcode_modifier): Delete floatd.
 907         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 908         FloatD by D.
 909         * i386-tlb.h: Re-generate.
 910
 911 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 912
 913         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 914
 915 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 918         * i386-tlb.h: Re-generate.
 919
 920 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 921
 922         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 923         forms.
 924         * i386-tlb.h: Re-generate.
 925
 926 2018-03-07  Alan Modra  <amodra@gmail.com>
 927
 928         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 929         bfd_arch_rs6000.
 930         * disassemble.h (print_insn_rs6000): Delete.
 931         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 932         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 933         (print_insn_rs6000): Delete.
 934
 935 2018-03-03  Alan Modra  <amodra@gmail.com>
 936
 937         * sysdep.h (opcodes_error_handler): Define.
 938         (_bfd_error_handler): Declare.
 939         * Makefile.am: Remove stray #.
 940         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 941         EDIT" comment.
 942         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 943         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 944         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 945         opcodes_error_handler to print errors.  Standardize error messages.
 946         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 947         and include opintl.h.
 948         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 949         * i386-gen.c: Standardize error messages.
 950         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 951         * Makefile.in: Regenerate.
 952         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 953         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 954         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 955         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 956         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 957         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 958         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 959         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 960         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 961         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 962         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 963         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 964         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 965
 966 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 967
 968         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 969         vpsub[bwdq] instructions.
 970         * i386-tbl.h: Regenerated.
 971
 972 2018-03-01  Alan Modra  <amodra@gmail.com>
 973
 974         * configure.ac (ALL_LINGUAS): Sort.
 975         * configure: Regenerate.
 976
 977 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 978
 979         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 980         macro by assignements.
 981
 982 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 983
 984         PR gas/22871
 985         * i386-gen.c (opcode_modifiers): Add Optimize.
 986         * i386-opc.h (Optimize): New enum.
 987         (i386_opcode_modifier): Add optimize.
 988         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 989         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 990         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 991         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 992         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 993         vpxord and vpxorq.
 994         * i386-tbl.h: Regenerated.
 995
 996 2018-02-26  Alan Modra  <amodra@gmail.com>
 997
 998         * crx-dis.c (getregliststring): Allocate a large enough buffer
 999         to silence false positive gcc8 warning.
1000
1001 2018-02-22  Shea Levy <shea@shealevy.com>
1002
1003         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1004
1005 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1006
1007         * i386-opc.tbl: Add {rex},
1008         * i386-tbl.h: Regenerated.
1009
1010 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1011
1012         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1013         (mips16_opcodes): Replace `M' with `m' for "restore".
1014
1015 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1016
1017         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1018
1019 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1020
1021         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1022         variable to `function_index'.
1023
1024 2018-02-13  Nick Clifton  <nickc@redhat.com>
1025
1026         PR 22823
1027         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1028         about truncation of printing.
1029
1030 2018-02-12  Henry Wong <henry@stuffedcow.net>
1031
1032         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1033
1034 2018-02-05  Nick Clifton  <nickc@redhat.com>
1035
1036         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1037
1038 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1039
1040         * i386-dis.c (enum): Add pconfig.
1041         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1042         (cpu_flags): Add CpuPCONFIG.
1043         * i386-opc.h (enum): Add CpuPCONFIG.
1044         (i386_cpu_flags): Add cpupconfig.
1045         * i386-opc.tbl: Add PCONFIG instruction.
1046         * i386-init.h: Regenerate.
1047         * i386-tbl.h: Likewise.
1048
1049 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1050
1051         * i386-dis.c (enum): Add PREFIX_0F09.
1052         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1053         (cpu_flags): Add CpuWBNOINVD.
1054         * i386-opc.h (enum): Add CpuWBNOINVD.
1055         (i386_cpu_flags): Add cpuwbnoinvd.
1056         * i386-opc.tbl: Add WBNOINVD instruction.
1057         * i386-init.h: Regenerate.
1058         * i386-tbl.h: Likewise.
1059
1060 2018-01-17  Jim Wilson  <jimw@sifive.com>
1061
1062         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1063
1064 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1065
1066         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1067         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1068         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1069         (cpu_flags): Add CpuIBT, CpuSHSTK.
1070         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1071         (i386_cpu_flags): Add cpuibt, cpushstk.
1072         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1073         * i386-init.h: Regenerate.
1074         * i386-tbl.h: Likewise.
1075
1076 2018-01-16  Nick Clifton  <nickc@redhat.com>
1077
1078         * po/pt_BR.po: Updated Brazilian Portugese translation.
1079         * po/de.po: Updated German translation.
1080
1081 2018-01-15  Jim Wilson  <jimw@sifive.com>
1082
1083         * riscv-opc.c (match_c_nop): New.
1084         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1085
1086 2018-01-15  Nick Clifton  <nickc@redhat.com>
1087
1088         * po/uk.po: Updated Ukranian translation.
1089
1090 2018-01-13  Nick Clifton  <nickc@redhat.com>
1091
1092         * po/opcodes.pot: Regenerated.
1093
1094 2018-01-13  Nick Clifton  <nickc@redhat.com>
1095
1096         * configure: Regenerate.
1097
1098 2018-01-13  Nick Clifton  <nickc@redhat.com>
1099
1100         2.30 branch created.
1101
1102 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1103
1104         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1105         * i386-tbl.h: Regenerate.
1106
1107 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1108
1109         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1110         * i386-tbl.h: Re-generate.
1111
1112 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1115         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1116         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1117         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1118         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1119         Disp8MemShift of AVX512VL forms.
1120         * i386-tbl.h: Re-generate.
1121
1122 2018-01-09  Jim Wilson  <jimw@sifive.com>
1123
1124         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1125         then the hi_addr value is zero.
1126
1127 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1128
1129         * arm-dis.c (arm_opcodes): Add csdb.
1130         (thumb32_opcodes): Add csdb.
1131
1132 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1133
1134         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1135         * aarch64-asm-2.c: Regenerate.
1136         * aarch64-dis-2.c: Regenerate.
1137         * aarch64-opc-2.c: Regenerate.
1138
1139 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1140
1141         PR gas/22681
1142         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1143         Remove AVX512 vmovd with 64-bit operands.
1144         * i386-tbl.h: Regenerated.
1145
1146 2018-01-05  Jim Wilson  <jimw@sifive.com>
1147
1148         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1149         jalr.
1150
1151 2018-01-03  Alan Modra  <amodra@gmail.com>
1152
1153         Update year range in copyright notice of all files.
1154
1155 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1156
1157         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1158         and OPERAND_TYPE_REGZMM entries.
1159
1160 For older changes see ChangeLog-2017
1161 \f
1162 Copyright (C) 2018 Free Software Foundation, Inc.
1163
1164 Copying and distribution of this file, with or without modification,
1165 are permitted in any medium without royalty provided the copyright
1166 notice and this notice are preserved.
1167
1168 Local Variables:
1169 mode: change-log
1170 left-margin: 8
1171 fill-column: 74
1172 version-control: never
1173 End: