1 2018-08-20 Alan Modra <amodra@gmail.com>
3 * sh-opc.h (MASK): Simplify.
5 2018-08-18 John Darrington <john@darrington.wattle.id.au>
7 * s12z-dis.c (bm_decode): Deal with cases where the mode is
8 BM_RESERVED0 or BM_RESERVED1
9 (bm_rel_decode, bm_n_bytes): Ditto.
11 2018-08-18 John Darrington <john@darrington.wattle.id.au>
15 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
17 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
18 address with the addr32 prefix and without base nor index
21 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
23 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
24 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
25 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
26 (cpu_flags): Add CpuCMOV and CpuFXSR.
27 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
28 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
29 * i386-init.h: Regenerated.
30 * i386-tbl.h: Likewise.
32 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
34 * arc-regs.h: Update auxiliary registers.
36 2018-08-06 Jan Beulich <jbeulich@suse.com>
38 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
39 (RegIP, RegIZ): Define.
40 * i386-reg.tbl: Adjust comments.
41 (rip): Use Qword instead of BaseIndex. Use RegIP.
42 (eip): Use Dword instead of BaseIndex. Use RegIP.
43 (riz): Add Qword. Use RegIZ.
44 (eiz): Add Dword. Use RegIZ.
45 * i386-tbl.h: Re-generate.
47 2018-08-03 Jan Beulich <jbeulich@suse.com>
49 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
50 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
51 vpmovzxdq, vpmovzxwd): Remove NoRex64.
52 * i386-tbl.h: Re-generate.
54 2018-08-03 Jan Beulich <jbeulich@suse.com>
56 * i386-gen.c (operand_types): Remove Mem field.
57 * i386-opc.h (union i386_operand_type): Remove mem field.
58 * i386-init.h, i386-tbl.h: Re-generate.
60 2018-08-01 Alan Modra <amodra@gmail.com>
62 * po/POTFILES.in: Regenerate.
64 2018-07-31 Nick Clifton <nickc@redhat.com>
66 * po/sv.po: Updated Swedish translation.
68 2018-07-31 Jan Beulich <jbeulich@suse.com>
70 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
71 * i386-init.h, i386-tbl.h: Re-generate.
73 2018-07-31 Jan Beulich <jbeulich@suse.com>
75 * i386-opc.h (ZEROING_MASKING) Rename to ...
76 (DYNAMIC_MASKING): ... this. Adjust comment.
77 * i386-opc.tbl (MaskingMorZ): Define.
78 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
79 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
80 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
81 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
82 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
83 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
84 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
85 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
86 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
88 2018-07-31 Jan Beulich <jbeulich@suse.com>
90 * i386-opc.tbl: Use element rather than vector size for AVX512*
92 * i386-tbl.h: Re-generate.
94 2018-07-31 Jan Beulich <jbeulich@suse.com>
96 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
97 (cpu_flags): Drop CpuVREX.
98 * i386-opc.h (CpuVREX): Delete.
99 (union i386_cpu_flags): Remove cpuvrex.
100 * i386-init.h, i386-tbl.h: Re-generate.
102 2018-07-30 Jim Wilson <jimw@sifive.com>
104 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
106 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
108 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
110 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
111 * Makefile.in: Regenerated.
112 * configure.ac: Add C-SKY.
113 * configure: Regenerated.
114 * csky-dis.c: New file.
115 * csky-opc.h: New file.
116 * disassemble.c (ARCH_csky): Define.
117 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
118 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
120 2018-07-27 Alan Modra <amodra@gmail.com>
122 * ppc-opc.c (insert_sprbat): Correct function parameter and
124 (extract_sprbat): Likewise, variable too.
126 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
127 Alan Modra <amodra@gmail.com>
129 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
130 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
131 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
132 support disjointed BAT.
133 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
134 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
135 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
137 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
138 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
140 * i386-gen.c (adjust_broadcast_modifier): New function.
141 (process_i386_opcode_modifier): Add an argument for operands.
142 Adjust the Broadcast value based on operands.
143 (output_i386_opcode): Pass operand_types to
144 process_i386_opcode_modifier.
145 (process_i386_opcodes): Pass NULL as operands to
146 process_i386_opcode_modifier.
147 * i386-opc.h (BYTE_BROADCAST): New.
148 (WORD_BROADCAST): Likewise.
149 (DWORD_BROADCAST): Likewise.
150 (QWORD_BROADCAST): Likewise.
151 (i386_opcode_modifier): Expand broadcast to 3 bits.
152 * i386-tbl.h: Regenerated.
154 2018-07-24 Alan Modra <amodra@gmail.com>
157 * or1k-desc.h: Regenerate.
159 2018-07-24 Jan Beulich <jbeulich@suse.com>
161 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
162 vcvtusi2ss, and vcvtusi2sd.
163 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
164 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
165 * i386-tbl.h: Re-generate.
167 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
169 * arc-opc.c (extract_w6): Fix extending the sign.
171 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
173 * arc-tbl.h (vewt): Allow it for ARC EM family.
175 2018-07-23 Alan Modra <amodra@gmail.com>
178 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
179 opcode variants for mtspr/mfspr encodings.
181 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
182 Maciej W. Rozycki <macro@mips.com>
184 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
185 loongson3a descriptors.
186 (parse_mips_ase_option): Handle -M loongson-mmi option.
187 (print_mips_disassembler_options): Document -M loongson-mmi.
188 * mips-opc.c (LMMI): New macro.
189 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
192 2018-07-19 Jan Beulich <jbeulich@suse.com>
194 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
195 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
196 IgnoreSize and [XYZ]MMword where applicable.
197 * i386-tbl.h: Re-generate.
199 2018-07-19 Jan Beulich <jbeulich@suse.com>
201 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
202 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
203 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
204 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
205 * i386-tbl.h: Re-generate.
207 2018-07-19 Jan Beulich <jbeulich@suse.com>
209 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
210 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
211 VPCLMULQDQ templates into their respective AVX512VL counterparts
212 where possible, using Disp8ShiftVL and CheckRegSize instead of
213 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
214 * i386-tbl.h: Re-generate.
216 2018-07-19 Jan Beulich <jbeulich@suse.com>
218 * i386-opc.tbl: Fold AVX512DQ templates into their respective
219 AVX512VL counterparts where possible, using Disp8ShiftVL and
220 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
221 IgnoreSize) as appropriate.
222 * i386-tbl.h: Re-generate.
224 2018-07-19 Jan Beulich <jbeulich@suse.com>
226 * i386-opc.tbl: Fold AVX512BW templates into their respective
227 AVX512VL counterparts where possible, using Disp8ShiftVL and
228 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
229 IgnoreSize) as appropriate.
230 * i386-tbl.h: Re-generate.
232 2018-07-19 Jan Beulich <jbeulich@suse.com>
234 * i386-opc.tbl: Fold AVX512CD templates into their respective
235 AVX512VL counterparts where possible, using Disp8ShiftVL and
236 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
237 IgnoreSize) as appropriate.
238 * i386-tbl.h: Re-generate.
240 2018-07-19 Jan Beulich <jbeulich@suse.com>
242 * i386-opc.h (DISP8_SHIFT_VL): New.
243 * i386-opc.tbl (Disp8ShiftVL): Define.
244 (various): Fold AVX512VL templates into their respective
245 AVX512F counterparts where possible, using Disp8ShiftVL and
246 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
247 IgnoreSize) as appropriate.
248 * i386-tbl.h: Re-generate.
250 2018-07-19 Jan Beulich <jbeulich@suse.com>
252 * Makefile.am: Change dependencies and rule for
253 $(srcdir)/i386-init.h.
254 * Makefile.in: Re-generate.
255 * i386-gen.c (process_i386_opcodes): New local variable
256 "marker". Drop opening of input file. Recognize marker and line
258 * i386-opc.tbl (OPCODE_I386_H): Define.
259 (i386-opc.h): Include it.
262 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
265 * i386-opc.h (Byte): Update comments.
274 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
276 * i386-tbl.h: Regenerated.
278 2018-07-12 Sudakshina Das <sudi.das@arm.com>
280 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
281 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
282 * aarch64-asm-2.c: Regenerate.
283 * aarch64-dis-2.c: Regenerate.
284 * aarch64-opc-2.c: Regenerate.
286 2018-07-12 Tamar Christina <tamar.christina@arm.com>
289 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
290 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
291 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
292 sqdmulh, sqrdmulh): Use Em16.
294 2018-07-11 Sudakshina Das <sudi.das@arm.com>
296 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
297 csdb together with them.
298 (thumb32_opcodes): Likewise.
300 2018-07-11 Jan Beulich <jbeulich@suse.com>
302 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
303 requiring 32-bit registers as operands 2 and 3. Improve
305 (mwait, mwaitx): Fold templates. Improve comments.
306 OPERAND_TYPE_INOUTPORTREG.
307 * i386-tbl.h: Re-generate.
309 2018-07-11 Jan Beulich <jbeulich@suse.com>
311 * i386-gen.c (operand_type_init): Remove
312 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
313 OPERAND_TYPE_INOUTPORTREG.
314 * i386-init.h: Re-generate.
316 2018-07-11 Jan Beulich <jbeulich@suse.com>
318 * i386-opc.tbl (wrssd, wrussd): Add Dword.
319 (wrssq, wrussq): Add Qword.
320 * i386-tbl.h: Re-generate.
322 2018-07-11 Jan Beulich <jbeulich@suse.com>
324 * i386-opc.h: Rename OTMax to OTNum.
325 (OTNumOfUints): Adjust calculation.
326 (OTUnused): Directly alias to OTNum.
328 2018-07-09 Maciej W. Rozycki <macro@mips.com>
330 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
332 (lea_reg_xys): Likewise.
333 (print_insn_loop_primitive): Rename `reg' local variable to
336 2018-07-06 Tamar Christina <tamar.christina@arm.com>
339 * aarch64-tbl.h (ldarh): Fix disassembly mask.
341 2018-07-06 Tamar Christina <tamar.christina@arm.com>
344 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
345 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
347 2018-07-02 Maciej W. Rozycki <macro@mips.com>
350 * mips-dis.c (mips_option_arg_t): New enumeration.
351 (mips_options): New variable.
352 (disassembler_options_mips): New function.
353 (print_mips_disassembler_options): Reimplement in terms of
354 `disassembler_options_mips'.
355 * arm-dis.c (disassembler_options_arm): Adapt to using the
356 `disasm_options_and_args_t' structure.
357 * ppc-dis.c (disassembler_options_powerpc): Likewise.
358 * s390-dis.c (disassembler_options_s390): Likewise.
360 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
362 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
364 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
365 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
366 * testsuite/ld-arm/tls-longplt.d: Likewise.
368 2018-06-29 Tamar Christina <tamar.christina@arm.com>
371 * aarch64-asm-2.c: Regenerate.
372 * aarch64-dis-2.c: Likewise.
373 * aarch64-opc-2.c: Likewise.
374 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
375 * aarch64-opc.c (operand_general_constraint_met_p,
376 aarch64_print_operand): Likewise.
377 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
378 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
380 (AARCH64_OPERANDS): Add Em2.
382 2018-06-26 Nick Clifton <nickc@redhat.com>
384 * po/uk.po: Updated Ukranian translation.
385 * po/de.po: Updated German translation.
386 * po/pt_BR.po: Updated Brazilian Portuguese translation.
388 2018-06-26 Nick Clifton <nickc@redhat.com>
390 * nfp-dis.c: Fix spelling mistake.
392 2018-06-24 Nick Clifton <nickc@redhat.com>
394 * configure: Regenerate.
395 * po/opcodes.pot: Regenerate.
397 2018-06-24 Nick Clifton <nickc@redhat.com>
401 2018-06-19 Tamar Christina <tamar.christina@arm.com>
403 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
404 * aarch64-asm-2.c: Regenerate.
405 * aarch64-dis-2.c: Likewise.
407 2018-06-21 Maciej W. Rozycki <macro@mips.com>
409 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
410 `-M ginv' option description.
412 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
415 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
418 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
420 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
421 * configure.ac: Remove AC_PREREQ.
422 * Makefile.in: Re-generate.
423 * aclocal.m4: Re-generate.
424 * configure: Re-generate.
426 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
428 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
429 mips64r6 descriptors.
430 (parse_mips_ase_option): Handle -Mginv option.
431 (print_mips_disassembler_options): Document -Mginv.
432 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
434 (mips_opcodes): Define ginvi and ginvt.
436 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
437 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
439 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
440 * mips-opc.c (CRC, CRC64): New macros.
441 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
442 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
445 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
448 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
449 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
451 2018-06-06 Alan Modra <amodra@gmail.com>
453 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
454 setjmp. Move init for some other vars later too.
456 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
458 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
459 (dis_private): Add new fields for property section tracking.
460 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
461 (xtensa_instruction_fits): New functions.
462 (fetch_data): Bump minimal fetch size to 4.
463 (print_insn_xtensa): Make struct dis_private static.
464 Load and prepare property table on section change.
465 Don't disassemble literals. Don't disassemble instructions that
466 cross property table boundaries.
468 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
470 * configure: Regenerated.
472 2018-06-01 Jan Beulich <jbeulich@suse.com>
474 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
475 * i386-tbl.h: Re-generate.
477 2018-06-01 Jan Beulich <jbeulich@suse.com>
479 * i386-opc.tbl (sldt, str): Add NoRex64.
480 * i386-tbl.h: Re-generate.
482 2018-06-01 Jan Beulich <jbeulich@suse.com>
484 * i386-opc.tbl (invpcid): Add Oword.
485 * i386-tbl.h: Re-generate.
487 2018-06-01 Alan Modra <amodra@gmail.com>
489 * sysdep.h (_bfd_error_handler): Don't declare.
490 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
491 * rl78-decode.opc: Likewise.
492 * msp430-decode.c: Regenerate.
493 * rl78-decode.c: Regenerate.
495 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
497 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
498 * i386-init.h : Regenerated.
500 2018-05-25 Alan Modra <amodra@gmail.com>
502 * Makefile.in: Regenerate.
503 * po/POTFILES.in: Regenerate.
505 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
507 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
508 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
509 (insert_bab, extract_bab, insert_btab, extract_btab,
510 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
511 (BAT, BBA VBA RBS XB6S): Delete macros.
512 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
513 (BB, BD, RBX, XC6): Update for new macros.
514 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
515 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
516 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
517 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
519 2018-05-18 John Darrington <john@darrington.wattle.id.au>
521 * Makefile.am: Add support for s12z architecture.
522 * configure.ac: Likewise.
523 * disassemble.c: Likewise.
524 * disassemble.h: Likewise.
525 * Makefile.in: Regenerate.
526 * configure: Regenerate.
527 * s12z-dis.c: New file.
530 2018-05-18 Alan Modra <amodra@gmail.com>
532 * nfp-dis.c: Don't #include libbfd.h.
533 (init_nfp3200_priv): Use bfd_get_section_contents.
534 (nit_nfp6000_mecsr_sec): Likewise.
536 2018-05-17 Nick Clifton <nickc@redhat.com>
538 * po/zh_CN.po: Updated simplified Chinese translation.
540 2018-05-16 Tamar Christina <tamar.christina@arm.com>
543 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
544 * aarch64-dis-2.c: Regenerate.
546 2018-05-15 Tamar Christina <tamar.christina@arm.com>
549 * aarch64-asm.c (opintl.h): Include.
550 (aarch64_ins_sysreg): Enforce read/write constraints.
551 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
552 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
553 (F_REG_READ, F_REG_WRITE): New.
554 * aarch64-opc.c (aarch64_print_operand): Generate notes for
556 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
557 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
558 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
559 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
560 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
561 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
562 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
563 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
564 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
565 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
566 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
567 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
568 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
569 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
570 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
571 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
572 msr (F_SYS_WRITE), mrs (F_SYS_READ).
574 2018-05-15 Tamar Christina <tamar.christina@arm.com>
577 * aarch64-dis.c (no_notes: New.
578 (parse_aarch64_dis_option): Support notes.
579 (aarch64_decode_insn, print_operands): Likewise.
580 (print_aarch64_disassembler_options): Document notes.
581 * aarch64-opc.c (aarch64_print_operand): Support notes.
583 2018-05-15 Tamar Christina <tamar.christina@arm.com>
586 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
587 and take error struct.
588 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
589 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
590 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
591 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
592 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
593 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
594 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
595 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
596 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
597 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
598 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
599 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
600 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
601 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
602 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
603 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
604 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
605 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
606 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
607 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
608 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
609 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
610 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
611 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
612 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
613 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
614 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
615 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
616 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
617 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
618 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
619 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
620 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
621 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
622 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
623 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
624 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
625 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
626 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
627 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
628 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
629 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
630 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
631 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
632 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
633 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
634 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
635 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
636 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
637 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
638 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
639 (determine_disassembling_preference, aarch64_decode_insn,
640 print_insn_aarch64_word, print_insn_data): Take errors struct.
641 (print_insn_aarch64): Use errors.
642 * aarch64-asm-2.c: Regenerate.
643 * aarch64-dis-2.c: Regenerate.
644 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
645 boolean in aarch64_insert_operan.
646 (print_operand_extractor): Likewise.
647 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
649 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
651 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
653 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
655 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
657 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
659 * cr16-opc.c (cr16_instruction): Comment typo fix.
660 * hppa-dis.c (print_insn_hppa): Likewise.
662 2018-05-08 Jim Wilson <jimw@sifive.com>
664 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
665 (match_c_slli64, match_srxi_as_c_srxi): New.
666 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
667 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
668 <c.slli, c.srli, c.srai>: Use match_s_slli.
669 <c.slli64, c.srli64, c.srai64>: New.
671 2018-05-08 Alan Modra <amodra@gmail.com>
673 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
674 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
675 partition opcode space for index lookup.
677 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
679 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
680 <insn_length>: ...with this. Update usage.
681 Remove duplicate call to *info->memory_error_func.
683 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
684 H.J. Lu <hongjiu.lu@intel.com>
686 * i386-dis.c (Gva): New.
687 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
688 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
689 (prefix_table): New instructions (see prefix above).
690 (mod_table): New instructions (see prefix above).
691 (OP_G): Handle va_mode.
692 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
694 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
695 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
696 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
697 * i386-opc.tbl: Add movidir{i,64b}.
698 * i386-init.h: Regenerated.
699 * i386-tbl.h: Likewise.
701 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
703 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
705 * i386-opc.h (AddrPrefixOp0): Renamed to ...
706 (AddrPrefixOpReg): This.
707 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
708 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
710 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
712 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
713 (vle_num_opcodes): Likewise.
714 (spe2_num_opcodes): Likewise.
715 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
717 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
718 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
721 2018-05-01 Tamar Christina <tamar.christina@arm.com>
723 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
725 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
727 Makefile.am: Added nfp-dis.c.
728 configure.ac: Added bfd_nfp_arch.
729 disassemble.h: Added print_insn_nfp prototype.
730 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
731 nfp-dis.c: New, for NFP support.
732 po/POTFILES.in: Added nfp-dis.c to the list.
733 Makefile.in: Regenerate.
734 configure: Regenerate.
736 2018-04-26 Jan Beulich <jbeulich@suse.com>
738 * i386-opc.tbl: Fold various non-memory operand AVX512VL
739 templates into their base ones.
740 * i386-tlb.h: Re-generate.
742 2018-04-26 Jan Beulich <jbeulich@suse.com>
744 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
745 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
746 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
747 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
748 * i386-init.h: Re-generate.
750 2018-04-26 Jan Beulich <jbeulich@suse.com>
752 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
753 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
754 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
755 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
757 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
759 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
761 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
762 cpuregzmm, and cpuregmask.
763 * i386-init.h: Re-generate.
764 * i386-tbl.h: Re-generate.
766 2018-04-26 Jan Beulich <jbeulich@suse.com>
768 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
769 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
770 * i386-init.h: Re-generate.
772 2018-04-26 Jan Beulich <jbeulich@suse.com>
774 * i386-gen.c (VexImmExt): Delete.
775 * i386-opc.h (VexImmExt, veximmext): Delete.
776 * i386-opc.tbl: Drop all VexImmExt uses.
777 * i386-tlb.h: Re-generate.
779 2018-04-25 Jan Beulich <jbeulich@suse.com>
781 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
783 * i386-tlb.h: Re-generate.
785 2018-04-25 Tamar Christina <tamar.christina@arm.com>
787 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
789 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
791 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
793 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
794 (cpu_flags): Add CpuCLDEMOTE.
795 * i386-init.h: Regenerate.
796 * i386-opc.h (enum): Add CpuCLDEMOTE,
797 (i386_cpu_flags): Add cpucldemote.
798 * i386-opc.tbl: Add cldemote.
799 * i386-tbl.h: Regenerate.
801 2018-04-16 Alan Modra <amodra@gmail.com>
803 * Makefile.am: Remove sh5 and sh64 support.
804 * configure.ac: Likewise.
805 * disassemble.c: Likewise.
806 * disassemble.h: Likewise.
807 * sh-dis.c: Likewise.
808 * sh64-dis.c: Delete.
809 * sh64-opc.c: Delete.
810 * sh64-opc.h: Delete.
811 * Makefile.in: Regenerate.
812 * configure: Regenerate.
813 * po/POTFILES.in: Regenerate.
815 2018-04-16 Alan Modra <amodra@gmail.com>
817 * Makefile.am: Remove w65 support.
818 * configure.ac: Likewise.
819 * disassemble.c: Likewise.
820 * disassemble.h: Likewise.
823 * Makefile.in: Regenerate.
824 * configure: Regenerate.
825 * po/POTFILES.in: Regenerate.
827 2018-04-16 Alan Modra <amodra@gmail.com>
829 * configure.ac: Remove we32k support.
830 * configure: Regenerate.
832 2018-04-16 Alan Modra <amodra@gmail.com>
834 * Makefile.am: Remove m88k support.
835 * configure.ac: Likewise.
836 * disassemble.c: Likewise.
837 * disassemble.h: Likewise.
838 * m88k-dis.c: Delete.
839 * Makefile.in: Regenerate.
840 * configure: Regenerate.
841 * po/POTFILES.in: Regenerate.
843 2018-04-16 Alan Modra <amodra@gmail.com>
845 * Makefile.am: Remove i370 support.
846 * configure.ac: Likewise.
847 * disassemble.c: Likewise.
848 * disassemble.h: Likewise.
849 * i370-dis.c: Delete.
850 * i370-opc.c: Delete.
851 * Makefile.in: Regenerate.
852 * configure: Regenerate.
853 * po/POTFILES.in: Regenerate.
855 2018-04-16 Alan Modra <amodra@gmail.com>
857 * Makefile.am: Remove h8500 support.
858 * configure.ac: Likewise.
859 * disassemble.c: Likewise.
860 * disassemble.h: Likewise.
861 * h8500-dis.c: Delete.
862 * h8500-opc.h: Delete.
863 * Makefile.in: Regenerate.
864 * configure: Regenerate.
865 * po/POTFILES.in: Regenerate.
867 2018-04-16 Alan Modra <amodra@gmail.com>
869 * configure.ac: Remove tahoe support.
870 * configure: Regenerate.
872 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
874 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
876 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
878 * i386-tbl.h: Regenerated.
880 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
882 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
883 PREFIX_MOD_1_0FAE_REG_6.
885 (OP_E_register): Use va_mode.
886 * i386-dis-evex.h (prefix_table):
887 New instructions (see prefixes above).
888 * i386-gen.c (cpu_flag_init): Add WAITPKG.
889 (cpu_flags): Likewise.
890 * i386-opc.h (enum): Likewise.
891 (i386_cpu_flags): Likewise.
892 * i386-opc.tbl: Add umonitor, umwait, tpause.
893 * i386-init.h: Regenerate.
894 * i386-tbl.h: Likewise.
896 2018-04-11 Alan Modra <amodra@gmail.com>
898 * opcodes/i860-dis.c: Delete.
899 * opcodes/i960-dis.c: Delete.
900 * Makefile.am: Remove i860 and i960 support.
901 * configure.ac: Likewise.
902 * disassemble.c: Likewise.
903 * disassemble.h: Likewise.
904 * Makefile.in: Regenerate.
905 * configure: Regenerate.
906 * po/POTFILES.in: Regenerate.
908 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
911 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
913 (print_insn): Clear vex instead of vex.evex.
915 2018-04-04 Nick Clifton <nickc@redhat.com>
917 * po/es.po: Updated Spanish translation.
919 2018-03-28 Jan Beulich <jbeulich@suse.com>
921 * i386-gen.c (opcode_modifiers): Delete VecESize.
922 * i386-opc.h (VecESize): Delete.
923 (struct i386_opcode_modifier): Delete vecesize.
924 * i386-opc.tbl: Drop VecESize.
925 * i386-tlb.h: Re-generate.
927 2018-03-28 Jan Beulich <jbeulich@suse.com>
929 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
930 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
931 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
932 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
933 * i386-tlb.h: Re-generate.
935 2018-03-28 Jan Beulich <jbeulich@suse.com>
937 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
939 * i386-tlb.h: Re-generate.
941 2018-03-28 Jan Beulich <jbeulich@suse.com>
943 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
944 (vex_len_table): Drop Y for vcvt*2si.
945 (putop): Replace plain 'Y' handling by abort().
947 2018-03-28 Nick Clifton <nickc@redhat.com>
950 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
951 instructions with only a base address register.
952 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
953 handle AARHC64_OPND_SVE_ADDR_R.
954 (aarch64_print_operand): Likewise.
955 * aarch64-asm-2.c: Regenerate.
956 * aarch64_dis-2.c: Regenerate.
957 * aarch64-opc-2.c: Regenerate.
959 2018-03-22 Jan Beulich <jbeulich@suse.com>
961 * i386-opc.tbl: Drop VecESize from register only insn forms and
962 memory forms not allowing broadcast.
963 * i386-tlb.h: Re-generate.
965 2018-03-22 Jan Beulich <jbeulich@suse.com>
967 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
968 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
969 sha256*): Drop Disp<N>.
971 2018-03-22 Jan Beulich <jbeulich@suse.com>
973 * i386-dis.c (EbndS, bnd_swap_mode): New.
974 (prefix_table): Use EbndS.
975 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
976 * i386-opc.tbl (bndmov): Move misplaced Load.
977 * i386-tlb.h: Re-generate.
979 2018-03-22 Jan Beulich <jbeulich@suse.com>
981 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
982 templates allowing memory operands and folded ones for register
984 * i386-tlb.h: Re-generate.
986 2018-03-22 Jan Beulich <jbeulich@suse.com>
988 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
989 256-bit templates. Drop redundant leftover Disp<N>.
990 * i386-tlb.h: Re-generate.
992 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
994 * riscv-opc.c (riscv_insn_types): New.
996 2018-03-13 Nick Clifton <nickc@redhat.com>
998 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1000 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1002 * i386-opc.tbl: Add Optimize to clr.
1003 * i386-tbl.h: Regenerated.
1005 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1007 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1008 * i386-opc.h (OldGcc): Removed.
1009 (i386_opcode_modifier): Remove oldgcc.
1010 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1011 instructions for old (<= 2.8.1) versions of gcc.
1012 * i386-tbl.h: Regenerated.
1014 2018-03-08 Jan Beulich <jbeulich@suse.com>
1016 * i386-opc.h (EVEXDYN): New.
1017 * i386-opc.tbl: Fold various AVX512VL templates.
1018 * i386-tlb.h: Re-generate.
1020 2018-03-08 Jan Beulich <jbeulich@suse.com>
1022 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1023 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1024 vpexpandd, vpexpandq): Fold AFX512VF templates.
1025 * i386-tlb.h: Re-generate.
1027 2018-03-08 Jan Beulich <jbeulich@suse.com>
1029 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1030 Fold 128- and 256-bit VEX-encoded templates.
1031 * i386-tlb.h: Re-generate.
1033 2018-03-08 Jan Beulich <jbeulich@suse.com>
1035 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1036 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1037 vpexpandd, vpexpandq): Fold AVX512F templates.
1038 * i386-tlb.h: Re-generate.
1040 2018-03-08 Jan Beulich <jbeulich@suse.com>
1042 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1043 64-bit templates. Drop Disp<N>.
1044 * i386-tlb.h: Re-generate.
1046 2018-03-08 Jan Beulich <jbeulich@suse.com>
1048 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1049 and 256-bit templates.
1050 * i386-tlb.h: Re-generate.
1052 2018-03-08 Jan Beulich <jbeulich@suse.com>
1054 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1055 * i386-tlb.h: Re-generate.
1057 2018-03-08 Jan Beulich <jbeulich@suse.com>
1059 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1061 * i386-tlb.h: Re-generate.
1063 2018-03-08 Jan Beulich <jbeulich@suse.com>
1065 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1066 * i386-tlb.h: Re-generate.
1068 2018-03-08 Jan Beulich <jbeulich@suse.com>
1070 * i386-gen.c (opcode_modifiers): Delete FloatD.
1071 * i386-opc.h (FloatD): Delete.
1072 (struct i386_opcode_modifier): Delete floatd.
1073 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1075 * i386-tlb.h: Re-generate.
1077 2018-03-08 Jan Beulich <jbeulich@suse.com>
1079 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1081 2018-03-08 Jan Beulich <jbeulich@suse.com>
1083 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1084 * i386-tlb.h: Re-generate.
1086 2018-03-08 Jan Beulich <jbeulich@suse.com>
1088 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1090 * i386-tlb.h: Re-generate.
1092 2018-03-07 Alan Modra <amodra@gmail.com>
1094 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1096 * disassemble.h (print_insn_rs6000): Delete.
1097 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1098 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1099 (print_insn_rs6000): Delete.
1101 2018-03-03 Alan Modra <amodra@gmail.com>
1103 * sysdep.h (opcodes_error_handler): Define.
1104 (_bfd_error_handler): Declare.
1105 * Makefile.am: Remove stray #.
1106 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1108 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1109 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1110 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1111 opcodes_error_handler to print errors. Standardize error messages.
1112 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1113 and include opintl.h.
1114 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1115 * i386-gen.c: Standardize error messages.
1116 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1117 * Makefile.in: Regenerate.
1118 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1119 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1120 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1121 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1122 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1123 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1124 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1125 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1126 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1127 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1128 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1129 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1130 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1132 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1134 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1135 vpsub[bwdq] instructions.
1136 * i386-tbl.h: Regenerated.
1138 2018-03-01 Alan Modra <amodra@gmail.com>
1140 * configure.ac (ALL_LINGUAS): Sort.
1141 * configure: Regenerate.
1143 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1145 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1146 macro by assignements.
1148 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1151 * i386-gen.c (opcode_modifiers): Add Optimize.
1152 * i386-opc.h (Optimize): New enum.
1153 (i386_opcode_modifier): Add optimize.
1154 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1155 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1156 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1157 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1158 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1160 * i386-tbl.h: Regenerated.
1162 2018-02-26 Alan Modra <amodra@gmail.com>
1164 * crx-dis.c (getregliststring): Allocate a large enough buffer
1165 to silence false positive gcc8 warning.
1167 2018-02-22 Shea Levy <shea@shealevy.com>
1169 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1171 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1173 * i386-opc.tbl: Add {rex},
1174 * i386-tbl.h: Regenerated.
1176 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1178 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1179 (mips16_opcodes): Replace `M' with `m' for "restore".
1181 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1183 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1185 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1187 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1188 variable to `function_index'.
1190 2018-02-13 Nick Clifton <nickc@redhat.com>
1193 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1194 about truncation of printing.
1196 2018-02-12 Henry Wong <henry@stuffedcow.net>
1198 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1200 2018-02-05 Nick Clifton <nickc@redhat.com>
1202 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1204 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1206 * i386-dis.c (enum): Add pconfig.
1207 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1208 (cpu_flags): Add CpuPCONFIG.
1209 * i386-opc.h (enum): Add CpuPCONFIG.
1210 (i386_cpu_flags): Add cpupconfig.
1211 * i386-opc.tbl: Add PCONFIG instruction.
1212 * i386-init.h: Regenerate.
1213 * i386-tbl.h: Likewise.
1215 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1217 * i386-dis.c (enum): Add PREFIX_0F09.
1218 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1219 (cpu_flags): Add CpuWBNOINVD.
1220 * i386-opc.h (enum): Add CpuWBNOINVD.
1221 (i386_cpu_flags): Add cpuwbnoinvd.
1222 * i386-opc.tbl: Add WBNOINVD instruction.
1223 * i386-init.h: Regenerate.
1224 * i386-tbl.h: Likewise.
1226 2018-01-17 Jim Wilson <jimw@sifive.com>
1228 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1230 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1232 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1233 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1234 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1235 (cpu_flags): Add CpuIBT, CpuSHSTK.
1236 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1237 (i386_cpu_flags): Add cpuibt, cpushstk.
1238 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1239 * i386-init.h: Regenerate.
1240 * i386-tbl.h: Likewise.
1242 2018-01-16 Nick Clifton <nickc@redhat.com>
1244 * po/pt_BR.po: Updated Brazilian Portugese translation.
1245 * po/de.po: Updated German translation.
1247 2018-01-15 Jim Wilson <jimw@sifive.com>
1249 * riscv-opc.c (match_c_nop): New.
1250 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1252 2018-01-15 Nick Clifton <nickc@redhat.com>
1254 * po/uk.po: Updated Ukranian translation.
1256 2018-01-13 Nick Clifton <nickc@redhat.com>
1258 * po/opcodes.pot: Regenerated.
1260 2018-01-13 Nick Clifton <nickc@redhat.com>
1262 * configure: Regenerate.
1264 2018-01-13 Nick Clifton <nickc@redhat.com>
1266 2.30 branch created.
1268 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1270 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1271 * i386-tbl.h: Regenerate.
1273 2018-01-10 Jan Beulich <jbeulich@suse.com>
1275 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1276 * i386-tbl.h: Re-generate.
1278 2018-01-10 Jan Beulich <jbeulich@suse.com>
1280 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1281 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1282 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1283 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1284 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1285 Disp8MemShift of AVX512VL forms.
1286 * i386-tbl.h: Re-generate.
1288 2018-01-09 Jim Wilson <jimw@sifive.com>
1290 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1291 then the hi_addr value is zero.
1293 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1295 * arm-dis.c (arm_opcodes): Add csdb.
1296 (thumb32_opcodes): Add csdb.
1298 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1300 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1301 * aarch64-asm-2.c: Regenerate.
1302 * aarch64-dis-2.c: Regenerate.
1303 * aarch64-opc-2.c: Regenerate.
1305 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1308 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1309 Remove AVX512 vmovd with 64-bit operands.
1310 * i386-tbl.h: Regenerated.
1312 2018-01-05 Jim Wilson <jimw@sifive.com>
1314 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1317 2018-01-03 Alan Modra <amodra@gmail.com>
1319 Update year range in copyright notice of all files.
1321 2018-01-02 Jan Beulich <jbeulich@suse.com>
1323 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1324 and OPERAND_TYPE_REGZMM entries.
1326 For older changes see ChangeLog-2017
1328 Copyright (C) 2018 Free Software Foundation, Inc.
1330 Copying and distribution of this file, with or without modification,
1331 are permitted in any medium without royalty provided the copyright
1332 notice and this notice are preserved.
1338 version-control: never