opcodes/ChangeLog

   1 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
   2
   3         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
   4         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
   5         (operand_general_constraint_met_p): validate
   6         AARCH64_OPND_UNDEFINED.
   7         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
   8         for FLD_imm16_2.
   9         * aarch64-asm-2.c: Regenerated.
  10         * aarch64-dis-2.c: Regenerated.
  11         * aarch64-opc-2.c: Regenerated.
  12
  13 2020-04-29  Nick Clifton  <nickc@redhat.com>
  14
  15         PR 22699
  16         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
  17         and SETRC insns.
  18
  19 2020-04-29  Nick Clifton  <nickc@redhat.com>
  20
  21         * po/sv.po: Updated Swedish translation.
  22
  23 2020-04-29  Nick Clifton  <nickc@redhat.com>
  24
  25         PR 22699
  26         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
  27         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
  28         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
  29         IMM0_8U case.
  30
  31 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  32
  33         PR 25848
  34         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  35         cmpi only on m68020up and cpu32.
  36
  37 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  38
  39         * aarch64-asm.c (aarch64_ins_none): New.
  40         * aarch64-asm.h (ins_none): New declaration.
  41         * aarch64-dis.c (aarch64_ext_none): New.
  42         * aarch64-dis.h (ext_none): New declaration.
  43         * aarch64-opc.c (aarch64_print_operand): Update case for
  44         AARCH64_OPND_BARRIER_PSB.
  45         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  46         (AARCH64_OPERANDS): Update inserter/extracter for
  47         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  48         * aarch64-asm-2.c: Regenerated.
  49         * aarch64-dis-2.c: Regenerated.
  50         * aarch64-opc-2.c: Regenerated.
  51
  52 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  53
  54         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  55         (aarch64_feature_ras, RAS): Likewise.
  56         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  57         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  58         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  59         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  60         * aarch64-asm-2.c: Regenerated.
  61         * aarch64-dis-2.c: Regenerated.
  62         * aarch64-opc-2.c: Regenerated.
  63
  64 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  65
  66         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  67         (print_insn_neon): Support disassembly of conditional
  68         instructions.
  69
  70 2020-02-16  David Faust  <david.faust@oracle.com>
  71
  72         * bpf-desc.c: Regenerate.
  73         * bpf-desc.h: Likewise.
  74         * bpf-opc.c: Regenerate.
  75         * bpf-opc.h: Likewise.
  76
  77 2020-04-07  Lili Cui  <lili.cui@intel.com>
  78
  79         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  80         (prefix_table): New instructions (see prefixes above).
  81         (rm_table): Likewise
  82         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
  83         CPU_ANY_TSXLDTRK_FLAGS.
  84         (cpu_flags): Add CpuTSXLDTRK.
  85         * i386-opc.h (enum): Add CpuTSXLDTRK.
  86         (i386_cpu_flags): Add cputsxldtrk.
  87         * i386-opc.tbl: Add XSUSPLDTRK insns.
  88         * i386-init.h: Regenerate.
  89         * i386-tbl.h: Likewise.
  90
  91 2020-04-02  Lili Cui  <lili.cui@intel.com>
  92
  93         * i386-dis.c (prefix_table): New instructions serialize.
  94         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
  95         CPU_ANY_SERIALIZE_FLAGS.
  96         (cpu_flags): Add CpuSERIALIZE.
  97         * i386-opc.h (enum): Add CpuSERIALIZE.
  98         (i386_cpu_flags): Add cpuserialize.
  99         * i386-opc.tbl: Add SERIALIZE insns.
 100         * i386-init.h: Regenerate.
 101         * i386-tbl.h: Likewise.
 102
 103 2020-03-26  Alan Modra  <amodra@gmail.com>
 104
 105         * disassemble.h (opcodes_assert): Declare.
 106         (OPCODES_ASSERT): Define.
 107         * disassemble.c: Don't include assert.h.  Include opintl.h.
 108         (opcodes_assert): New function.
 109         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 110         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 111         calculate maxlen.  Omit insn decoding when insn length exceeds
 112         maxlen.  Exit from nibble loop when looking for E, before
 113         accessing next data byte.  Move processing of E outside loop.
 114         Replace tests of maxlen in loop with assertions.
 115
 116 2020-03-26  Alan Modra  <amodra@gmail.com>
 117
 118         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 119
 120 2020-03-25  Alan Modra  <amodra@gmail.com>
 121
 122         * z80-dis.c (suffix): Init mybuf.
 123
 124 2020-03-22  Alan Modra  <amodra@gmail.com>
 125
 126         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 127         successflly read from section.
 128
 129 2020-03-22  Alan Modra  <amodra@gmail.com>
 130
 131         * arc-dis.c (find_format): Use ISO C string concatenation rather
 132         than line continuation within a string.  Don't access needs_limm
 133         before testing opcode != NULL.
 134
 135 2020-03-22  Alan Modra  <amodra@gmail.com>
 136
 137         * ns32k-dis.c (print_insn_arg): Update comment.
 138         (print_insn_ns32k): Reduce size of index_offset array, and
 139         initialize, passing -1 to print_insn_arg for args that are not
 140         an index.  Don't exit arg loop early.  Abort on bad arg number.
 141
 142 2020-03-22  Alan Modra  <amodra@gmail.com>
 143
 144         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 145         * s12z-opc.c: Formatting.
 146         (operands_f): Return an int.
 147         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 148         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 149         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 150         (exg_sex_discrim): Likewise.
 151         (create_immediate_operand, create_bitfield_operand),
 152         (create_register_operand_with_size, create_register_all_operand),
 153         (create_register_all16_operand, create_simple_memory_operand),
 154         (create_memory_operand, create_memory_auto_operand): Don't
 155         segfault on malloc failure.
 156         (z_ext24_decode): Return an int status, negative on fail, zero
 157         on success.
 158         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 159         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 160         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 161         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 162         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 163         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 164         (loop_primitive_decode, shift_decode, psh_pul_decode),
 165         (bit_field_decode): Similarly.
 166         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 167         to return value, update callers.
 168         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 169         Don't segfault on NULL operand.
 170         (decode_operation): Return OP_INVALID on first fail.
 171         (decode_s12z): Check all reads, returning -1 on fail.
 172
 173 2020-03-20  Alan Modra  <amodra@gmail.com>
 174
 175         * metag-dis.c (print_insn_metag): Don't ignore status from
 176         read_memory_func.
 177
 178 2020-03-20  Alan Modra  <amodra@gmail.com>
 179
 180         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 181         Initialize parts of buffer not written when handling a possible
 182         2-byte insn at end of section.  Don't attempt decoding of such
 183         an insn by the 4-byte machinery.
 184
 185 2020-03-20  Alan Modra  <amodra@gmail.com>
 186
 187         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 188         partially filled buffer.  Prevent lookup of 4-byte insns when
 189         only VLE 2-byte insns are possible due to section size.  Print
 190         ".word" rather than ".long" for 2-byte leftovers.
 191
 192 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 193
 194         PR 25641
 195         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 196
 197 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-dis.c (X86_64_0D): Rename to ...
 200         (X86_64_0E): ... this.
 201
 202 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 203
 204         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 205         * Makefile.in: Regenerated.
 206
 207 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 210         3-operand pseudos.
 211         * i386-tbl.h: Re-generate.
 212
 213 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 216         vprot*, vpsha*, and vpshl*.
 217         * i386-tbl.h: Re-generate.
 218
 219 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 222         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 223         * i386-tbl.h: Re-generate.
 224
 225 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 228         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 229         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 230         * i386-tbl.h: Re-generate.
 231
 232 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 233
 234         * i386-gen.c (struct template_arg, struct template_instance,
 235         struct template_param, struct template, templates,
 236         parse_template, expand_templates): New.
 237         (process_i386_opcodes): Various local variables moved to
 238         expand_templates. Call parse_template and expand_templates.
 239         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 240         * i386-tbl.h: Re-generate.
 241
 242 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 245         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 246         register and memory source templates. Replace VexW= by VexW*
 247         where applicable.
 248         * i386-tbl.h: Re-generate.
 249
 250 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 251
 252         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 253         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 254         * i386-tbl.h: Re-generate.
 255
 256 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 259         * i386-tbl.h: Re-generate.
 260
 261 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 262
 263         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 264         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 265         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 266         VexW0 on SSE2AVX variants.
 267         (vmovq): Drop NoRex64 from XMM/XMM variants.
 268         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 269         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 270         applicable use VexW0.
 271         * i386-tbl.h: Re-generate.
 272
 273 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 276         * i386-opc.h (Rex64): Delete.
 277         (struct i386_opcode_modifier): Remove rex64 field.
 278         * i386-opc.tbl (crc32): Drop Rex64.
 279         Replace Rex64 with Size64 everywhere else.
 280         * i386-tbl.h: Re-generate.
 281
 282 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-dis.c (OP_E_memory): Exclude recording of used address
 285         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 286         addressed memory operands for MPX insns.
 287
 288 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 291         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 292         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 293         (ptwrite): Split into non-64-bit and 64-bit forms.
 294         * i386-tbl.h: Re-generate.
 295
 296 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 299         template.
 300         * i386-tbl.h: Re-generate.
 301
 302 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 305         (prefix_table): Move vmmcall here. Add vmgexit.
 306         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 307         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 308         (cpu_flags): Add CpuSEV_ES entry.
 309         * i386-opc.h (CpuSEV_ES): New.
 310         (union i386_cpu_flags): Add cpusev_es field.
 311         * i386-opc.tbl (vmgexit): New.
 312         * i386-init.h, i386-tbl.h: Re-generate.
 313
 314 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 315
 316         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 317         with MnemonicSize.
 318         * i386-opc.h (IGNORESIZE): New.
 319         (DEFAULTSIZE): Likewise.
 320         (IgnoreSize): Removed.
 321         (DefaultSize): Likewise.
 322         (MnemonicSize): New.
 323         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 324         mnemonicsize.
 325         * i386-opc.tbl (IgnoreSize): New.
 326         (DefaultSize): Likewise.
 327         * i386-tbl.h: Regenerated.
 328
 329 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 330
 331         PR 25627
 332         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 333         instructions.
 334
 335 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 336
 337         PR gas/25622
 338         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 339         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 340         * i386-tbl.h: Regenerated.
 341
 342 2020-02-26  Alan Modra  <amodra@gmail.com>
 343
 344         * aarch64-asm.c: Indent labels correctly.
 345         * aarch64-dis.c: Likewise.
 346         * aarch64-gen.c: Likewise.
 347         * aarch64-opc.c: Likewise.
 348         * alpha-dis.c: Likewise.
 349         * i386-dis.c: Likewise.
 350         * nds32-asm.c: Likewise.
 351         * nfp-dis.c: Likewise.
 352         * visium-dis.c: Likewise.
 353
 354 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 355
 356         * arc-regs.h (int_vector_base): Make it available for all ARC
 357         CPUs.
 358
 359 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 360
 361         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 362         changed.
 363
 364 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 365
 366         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 367         c.mv/c.li if rs1 is zero.
 368
 369 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 370
 371         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 372         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 373         CPU_POPCNT_FLAGS.
 374         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 375         * i386-opc.h (CpuABM): Removed.
 376         (CpuPOPCNT): New.
 377         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 378         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 379         popcnt.  Remove CpuABM from lzcnt.
 380         * i386-init.h: Regenerated.
 381         * i386-tbl.h: Likewise.
 382
 383 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 384
 385         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 386         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 387         VexW1 instead of open-coding them.
 388         * i386-tbl.h: Re-generate.
 389
 390 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.tbl (AddrPrefixOpReg): Define.
 393         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 394         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 395         templates. Drop NoRex64.
 396         * i386-tbl.h: Re-generate.
 397
 398 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 399
 400         PR gas/6518
 401         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 402         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 403         into Intel syntax instance (with Unpsecified) and AT&T one
 404         (without).
 405         (vcvtneps2bf16): Likewise, along with folding the two so far
 406         separate ones.
 407         * i386-tbl.h: Re-generate.
 408
 409 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 410
 411         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 412         CPU_ANY_SSE4A_FLAGS.
 413
 414 2020-02-17  Alan Modra  <amodra@gmail.com>
 415
 416         * i386-gen.c (cpu_flag_init): Correct last change.
 417
 418 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 419
 420         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 421         CPU_ANY_SSE4_FLAGS.
 422
 423 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 424
 425         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 426         (movzx): Likewise.
 427
 428 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 429
 430         PR gas/25438
 431         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 432         destination for Cpu64-only variant.
 433         (movzx): Fold patterns.
 434         * i386-tbl.h: Re-generate.
 435
 436 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 439         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 440         CPU_ANY_SSE4_FLAGS entry.
 441         * i386-init.h: Re-generate.
 442
 443 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 444
 445         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 446         with Unspecified, making the present one AT&T syntax only.
 447         * i386-tbl.h: Re-generate.
 448
 449 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 450
 451         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 452         * i386-tbl.h: Re-generate.
 453
 454 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 455
 456         PR gas/24546
 457         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 458         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 459         Amd64 and Intel64 templates.
 460         (call, jmp): Likewise for far indirect variants. Dro
 461         Unspecified.
 462         * i386-tbl.h: Re-generate.
 463
 464 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 467         * i386-opc.h (ShortForm): Delete.
 468         (struct i386_opcode_modifier): Remove shortform field.
 469         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 470         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 471         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 472         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 473         Drop ShortForm.
 474         * i386-tbl.h: Re-generate.
 475
 476 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 479         fucompi): Drop ShortForm from operand-less templates.
 480         * i386-tbl.h: Re-generate.
 481
 482 2020-02-11  Alan Modra  <amodra@gmail.com>
 483
 484         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 485         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 486         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 487         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 488         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 489
 490 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 491
 492         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 493         (cde_opcodes): Add VCX* instructions.
 494
 495 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 496             Matthew Malcomson  <matthew.malcomson@arm.com>
 497
 498         * arm-dis.c (struct cdeopcode32): New.
 499         (CDE_OPCODE): New macro.
 500         (cde_opcodes): New disassembly table.
 501         (regnames): New option to table.
 502         (cde_coprocs): New global variable.
 503         (print_insn_cde): New
 504         (print_insn_thumb32): Use print_insn_cde.
 505         (parse_arm_disassembler_options): Parse coprocN args.
 506
 507 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 508
 509         PR gas/25516
 510         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 511         with ISA64.
 512         * i386-opc.h (AMD64): Removed.
 513         (Intel64): Likewose.
 514         (AMD64): New.
 515         (INTEL64): Likewise.
 516         (INTEL64ONLY): Likewise.
 517         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 518         * i386-opc.tbl (Amd64): New.
 519         (Intel64): Likewise.
 520         (Intel64Only): Likewise.
 521         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 522         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 523         * i386-tbl.h: Regenerated.
 524
 525 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 526
 527         PR 25469
 528         * z80-dis.c: Add support for GBZ80 opcodes.
 529
 530 2020-02-04  Alan Modra  <amodra@gmail.com>
 531
 532         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 533
 534 2020-02-03  Alan Modra  <amodra@gmail.com>
 535
 536         * m32c-ibld.c: Regenerate.
 537
 538 2020-02-01  Alan Modra  <amodra@gmail.com>
 539
 540         * frv-ibld.c: Regenerate.
 541
 542 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 543
 544         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 545         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 546         (OP_E_memory): Replace xmm_mdq_mode case label by
 547         vex_scalar_w_dq_mode one.
 548         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 549
 550 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 551
 552         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 553         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 554         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 555         (intel_operand_size): Drop vex_w_dq_mode case label.
 556
 557 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 558
 559         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 560         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 561
 562 2020-01-30  Alan Modra  <amodra@gmail.com>
 563
 564         * m32c-ibld.c: Regenerate.
 565
 566 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 567
 568         * bpf-opc.c: Regenerate.
 569
 570 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 573         (dis386): Use them to replace C2/C3 table entries.
 574         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 575         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 576         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 577         * i386-tbl.h: Re-generate.
 578
 579 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 582         forms.
 583         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 584         DefaultSize.
 585         * i386-tbl.h: Re-generate.
 586
 587 2020-01-30  Alan Modra  <amodra@gmail.com>
 588
 589         * tic4x-dis.c (tic4x_dp): Make unsigned.
 590
 591 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 592             Jan Beulich  <jbeulich@suse.com>
 593
 594         PR binutils/25445
 595         * i386-dis.c (MOVSXD_Fixup): New function.
 596         (movsxd_mode): New enum.
 597         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 598         (intel_operand_size): Handle movsxd_mode.
 599         (OP_E_register): Likewise.
 600         (OP_G): Likewise.
 601         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 602         register on movsxd.  Add movsxd with 16-bit destination register
 603         for AMD64 and Intel64 ISAs.
 604         * i386-tbl.h: Regenerated.
 605
 606 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 607
 608         PR 25403
 609         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 610         * aarch64-asm-2.c: Regenerate
 611         * aarch64-dis-2.c: Likewise.
 612         * aarch64-opc-2.c: Likewise.
 613
 614 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-opc.tbl (sysret): Drop DefaultSize.
 617         * i386-tbl.h: Re-generate.
 618
 619 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 620
 621         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 622         Dword.
 623         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 624         * i386-tbl.h: Re-generate.
 625
 626 2020-01-20  Nick Clifton  <nickc@redhat.com>
 627
 628         * po/de.po: Updated German translation.
 629         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 630         * po/uk.po: Updated Ukranian translation.
 631
 632 2020-01-20  Alan Modra  <amodra@gmail.com>
 633
 634         * hppa-dis.c (fput_const): Remove useless cast.
 635
 636 2020-01-20  Alan Modra  <amodra@gmail.com>
 637
 638         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 639
 640 2020-01-18  Nick Clifton  <nickc@redhat.com>
 641
 642         * configure: Regenerate.
 643         * po/opcodes.pot: Regenerate.
 644
 645 2020-01-18  Nick Clifton  <nickc@redhat.com>
 646
 647         Binutils 2.34 branch created.
 648
 649 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 650
 651         * opintl.h: Fix spelling error (seperate).
 652
 653 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 654
 655         * i386-opc.tbl: Add {vex} pseudo prefix.
 656         * i386-tbl.h: Regenerated.
 657
 658 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 659
 660         PR 25376
 661         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 662         (neon_opcodes): Likewise.
 663         (select_arm_features): Make sure we enable MVE bits when selecting
 664         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 665         any architecture.
 666
 667 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 668
 669         * i386-opc.tbl: Drop stale comment from XOP section.
 670
 671 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 672
 673         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 674         (extractps): Add VexWIG to SSE2AVX forms.
 675         * i386-tbl.h: Re-generate.
 676
 677 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 678
 679         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 680         Size64 from and use VexW1 on SSE2AVX forms.
 681         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 682         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 683         * i386-tbl.h: Re-generate.
 684
 685 2020-01-15  Alan Modra  <amodra@gmail.com>
 686
 687         * tic4x-dis.c (tic4x_version): Make unsigned long.
 688         (optab, optab_special, registernames): New file scope vars.
 689         (tic4x_print_register): Set up registernames rather than
 690         malloc'd registertable.
 691         (tic4x_disassemble): Delete optable and optable_special.  Use
 692         optab and optab_special instead.  Throw away old optab,
 693         optab_special and registernames when info->mach changes.
 694
 695 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 696
 697         PR 25377
 698         * z80-dis.c (suffix): Use .db instruction to generate double
 699         prefix.
 700
 701 2020-01-14  Alan Modra  <amodra@gmail.com>
 702
 703         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 704         values to unsigned before shifting.
 705
 706 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 707
 708         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 709         flow instructions.
 710         (print_insn_thumb16, print_insn_thumb32): Likewise.
 711         (print_insn): Initialize the insn info.
 712         * i386-dis.c (print_insn): Initialize the insn info fields, and
 713         detect jumps.
 714
 715 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 716
 717         * arc-opc.c (C_NE): Make it required.
 718
 719 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 720
 721         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 722         reserved register name.
 723
 724 2020-01-13  Alan Modra  <amodra@gmail.com>
 725
 726         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 727         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 728
 729 2020-01-13  Alan Modra  <amodra@gmail.com>
 730
 731         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 732         result of wasm_read_leb128 in a uint64_t and check that bits
 733         are not lost when copying to other locals.  Use uint32_t for
 734         most locals.  Use PRId64 when printing int64_t.
 735
 736 2020-01-13  Alan Modra  <amodra@gmail.com>
 737
 738         * score-dis.c: Formatting.
 739         * score7-dis.c: Formatting.
 740
 741 2020-01-13  Alan Modra  <amodra@gmail.com>
 742
 743         * score-dis.c (print_insn_score48): Use unsigned variables for
 744         unsigned values.  Don't left shift negative values.
 745         (print_insn_score32): Likewise.
 746         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 747
 748 2020-01-13  Alan Modra  <amodra@gmail.com>
 749
 750         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 751
 752 2020-01-13  Alan Modra  <amodra@gmail.com>
 753
 754         * fr30-ibld.c: Regenerate.
 755
 756 2020-01-13  Alan Modra  <amodra@gmail.com>
 757
 758         * xgate-dis.c (print_insn): Don't left shift signed value.
 759         (ripBits): Formatting, use 1u.
 760
 761 2020-01-10  Alan Modra  <amodra@gmail.com>
 762
 763         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 764         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 765
 766 2020-01-10  Alan Modra  <amodra@gmail.com>
 767
 768         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 769         and XRREG value earlier to avoid a shift with negative exponent.
 770         * m10200-dis.c (disassemble): Similarly.
 771
 772 2020-01-09  Nick Clifton  <nickc@redhat.com>
 773
 774         PR 25224
 775         * z80-dis.c (ld_ii_ii): Use correct cast.
 776
 777 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 778
 779         PR 25224
 780         * z80-dis.c (ld_ii_ii): Use character constant when checking
 781         opcode byte value.
 782
 783 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 784
 785         * i386-dis.c (SEP_Fixup): New.
 786         (SEP): Define.
 787         (dis386_twobyte): Use it for sysenter/sysexit.
 788         (enum x86_64_isa): Change amd64 enumerator to value 1.
 789         (OP_J): Compare isa64 against intel64 instead of amd64.
 790         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 791         forms.
 792         * i386-tbl.h: Re-generate.
 793
 794 2020-01-08  Alan Modra  <amodra@gmail.com>
 795
 796         * z8k-dis.c: Include libiberty.h
 797         (instr_data_s): Make max_fetched unsigned.
 798         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 799         Don't exceed byte_info bounds.
 800         (output_instr): Make num_bytes unsigned.
 801         (unpack_instr): Likewise for nibl_count and loop.
 802         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 803         idx unsigned.
 804         * z8k-opc.h: Regenerate.
 805
 806 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 807
 808         * arc-tbl.h (llock): Use 'LLOCK' as class.
 809         (llockd): Likewise.
 810         (scond): Use 'SCOND' as class.
 811         (scondd): Likewise.
 812         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 813         (scondd): Likewise.
 814
 815 2020-01-06  Alan Modra  <amodra@gmail.com>
 816
 817         * m32c-ibld.c: Regenerate.
 818
 819 2020-01-06  Alan Modra  <amodra@gmail.com>
 820
 821         PR 25344
 822         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 823         Peek at next byte to prevent recursion on repeated prefix bytes.
 824         Ensure uninitialised "mybuf" is not accessed.
 825         (print_insn_z80): Don't zero n_fetch and n_used here,..
 826         (print_insn_z80_buf): ..do it here instead.
 827
 828 2020-01-04  Alan Modra  <amodra@gmail.com>
 829
 830         * m32r-ibld.c: Regenerate.
 831
 832 2020-01-04  Alan Modra  <amodra@gmail.com>
 833
 834         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 835
 836 2020-01-04  Alan Modra  <amodra@gmail.com>
 837
 838         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 839
 840 2020-01-04  Alan Modra  <amodra@gmail.com>
 841
 842         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 843
 844 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 845
 846         * aarch64-tbl.h (aarch64_opcode_table): Use
 847         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 848
 849 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 850
 851         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 852         forms of SUDOT and USDOT.
 853
 854 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 855
 856         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 857         uzip{1,2}.
 858         * opcodes/aarch64-dis-2.c: Re-generate.
 859
 860 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 861
 862         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 863         FMMLA encoding.
 864         * opcodes/aarch64-dis-2.c: Re-generate.
 865
 866 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 867
 868         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 869
 870 2020-01-01  Alan Modra  <amodra@gmail.com>
 871
 872         Update year range in copyright notice of all files.
 873
 874 For older changes see ChangeLog-2019
 875 \f
 876 Copyright (C) 2020 Free Software Foundation, Inc.
 877
 878 Copying and distribution of this file, with or without modification,
 879 are permitted in any medium without royalty provided the copyright
 880 notice and this notice are preserved.
 881
 882 Local Variables:
 883 mode: change-log
 884 left-margin: 8
 885 fill-column: 74
 886 version-control: never
 887 End: