1 2006-05-03 Thiemo Seufer <ths@mips.com>
3 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
5 2006-05-02 Thiemo Seufer <ths@mips.com>
6 Nigel Stephens <nigel@mips.com>
7 David Ung <davidu@mips.com>
9 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
10 (print_mips16_insn_arg): Force mips16 to odd addresses.
12 2006-04-30 Thiemo Seufer <ths@mips.com>
13 David Ung <davidu@mips.com>
15 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
17 * mips-dis.c (print_insn_args): Adds udi argument handling.
19 2006-04-28 James E Wilson <wilson@specifix.com>
21 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
24 2006-04-28 Thiemo Seufer <ths@mips.com>
25 David Ung <davidu@mips.com>
26 Nigel Stephens <nigel@mips.com>
28 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
31 2006-04-28 Thiemo Seufer <ths@mips.com>
32 Nigel Stephens <nigel@mips.com>
33 David Ung <davidu@mips.com>
35 * mips-dis.c (print_insn_args): Add mips_opcode argument.
36 (print_insn_mips): Adjust print_insn_args call.
38 2006-04-28 Thiemo Seufer <ths@mips.com>
39 Nigel Stephens <nigel@mips.com>
41 * mips-dis.c (print_insn_args): Print $fcc only for FP
42 instructions, use $cc elsewise.
44 2006-04-28 Thiemo Seufer <ths@mips.com>
45 Nigel Stephens <nigel@mips.com>
47 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
48 Map MIPS16 registers to O32 names.
49 (print_mips16_insn_arg): Use mips16_reg_names.
51 2006-04-26 Julian Brown <julian@codesourcery.com>
53 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
56 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
57 Julian Brown <julian@codesourcery.com>
59 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
60 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
61 Add unified load/store instruction names.
62 (neon_opcode_table): New.
63 (arm_opcodes): Expand meaning of %<bitfield>['`?].
64 (arm_decode_bitfield): New.
65 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
66 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
67 (print_insn_neon): New.
68 (print_insn_arm): Adjust print_insn_coprocessor call. Call
69 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
70 (print_insn_thumb32): Likewise.
72 2006-04-19 Alan Modra <amodra@bigpond.net.au>
74 * Makefile.am: Run "make dep-am".
75 * Makefile.in: Regenerate.
77 2006-04-19 Alan Modra <amodra@bigpond.net.au>
79 * avr-dis.c (avr_operand): Warning fix.
81 * configure: Regenerate.
83 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
85 * po/POTFILES.in: Regenerated.
87 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
90 * avr-dis.c (avr_operand): Arrange for a comment to appear before
91 the symolic form of an address, so that the output of objdump -d
94 2006-04-10 DJ Delorie <dj@redhat.com>
96 * m32c-asm.c: Regenerate.
98 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
100 * Makefile.am: Add install-html target.
101 * Makefile.in: Regenerate.
103 2006-04-06 Nick Clifton <nickc@redhat.com>
105 * po/vi/po: Updated Vietnamese translation.
107 2006-03-31 Paul Koning <ni1d@arrl.net>
109 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
111 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
113 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
114 logic to identify halfword shifts.
116 2006-03-16 Paul Brook <paul@codesourcery.com>
118 * arm-dis.c (arm_opcodes): Rename swi to svc.
119 (thumb_opcodes): Ditto.
121 2006-03-13 DJ Delorie <dj@redhat.com>
123 * m32c-asm.c: Regenerate.
124 * m32c-desc.c: Likewise.
125 * m32c-desc.h: Likewise.
126 * m32c-dis.c: Likewise.
127 * m32c-ibld.c: Likewise.
128 * m32c-opc.c: Likewise.
129 * m32c-opc.h: Likewise.
131 2006-03-10 DJ Delorie <dj@redhat.com>
133 * m32c-desc.c: Regenerate with mul.l, mulu.l.
134 * m32c-opc.c: Likewise.
135 * m32c-opc.h: Likewise.
138 2006-03-09 Nick Clifton <nickc@redhat.com>
140 * po/sv.po: Updated Swedish translation.
142 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
145 * i386-dis.c (REP_Fixup): New function.
146 (AL): Remove duplicate.
151 (indirDXr): Likewise.
154 (dis386): Updated entries of ins, outs, movs, lods and stos.
156 2006-03-05 Nick Clifton <nickc@redhat.com>
158 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
159 signed 32-bit value into an unsigned 32-bit field when the host is
161 * fr30-ibld.c: Regenerate.
162 * frv-ibld.c: Regenerate.
163 * ip2k-ibld.c: Regenerate.
164 * iq2000-asm.c: Regenerate.
165 * iq2000-ibld.c: Regenerate.
166 * m32c-ibld.c: Regenerate.
167 * m32r-ibld.c: Regenerate.
168 * openrisc-ibld.c: Regenerate.
169 * xc16x-ibld.c: Regenerate.
170 * xstormy16-ibld.c: Regenerate.
172 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
174 * xc16x-asm.c: Regenerate.
175 * xc16x-dis.c: Regenerate.
177 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
179 * po/Make-in: Add html target.
181 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
183 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
184 Intel Merom New Instructions.
185 (THREE_BYTE_0): Likewise.
186 (THREE_BYTE_1): Likewise.
187 (three_byte_table): Likewise.
188 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
189 THREE_BYTE_1 for entry 0x3a.
190 (twobyte_has_modrm): Updated.
191 (twobyte_uses_SSE_prefix): Likewise.
192 (print_insn): Handle 3-byte opcodes used by Intel Merom New
195 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
197 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
198 (v9_hpriv_reg_names): New table.
199 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
200 New cases '$' and '%' for read/write hyperprivileged register.
201 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
202 window handling and rdhpr/wrhpr instructions.
204 2006-02-24 DJ Delorie <dj@redhat.com>
206 * m32c-desc.c: Regenerate with linker relaxation attributes.
207 * m32c-desc.h: Likewise.
208 * m32c-dis.c: Likewise.
209 * m32c-opc.c: Likewise.
211 2006-02-24 Paul Brook <paul@codesourcery.com>
213 * arm-dis.c (arm_opcodes): Add V7 instructions.
214 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
215 (print_arm_address): New function.
216 (print_insn_arm): Use it. Add 'P' and 'U' cases.
217 (psr_name): New function.
218 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
220 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
222 * ia64-opc-i.c (bXc): New.
224 (OpX2TaTbYaXcC): Likewise.
227 (ia64_opcodes_i): Add instructions for tf.
229 * ia64-opc.h (IMMU5b): New.
231 * ia64-asmtab.c: Regenerated.
233 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
235 * ia64-gen.c: Update copyright years.
236 * ia64-opc-b.c: Likewise.
238 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
240 * ia64-gen.c (lookup_regindex): Handle ".vm".
241 (print_dependency_table): Handle '\"'.
243 * ia64-ic.tbl: Updated from SDM 2.2.
244 * ia64-raw.tbl: Likewise.
245 * ia64-waw.tbl: Likewise.
246 * ia64-asmtab.c: Regenerated.
248 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
250 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
251 Anil Paranjape <anilp1@kpitcummins.com>
252 Shilin Shakti <shilins@kpitcummins.com>
254 * xc16x-desc.h: New file
255 * xc16x-desc.c: New file
256 * xc16x-opc.h: New file
257 * xc16x-opc.c: New file
258 * xc16x-ibld.c: New file
259 * xc16x-asm.c: New file
260 * xc16x-dis.c: New file
261 * Makefile.am: Entries for xc16x
262 * Makefile.in: Regenerate
263 * cofigure.in: Add xc16x target information.
264 * configure: Regenerate.
265 * disassemble.c: Add xc16x target information.
267 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
269 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
272 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
274 * i386-dis.c ('Z'): Add a new macro.
275 (dis386_twobyte): Use "movZ" for control register moves.
277 2006-02-10 Nick Clifton <nickc@redhat.com>
279 * iq2000-asm.c: Regenerate.
281 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
283 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
285 2006-01-26 David Ung <davidu@mips.com>
287 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
288 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
289 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
290 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
291 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
293 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
295 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
296 ld_d_r, pref_xd_cb): Use signed char to hold data to be
298 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
299 buffer overflows when disassembling instructions like
301 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
302 operand, if the offset is negative.
304 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
306 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
307 unsigned char to hold data to be disassembled.
309 2006-01-17 Andreas Schwab <schwab@suse.de>
312 * disassemble.c (disassemble_init_for_target): Set
313 disassembler_needs_relocs for bfd_arch_arm.
315 2006-01-16 Paul Brook <paul@codesourcery.com>
317 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
318 f?add?, and f?sub? instructions.
320 2006-01-16 Nick Clifton <nickc@redhat.com>
322 * po/zh_CN.po: New Chinese (simplified) translation.
323 * configure.in (ALL_LINGUAS): Add "zh_CH".
324 * configure: Regenerate.
326 2006-01-05 Paul Brook <paul@codesourcery.com>
328 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
330 2006-01-06 DJ Delorie <dj@redhat.com>
332 * m32c-desc.c: Regenerate.
333 * m32c-opc.c: Regenerate.
334 * m32c-opc.h: Regenerate.
336 2006-01-03 DJ Delorie <dj@redhat.com>
338 * cgen-ibld.in (extract_normal): Avoid memory range errors.
339 * m32c-ibld.c: Regenerated.
341 For older changes see ChangeLog-2005
347 version-control: never