opcodes/ChangeLog

   1 2021-03-10  Jan Beulich  <jbeulich@suse.com>
   2
   3         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
   4         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
   5         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
   6         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
   7         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
   8         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
   9         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
  10         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
  11         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
  12         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
  13         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
  14         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
  15         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
  16         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
  17         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
  18         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
  19         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
  20         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
  21         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
  22         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
  23         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
  24         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
  25         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
  26         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
  27         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
  28         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
  29         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
  30         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
  31         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
  32         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
  33         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
  34         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
  35         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
  36         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
  37         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
  38         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
  39         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
  40         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
  41         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
  42         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
  43         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
  44         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
  45         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
  46         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
  47         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
  48         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
  49         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
  50         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
  51         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
  52         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
  53         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
  54         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
  55         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
  56         VEX_W_0F99_P_2_LEN_0): Delete.
  57         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
  58         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
  59         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
  60         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
  61         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
  62         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
  63         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
  64         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
  65         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
  66         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
  67         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
  68         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
  69         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
  70         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
  71         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
  72         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
  73         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
  74         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
  75         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
  76         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
  77         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
  78         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
  79         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
  80         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
  81         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
  82         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
  83         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
  84         (prefix_table): No longer link to vex_len_table[] for opcodes
  85         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
  86         0F92, 0F93, 0F98, and 0F99.
  87         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
  88         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
  89         0F98, and 0F99.
  90         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
  91         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
  92         0F98, and 0F99.
  93         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
  94         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
  95         0F98, and 0F99.
  96         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
  97         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
  98         0F98, and 0F99.
  99
 100 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 101
 102         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 103         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 104         REG_VEX_0F73_M_0 respectively.
 105         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 106         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 107         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 108         MOD_VEX_0F73_REG_7): Delete.
 109         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 110         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 111         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 112         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 113         PREFIX_VEX_0F3AF0_L_0 respectively.
 114         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 115         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 116         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 117         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 118         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 119         VEX_LEN_0F38F7): New.
 120         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 121         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 122         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 123         0F38F3.
 124         (prefix_table): No longer link to vex_len_table[] for opcodes
 125         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 126         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 127         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 128         0F38F6, 0F38F7, and 0F3AF0.
 129         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 130         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 131         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 132         0F73.
 133
 134 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 135
 136         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 137         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 138         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 139         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 140         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 141         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 142         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 143         73.
 144         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 145         0F72, and 0F73.
 146         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 147         0F73.
 148
 149 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 150
 151         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 152         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 153         (reg_table): Don't link to mod_table[] where not needed. Add
 154         PREFIX_IGNORED to nop entries.
 155         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 156         (mod_table): Add nop entries next to prefetch ones. Drop
 157         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 158         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 159         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 160         PREFIX_OPCODE from endbr* entries.
 161         (get_valid_dis386): Also consider entry's name when zapping
 162         vindex.
 163         (print_insn): Handle PREFIX_IGNORED.
 164
 165 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 166
 167         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 168         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 169         element.
 170         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 171         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 172         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 173         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 174         (struct i386_opcode_modifier): Delete notrackprefixok,
 175         islockable, hleprefixok, and repprefixok fields. Add prefixok
 176         field.
 177         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 178         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 179         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 180         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 181         Replace HLEPrefixOk.
 182         * opcodes/i386-tbl.h: Re-generate.
 183
 184 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 185
 186         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 187         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 188         64-bit form.
 189         * opcodes/i386-tbl.h: Re-generate.
 190
 191 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 194         for {} instead of {0}. Don't look for '0'.
 195         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 196         size specifiers.
 197
 198 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 199
 200         PR 27158
 201         * riscv-dis.c (print_insn_args): Updated encoding macros.
 202         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 203         (match_c_addi16sp): Updated encoding macros.
 204         (match_c_lui): Likewise.
 205         (match_c_lui_with_hint): Likewise.
 206         (match_c_addi4spn): Likewise.
 207         (match_c_slli): Likewise.
 208         (match_slli_as_c_slli): Likewise.
 209         (match_c_slli64): Likewise.
 210         (match_srxi_as_c_srxi): Likewise.
 211         (riscv_insn_types): Added .insn css/cl/cs.
 212
 213 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 214
 215         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 216         (default_priv_spec): Updated type to riscv_spec_class.
 217         (parse_riscv_dis_option): Updated.
 218         * riscv-opc.c: Moved stuff and make the file tidy.
 219
 220 2021-02-17  Alan Modra  <amodra@gmail.com>
 221
 222         * wasm32-dis.c: Include limits.h.
 223         (CHAR_BIT): Provide backup define.
 224         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 225         Correct signed overflow checking.
 226
 227 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 230         * i386-tbl.h: Re-generate.
 231
 232 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 233
 234         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 235         Oword.
 236         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 237
 238 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 239
 240         * s390-mkopc.c (main): Accept arch14 as cpu string.
 241         * s390-opc.txt: Add new arch14 instructions.
 242
 243 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 244
 245         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 246         favour of LIBINTL.
 247         * configure: Regenerated.
 248
 249 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 250
 251         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 252         * tic54x-opc.c (regs): Rename to ...
 253         (tic54x_regs): ... this.
 254         (mmregs): Rename to ...
 255         (tic54x_mmregs): ... this.
 256         (condition_codes): Rename to ...
 257         (tic54x_condition_codes): ... this.
 258         (cc2_codes): Rename to ...
 259         (tic54x_cc2_codes): ... this.
 260         (cc3_codes): Rename to ...
 261         (tic54x_cc3_codes): ... this.
 262         (status_bits): Rename to ...
 263         (tic54x_status_bits): ... this.
 264         (misc_symbols): Rename to ...
 265         (tic54x_misc_symbols): ... this.
 266
 267 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 268
 269         * riscv-opc.c (MASK_RVB_IMM): Removed.
 270         (riscv_opcodes): Removed zb* instructions.
 271         (riscv_ext_version_table): Removed versions for zb*.
 272
 273 2021-01-26  Alan Modra  <amodra@gmail.com>
 274
 275         * i386-gen.c (parse_template): Ensure entire template_instance
 276         is initialised.
 277
 278 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 279
 280         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 281         (riscv_fpr_names_abi): Likewise.
 282         (riscv_opcodes): Likewise.
 283         (riscv_insn_types): Likewise.
 284
 285 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 286
 287         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 288
 289 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 290
 291         * riscv-dis.c: Comments tidy and improvement.
 292         * riscv-opc.c: Likewise.
 293
 294 2021-01-13  Alan Modra  <amodra@gmail.com>
 295
 296         * Makefile.in: Regenerate.
 297
 298 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 299
 300         PR binutils/26792
 301         * configure.ac: Use GNU_MAKE_JOBSERVER.
 302         * aclocal.m4: Regenerated.
 303         * configure: Likewise.
 304
 305 2021-01-12  Nick Clifton  <nickc@redhat.com>
 306
 307         * po/sr.po: Updated Serbian translation.
 308
 309 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 310
 311         PR ld/27173
 312         * configure: Regenerated.
 313
 314 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 315
 316         * aarch64-asm-2.c: Regenerate.
 317         * aarch64-dis-2.c: Likewise.
 318         * aarch64-opc-2.c: Likewise.
 319         * aarch64-opc.c (aarch64_print_operand):
 320         Delete handling of AARCH64_OPND_CSRE_CSR.
 321         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 322         (CSRE): Likewise.
 323         (_CSRE_INSN): Likewise.
 324         (aarch64_opcode_table): Delete csr.
 325
 326 2021-01-11  Nick Clifton  <nickc@redhat.com>
 327
 328         * po/de.po: Updated German translation.
 329         * po/fr.po: Updated French translation.
 330         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 331         * po/sv.po: Updated Swedish translation.
 332         * po/uk.po: Updated Ukranian translation.
 333
 334 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 335
 336         * configure: Regenerated.
 337
 338 2021-01-09  Nick Clifton  <nickc@redhat.com>
 339
 340         * configure: Regenerate.
 341         * po/opcodes.pot: Regenerate.
 342
 343 2021-01-09  Nick Clifton  <nickc@redhat.com>
 344
 345         * 2.36 release branch crated.
 346
 347 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 348
 349         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 350         (DW, (XRC_MASK): Define.
 351         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 352
 353 2021-01-09  Alan Modra  <amodra@gmail.com>
 354
 355         * configure: Regenerate.
 356
 357 2021-01-08  Nick Clifton  <nickc@redhat.com>
 358
 359         * po/sv.po: Updated Swedish translation.
 360
 361 2021-01-08  Nick Clifton  <nickc@redhat.com>
 362
 363         PR 27129
 364         * aarch64-dis.c (determine_disassembling_preference): Move call to
 365         aarch64_match_operands_constraint outside of the assertion.
 366         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 367         Replace with a return of FALSE.
 368
 369         PR 27139
 370         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 371         core system register.
 372
 373 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 374
 375         * configure: Regenerate.
 376
 377 2021-01-07  Nick Clifton  <nickc@redhat.com>
 378
 379         * po/fr.po: Updated French translation.
 380
 381 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 382
 383         * m68k-opc.c (chkl): Change minimum architecture requirement to
 384         m68020.
 385
 386 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 387
 388         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 389
 390 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 391             Jim Wilson  <jimw@sifive.com>
 392             Andrew Waterman  <andrew@sifive.com>
 393             Maxim Blinov  <maxim.blinov@embecosm.com>
 394             Kito Cheng  <kito.cheng@sifive.com>
 395             Nelson Chu  <nelson.chu@sifive.com>
 396
 397         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 398         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 399
 400 2021-01-01  Alan Modra  <amodra@gmail.com>
 401
 402         Update year range in copyright notice of all files.
 403
 404 For older changes see ChangeLog-2020
 405 \f
 406 Copyright (C) 2021 Free Software Foundation, Inc.
 407
 408 Copying and distribution of this file, with or without modification,
 409 are permitted in any medium without royalty provided the copyright
 410 notice and this notice are preserved.
 411
 412 Local Variables:
 413 mode: change-log
 414 left-margin: 8
 415 fill-column: 74
 416 version-control: never
 417 End: