opcodes/ChangeLog

   1 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
   4         address with the addr32 prefix and without base nor index
   5         registers.
   6
   7 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
   8
   9         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
  10         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
  11         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
  12         (cpu_flags): Add CpuCMOV and CpuFXSR.
  13         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
  14         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
  15         * i386-init.h: Regenerated.
  16         * i386-tbl.h: Likewise.
  17
  18 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
  19
  20         * arc-regs.h: Update auxiliary registers.
  21
  22 2018-08-06  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
  25         (RegIP, RegIZ): Define.
  26         * i386-reg.tbl: Adjust comments.
  27         (rip): Use Qword instead of BaseIndex. Use RegIP.
  28         (eip): Use Dword instead of BaseIndex. Use RegIP.
  29         (riz): Add Qword. Use RegIZ.
  30         (eiz): Add Dword. Use RegIZ.
  31         * i386-tbl.h: Re-generate.
  32
  33 2018-08-03  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
  36         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
  37         vpmovzxdq, vpmovzxwd): Remove NoRex64.
  38         * i386-tbl.h: Re-generate.
  39
  40 2018-08-03  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-gen.c (operand_types): Remove Mem field.
  43         * i386-opc.h (union i386_operand_type): Remove mem field.
  44         * i386-init.h, i386-tbl.h: Re-generate.
  45
  46 2018-08-01  Alan Modra  <amodra@gmail.com>
  47
  48         * po/POTFILES.in: Regenerate.
  49
  50 2018-07-31  Nick Clifton  <nickc@redhat.com>
  51
  52         * po/sv.po: Updated Swedish translation.
  53
  54 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
  57         * i386-init.h, i386-tbl.h: Re-generate.
  58
  59 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-opc.h (ZEROING_MASKING) Rename to ...
  62         (DYNAMIC_MASKING): ... this. Adjust comment.
  63         * i386-opc.tbl (MaskingMorZ): Define.
  64         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
  65         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
  66         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
  67         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
  68         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
  69         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
  70         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
  71         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
  72         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
  73
  74 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-opc.tbl: Use element rather than vector size for AVX512*
  77         scatter/gather insns.
  78         * i386-tbl.h: Re-generate.
  79
  80 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  81
  82         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
  83         (cpu_flags): Drop CpuVREX.
  84         * i386-opc.h (CpuVREX): Delete.
  85         (union i386_cpu_flags): Remove cpuvrex.
  86         * i386-init.h, i386-tbl.h: Re-generate.
  87
  88 2018-07-30  Jim Wilson  <jimw@sifive.com>
  89
  90         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
  91         fields.
  92         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
  93
  94 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
  95
  96         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
  97         * Makefile.in: Regenerated.
  98         * configure.ac: Add C-SKY.
  99         * configure: Regenerated.
 100         * csky-dis.c: New file.
 101         * csky-opc.h: New file.
 102         * disassemble.c (ARCH_csky): Define.
 103         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 104         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 105
 106 2018-07-27  Alan Modra  <amodra@gmail.com>
 107
 108         * ppc-opc.c (insert_sprbat): Correct function parameter and
 109         return type.
 110         (extract_sprbat): Likewise, variable too.
 111
 112 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 113             Alan Modra  <amodra@gmail.com>
 114
 115         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 116         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 117         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 118         support disjointed BAT.
 119         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 120         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 121         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 122
 123 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 124             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 125
 126         * i386-gen.c (adjust_broadcast_modifier): New function.
 127         (process_i386_opcode_modifier): Add an argument for operands.
 128         Adjust the Broadcast value based on operands.
 129         (output_i386_opcode): Pass operand_types to
 130         process_i386_opcode_modifier.
 131         (process_i386_opcodes): Pass NULL as operands to
 132         process_i386_opcode_modifier.
 133         * i386-opc.h (BYTE_BROADCAST): New.
 134         (WORD_BROADCAST): Likewise.
 135         (DWORD_BROADCAST): Likewise.
 136         (QWORD_BROADCAST): Likewise.
 137         (i386_opcode_modifier): Expand broadcast to 3 bits.
 138         * i386-tbl.h: Regenerated.
 139
 140 2018-07-24  Alan Modra  <amodra@gmail.com>
 141
 142         PR 23430
 143         * or1k-desc.h: Regenerate.
 144
 145 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 148         vcvtusi2ss, and vcvtusi2sd.
 149         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 150         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 151         * i386-tbl.h: Re-generate.
 152
 153 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 154
 155         * arc-opc.c (extract_w6): Fix extending the sign.
 156
 157 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 158
 159         * arc-tbl.h (vewt): Allow it for ARC EM family.
 160
 161 2018-07-23  Alan Modra  <amodra@gmail.com>
 162
 163         PR 23419
 164         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 165         opcode variants for mtspr/mfspr encodings.
 166
 167 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 168             Maciej W. Rozycki  <macro@mips.com>
 169
 170         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 171         loongson3a descriptors.
 172         (parse_mips_ase_option): Handle -M loongson-mmi option.
 173         (print_mips_disassembler_options): Document -M loongson-mmi.
 174         * mips-opc.c (LMMI): New macro.
 175         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 176         instructions.
 177
 178 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 181         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 182         IgnoreSize and [XYZ]MMword where applicable.
 183         * i386-tbl.h: Re-generate.
 184
 185 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 188         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 189         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 190         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 191         * i386-tbl.h: Re-generate.
 192
 193 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 196         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 197         VPCLMULQDQ templates into their respective AVX512VL counterparts
 198         where possible, using Disp8ShiftVL and CheckRegSize instead of
 199         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 200         * i386-tbl.h: Re-generate.
 201
 202 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 203
 204         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 205         AVX512VL counterparts where possible, using Disp8ShiftVL and
 206         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 207         IgnoreSize) as appropriate.
 208         * i386-tbl.h: Re-generate.
 209
 210 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 211
 212         * i386-opc.tbl: Fold AVX512BW templates into their respective
 213         AVX512VL counterparts where possible, using Disp8ShiftVL and
 214         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 215         IgnoreSize) as appropriate.
 216         * i386-tbl.h: Re-generate.
 217
 218 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 219
 220         * i386-opc.tbl: Fold AVX512CD templates into their respective
 221         AVX512VL counterparts where possible, using Disp8ShiftVL and
 222         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 223         IgnoreSize) as appropriate.
 224         * i386-tbl.h: Re-generate.
 225
 226 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-opc.h (DISP8_SHIFT_VL): New.
 229         * i386-opc.tbl (Disp8ShiftVL):  Define.
 230         (various): Fold AVX512VL templates into their respective
 231         AVX512F counterparts where possible, using Disp8ShiftVL and
 232         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 233         IgnoreSize) as appropriate.
 234         * i386-tbl.h: Re-generate.
 235
 236 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 237
 238         * Makefile.am: Change dependencies and rule for
 239         $(srcdir)/i386-init.h.
 240         * Makefile.in: Re-generate.
 241         * i386-gen.c (process_i386_opcodes): New local variable
 242         "marker". Drop opening of input file. Recognize marker and line
 243         number directives.
 244         * i386-opc.tbl (OPCODE_I386_H): Define.
 245         (i386-opc.h): Include it.
 246         (None): Undefine.
 247
 248 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 249
 250         PR gas/23418
 251         * i386-opc.h (Byte): Update comments.
 252         (Word): Likewise.
 253         (Dword): Likewise.
 254         (Fword): Likewise.
 255         (Qword): Likewise.
 256         (Tbyte): Likewise.
 257         (Xmmword): Likewise.
 258         (Ymmword): Likewise.
 259         (Zmmword): Likewise.
 260         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 261         vcvttps2uqq.
 262         * i386-tbl.h: Regenerated.
 263
 264 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 265
 266         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 267         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 268         * aarch64-asm-2.c: Regenerate.
 269         * aarch64-dis-2.c: Regenerate.
 270         * aarch64-opc-2.c: Regenerate.
 271
 272 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 273
 274         PR binutils/23192
 275         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 276         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 277         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 278         sqdmulh, sqrdmulh): Use Em16.
 279
 280 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 281
 282         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 283         csdb together with them.
 284         (thumb32_opcodes): Likewise.
 285
 286 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 287
 288         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 289         requiring 32-bit registers as operands 2 and 3. Improve
 290         comments.
 291         (mwait, mwaitx): Fold templates. Improve comments.
 292         OPERAND_TYPE_INOUTPORTREG.
 293         * i386-tbl.h: Re-generate.
 294
 295 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 296
 297         * i386-gen.c (operand_type_init): Remove
 298         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 299         OPERAND_TYPE_INOUTPORTREG.
 300         * i386-init.h: Re-generate.
 301
 302 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 305         (wrssq, wrussq): Add Qword.
 306         * i386-tbl.h: Re-generate.
 307
 308 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-opc.h: Rename OTMax to OTNum.
 311         (OTNumOfUints): Adjust calculation.
 312         (OTUnused): Directly alias to OTNum.
 313
 314 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 315
 316         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 317         `reg_xys'.
 318         (lea_reg_xys): Likewise.
 319         (print_insn_loop_primitive): Rename `reg' local variable to
 320         `reg_dxy'.
 321
 322 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 323
 324         PR binutils/23242
 325         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 326
 327 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 328
 329         PR binutils/23369
 330         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 331         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 332
 333 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 334
 335         PR tdep/8282
 336         * mips-dis.c (mips_option_arg_t): New enumeration.
 337         (mips_options): New variable.
 338         (disassembler_options_mips): New function.
 339         (print_mips_disassembler_options): Reimplement in terms of
 340         `disassembler_options_mips'.
 341         * arm-dis.c (disassembler_options_arm): Adapt to using the
 342         `disasm_options_and_args_t' structure.
 343         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 344         * s390-dis.c (disassembler_options_s390): Likewise.
 345
 346 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 347
 348         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 349         expected result.
 350         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 351         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 352         * testsuite/ld-arm/tls-longplt.d: Likewise.
 353
 354 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 355
 356         PR binutils/23192
 357         * aarch64-asm-2.c: Regenerate.
 358         * aarch64-dis-2.c: Likewise.
 359         * aarch64-opc-2.c: Likewise.
 360         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 361         * aarch64-opc.c (operand_general_constraint_met_p,
 362         aarch64_print_operand): Likewise.
 363         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 364         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 365         fmlal2, fmlsl2.
 366         (AARCH64_OPERANDS): Add Em2.
 367
 368 2018-06-26  Nick Clifton  <nickc@redhat.com>
 369
 370         * po/uk.po: Updated Ukranian translation.
 371         * po/de.po: Updated German translation.
 372         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 373
 374 2018-06-26  Nick Clifton  <nickc@redhat.com>
 375
 376         * nfp-dis.c: Fix spelling mistake.
 377
 378 2018-06-24  Nick Clifton  <nickc@redhat.com>
 379
 380         * configure: Regenerate.
 381         * po/opcodes.pot: Regenerate.
 382
 383 2018-06-24  Nick Clifton  <nickc@redhat.com>
 384
 385         2.31 branch created.
 386
 387 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 388
 389         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 390         * aarch64-asm-2.c: Regenerate.
 391         * aarch64-dis-2.c: Likewise.
 392
 393 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 394
 395         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 396         `-M ginv' option description.
 397
 398 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 399
 400         PR gas/23305
 401         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 402         la and lla.
 403
 404 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 405
 406         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 407         * configure.ac: Remove AC_PREREQ.
 408         * Makefile.in: Re-generate.
 409         * aclocal.m4: Re-generate.
 410         * configure: Re-generate.
 411
 412 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 413
 414         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 415         mips64r6 descriptors.
 416         (parse_mips_ase_option): Handle -Mginv option.
 417         (print_mips_disassembler_options): Document -Mginv.
 418         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 419         (GINV): New macro.
 420         (mips_opcodes): Define ginvi and ginvt.
 421
 422 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 423             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 424
 425         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 426         * mips-opc.c (CRC, CRC64): New macros.
 427         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 428         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 429         crc32cd for CRC64.
 430
 431 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 432
 433         PR 20319
 434         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 435         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 436
 437 2018-06-06  Alan Modra  <amodra@gmail.com>
 438
 439         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 440         setjmp.  Move init for some other vars later too.
 441
 442 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 443
 444         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 445         (dis_private): Add new fields for property section tracking.
 446         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 447         (xtensa_instruction_fits): New functions.
 448         (fetch_data): Bump minimal fetch size to 4.
 449         (print_insn_xtensa): Make struct dis_private static.
 450         Load and prepare property table on section change.
 451         Don't disassemble literals. Don't disassemble instructions that
 452         cross property table boundaries.
 453
 454 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 455
 456         * configure: Regenerated.
 457
 458 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 461         * i386-tbl.h: Re-generate.
 462
 463 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 464
 465         * i386-opc.tbl (sldt, str): Add NoRex64.
 466         * i386-tbl.h: Re-generate.
 467
 468 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.tbl (invpcid): Add Oword.
 471         * i386-tbl.h: Re-generate.
 472
 473 2018-06-01  Alan Modra  <amodra@gmail.com>
 474
 475         * sysdep.h (_bfd_error_handler): Don't declare.
 476         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 477         * rl78-decode.opc: Likewise.
 478         * msp430-decode.c: Regenerate.
 479         * rl78-decode.c: Regenerate.
 480
 481 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 482
 483         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 484         * i386-init.h : Regenerated.
 485
 486 2018-05-25  Alan Modra  <amodra@gmail.com>
 487
 488         * Makefile.in: Regenerate.
 489         * po/POTFILES.in: Regenerate.
 490
 491 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 492
 493         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 494         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 495         (insert_bab, extract_bab, insert_btab, extract_btab,
 496         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 497         (BAT, BBA VBA RBS XB6S): Delete macros.
 498         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 499         (BB, BD, RBX, XC6): Update for new macros.
 500         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 501         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 502         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 503         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 504
 505 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 506
 507         * Makefile.am: Add support for s12z architecture.
 508         * configure.ac: Likewise.
 509         * disassemble.c: Likewise.
 510         * disassemble.h: Likewise.
 511         * Makefile.in: Regenerate.
 512         * configure: Regenerate.
 513         * s12z-dis.c: New file.
 514         * s12z.h: New file.
 515
 516 2018-05-18  Alan Modra  <amodra@gmail.com>
 517
 518         * nfp-dis.c: Don't #include libbfd.h.
 519         (init_nfp3200_priv): Use bfd_get_section_contents.
 520         (nit_nfp6000_mecsr_sec): Likewise.
 521
 522 2018-05-17  Nick Clifton  <nickc@redhat.com>
 523
 524         * po/zh_CN.po: Updated simplified Chinese translation.
 525
 526 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 527
 528         PR binutils/23109
 529         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 530         * aarch64-dis-2.c: Regenerate.
 531
 532 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 533
 534         PR binutils/21446
 535         * aarch64-asm.c (opintl.h): Include.
 536         (aarch64_ins_sysreg): Enforce read/write constraints.
 537         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 538         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 539         (F_REG_READ, F_REG_WRITE): New.
 540         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 541         AARCH64_OPND_SYSREG.
 542         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 543         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 544         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 545         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 546         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 547         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 548         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 549         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 550         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 551         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 552         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 553         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 554         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 555         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 556         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 557         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 558         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 559
 560 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 561
 562         PR binutils/21446
 563         * aarch64-dis.c (no_notes: New.
 564         (parse_aarch64_dis_option): Support notes.
 565         (aarch64_decode_insn, print_operands): Likewise.
 566         (print_aarch64_disassembler_options): Document notes.
 567         * aarch64-opc.c (aarch64_print_operand): Support notes.
 568
 569 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 570
 571         PR binutils/21446
 572         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 573         and take error struct.
 574         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 575         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 576         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 577         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 578         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 579         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 580         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 581         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 582         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 583         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 584         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 585         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 586         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 587         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 588         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 589         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 590         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 591         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 592         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 593         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 594         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 595         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 596         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 597         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 598         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 599         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 600         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 601         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 602         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 603         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 604         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 605         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 606         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 607         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 608         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 609         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 610         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 611         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 612         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 613         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 614         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 615         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 616         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 617         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 618         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 619         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 620         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 621         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 622         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 623         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 624         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 625         (determine_disassembling_preference, aarch64_decode_insn,
 626         print_insn_aarch64_word, print_insn_data): Take errors struct.
 627         (print_insn_aarch64): Use errors.
 628         * aarch64-asm-2.c: Regenerate.
 629         * aarch64-dis-2.c: Regenerate.
 630         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 631         boolean in aarch64_insert_operan.
 632         (print_operand_extractor): Likewise.
 633         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 634
 635 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 636
 637         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 638
 639 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 640
 641         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 642
 643 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 644
 645         * cr16-opc.c (cr16_instruction): Comment typo fix.
 646         * hppa-dis.c (print_insn_hppa): Likewise.
 647
 648 2018-05-08  Jim Wilson  <jimw@sifive.com>
 649
 650         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 651         (match_c_slli64, match_srxi_as_c_srxi): New.
 652         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 653         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 654         <c.slli, c.srli, c.srai>: Use match_s_slli.
 655         <c.slli64, c.srli64, c.srai64>: New.
 656
 657 2018-05-08  Alan Modra  <amodra@gmail.com>
 658
 659         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 660         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 661         partition opcode space for index lookup.
 662
 663 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 664
 665         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 666         <insn_length>: ...with this.  Update usage.
 667         Remove duplicate call to *info->memory_error_func.
 668
 669 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 670             H.J. Lu  <hongjiu.lu@intel.com>
 671
 672         * i386-dis.c (Gva): New.
 673         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 674         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 675         (prefix_table): New instructions (see prefix above).
 676         (mod_table): New instructions (see prefix above).
 677         (OP_G): Handle va_mode.
 678         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 679         CPU_MOVDIR64B_FLAGS.
 680         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 681         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 682         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 683         * i386-opc.tbl: Add movidir{i,64b}.
 684         * i386-init.h: Regenerated.
 685         * i386-tbl.h: Likewise.
 686
 687 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 688
 689         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 690         AddrPrefixOpReg.
 691         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 692         (AddrPrefixOpReg): This.
 693         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 694         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 695
 696 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 697
 698         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 699         (vle_num_opcodes): Likewise.
 700         (spe2_num_opcodes): Likewise.
 701         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 702         initialization loop.
 703         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 704         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 705         only once.
 706
 707 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 708
 709         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 710
 711 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 712
 713         Makefile.am: Added nfp-dis.c.
 714         configure.ac: Added bfd_nfp_arch.
 715         disassemble.h: Added print_insn_nfp prototype.
 716         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 717         nfp-dis.c: New, for NFP support.
 718         po/POTFILES.in: Added nfp-dis.c to the list.
 719         Makefile.in: Regenerate.
 720         configure: Regenerate.
 721
 722 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 723
 724         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 725         templates into their base ones.
 726         * i386-tlb.h: Re-generate.
 727
 728 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 731         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 732         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 733         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 734         * i386-init.h: Re-generate.
 735
 736 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 739         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 740         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 741         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 742         comment.
 743         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 744         and CpuRegMask.
 745         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 746         CpuRegMask: Delete.
 747         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 748         cpuregzmm, and cpuregmask.
 749         * i386-init.h: Re-generate.
 750         * i386-tbl.h: Re-generate.
 751
 752 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 755         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 756         * i386-init.h: Re-generate.
 757
 758 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-gen.c (VexImmExt): Delete.
 761         * i386-opc.h (VexImmExt, veximmext): Delete.
 762         * i386-opc.tbl: Drop all VexImmExt uses.
 763         * i386-tlb.h: Re-generate.
 764
 765 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 768         register-only forms.
 769         * i386-tlb.h: Re-generate.
 770
 771 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 772
 773         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 774
 775 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 776
 777         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 778         PREFIX_0F1C.
 779         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 780         (cpu_flags): Add CpuCLDEMOTE.
 781         * i386-init.h: Regenerate.
 782         * i386-opc.h (enum): Add CpuCLDEMOTE,
 783         (i386_cpu_flags): Add cpucldemote.
 784         * i386-opc.tbl: Add cldemote.
 785         * i386-tbl.h: Regenerate.
 786
 787 2018-04-16  Alan Modra  <amodra@gmail.com>
 788
 789         * Makefile.am: Remove sh5 and sh64 support.
 790         * configure.ac: Likewise.
 791         * disassemble.c: Likewise.
 792         * disassemble.h: Likewise.
 793         * sh-dis.c: Likewise.
 794         * sh64-dis.c: Delete.
 795         * sh64-opc.c: Delete.
 796         * sh64-opc.h: Delete.
 797         * Makefile.in: Regenerate.
 798         * configure: Regenerate.
 799         * po/POTFILES.in: Regenerate.
 800
 801 2018-04-16  Alan Modra  <amodra@gmail.com>
 802
 803         * Makefile.am: Remove w65 support.
 804         * configure.ac: Likewise.
 805         * disassemble.c: Likewise.
 806         * disassemble.h: Likewise.
 807         * w65-dis.c: Delete.
 808         * w65-opc.h: Delete.
 809         * Makefile.in: Regenerate.
 810         * configure: Regenerate.
 811         * po/POTFILES.in: Regenerate.
 812
 813 2018-04-16  Alan Modra  <amodra@gmail.com>
 814
 815         * configure.ac: Remove we32k support.
 816         * configure: Regenerate.
 817
 818 2018-04-16  Alan Modra  <amodra@gmail.com>
 819
 820         * Makefile.am: Remove m88k support.
 821         * configure.ac: Likewise.
 822         * disassemble.c: Likewise.
 823         * disassemble.h: Likewise.
 824         * m88k-dis.c: Delete.
 825         * Makefile.in: Regenerate.
 826         * configure: Regenerate.
 827         * po/POTFILES.in: Regenerate.
 828
 829 2018-04-16  Alan Modra  <amodra@gmail.com>
 830
 831         * Makefile.am: Remove i370 support.
 832         * configure.ac: Likewise.
 833         * disassemble.c: Likewise.
 834         * disassemble.h: Likewise.
 835         * i370-dis.c: Delete.
 836         * i370-opc.c: Delete.
 837         * Makefile.in: Regenerate.
 838         * configure: Regenerate.
 839         * po/POTFILES.in: Regenerate.
 840
 841 2018-04-16  Alan Modra  <amodra@gmail.com>
 842
 843         * Makefile.am: Remove h8500 support.
 844         * configure.ac: Likewise.
 845         * disassemble.c: Likewise.
 846         * disassemble.h: Likewise.
 847         * h8500-dis.c: Delete.
 848         * h8500-opc.h: Delete.
 849         * Makefile.in: Regenerate.
 850         * configure: Regenerate.
 851         * po/POTFILES.in: Regenerate.
 852
 853 2018-04-16  Alan Modra  <amodra@gmail.com>
 854
 855         * configure.ac: Remove tahoe support.
 856         * configure: Regenerate.
 857
 858 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 859
 860         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 861         umwait.
 862         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 863         64-bit mode.
 864         * i386-tbl.h: Regenerated.
 865
 866 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 867
 868         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 869         PREFIX_MOD_1_0FAE_REG_6.
 870         (va_mode): New.
 871         (OP_E_register): Use va_mode.
 872         * i386-dis-evex.h (prefix_table):
 873         New instructions (see prefixes above).
 874         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 875         (cpu_flags): Likewise.
 876         * i386-opc.h (enum): Likewise.
 877         (i386_cpu_flags): Likewise.
 878         * i386-opc.tbl: Add umonitor, umwait, tpause.
 879         * i386-init.h: Regenerate.
 880         * i386-tbl.h: Likewise.
 881
 882 2018-04-11  Alan Modra  <amodra@gmail.com>
 883
 884         * opcodes/i860-dis.c: Delete.
 885         * opcodes/i960-dis.c: Delete.
 886         * Makefile.am: Remove i860 and i960 support.
 887         * configure.ac: Likewise.
 888         * disassemble.c: Likewise.
 889         * disassemble.h: Likewise.
 890         * Makefile.in: Regenerate.
 891         * configure: Regenerate.
 892         * po/POTFILES.in: Regenerate.
 893
 894 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 895
 896         PR binutils/23025
 897         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 898         to 0.
 899         (print_insn): Clear vex instead of vex.evex.
 900
 901 2018-04-04  Nick Clifton  <nickc@redhat.com>
 902
 903         * po/es.po: Updated Spanish translation.
 904
 905 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 906
 907         * i386-gen.c (opcode_modifiers): Delete VecESize.
 908         * i386-opc.h (VecESize): Delete.
 909         (struct i386_opcode_modifier): Delete vecesize.
 910         * i386-opc.tbl: Drop VecESize.
 911         * i386-tlb.h: Re-generate.
 912
 913 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 916         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 917         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 918         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 919         * i386-tlb.h: Re-generate.
 920
 921 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 924         Fold AVX512 forms
 925         * i386-tlb.h: Re-generate.
 926
 927 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 928
 929         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 930         (vex_len_table): Drop Y for vcvt*2si.
 931         (putop): Replace plain 'Y' handling by abort().
 932
 933 2018-03-28  Nick Clifton  <nickc@redhat.com>
 934
 935         PR 22988
 936         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 937         instructions with only a base address register.
 938         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 939         handle AARHC64_OPND_SVE_ADDR_R.
 940         (aarch64_print_operand): Likewise.
 941         * aarch64-asm-2.c: Regenerate.
 942         * aarch64_dis-2.c: Regenerate.
 943         * aarch64-opc-2.c: Regenerate.
 944
 945 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 946
 947         * i386-opc.tbl: Drop VecESize from register only insn forms and
 948         memory forms not allowing broadcast.
 949         * i386-tlb.h: Re-generate.
 950
 951 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 952
 953         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 954         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 955         sha256*): Drop Disp<N>.
 956
 957 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 958
 959         * i386-dis.c (EbndS, bnd_swap_mode): New.
 960         (prefix_table): Use EbndS.
 961         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 962         * i386-opc.tbl (bndmov): Move misplaced Load.
 963         * i386-tlb.h: Re-generate.
 964
 965 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 968         templates allowing memory operands and folded ones for register
 969         only flavors.
 970         * i386-tlb.h: Re-generate.
 971
 972 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 973
 974         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 975         256-bit templates. Drop redundant leftover Disp<N>.
 976         * i386-tlb.h: Re-generate.
 977
 978 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 979
 980         * riscv-opc.c (riscv_insn_types): New.
 981
 982 2018-03-13  Nick Clifton  <nickc@redhat.com>
 983
 984         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 985
 986 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 987
 988         * i386-opc.tbl: Add Optimize to clr.
 989         * i386-tbl.h: Regenerated.
 990
 991 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 992
 993         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 994         * i386-opc.h (OldGcc): Removed.
 995         (i386_opcode_modifier): Remove oldgcc.
 996         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 997         instructions for old (<= 2.8.1) versions of gcc.
 998         * i386-tbl.h: Regenerated.
 999
1000 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-opc.h (EVEXDYN): New.
1003         * i386-opc.tbl: Fold various AVX512VL templates.
1004         * i386-tlb.h: Re-generate.
1005
1006 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1007
1008         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1009         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1010         vpexpandd, vpexpandq): Fold AFX512VF templates.
1011         * i386-tlb.h: Re-generate.
1012
1013 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1014
1015         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1016         Fold 128- and 256-bit VEX-encoded templates.
1017         * i386-tlb.h: Re-generate.
1018
1019 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1022         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1023         vpexpandd, vpexpandq): Fold AVX512F templates.
1024         * i386-tlb.h: Re-generate.
1025
1026 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1027
1028         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1029         64-bit templates. Drop Disp<N>.
1030         * i386-tlb.h: Re-generate.
1031
1032 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1033
1034         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1035         and 256-bit templates.
1036         * i386-tlb.h: Re-generate.
1037
1038 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1039
1040         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1041         * i386-tlb.h: Re-generate.
1042
1043 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1044
1045         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1046         Drop NoAVX.
1047         * i386-tlb.h: Re-generate.
1048
1049 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1050
1051         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1052         * i386-tlb.h: Re-generate.
1053
1054 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1055
1056         * i386-gen.c (opcode_modifiers): Delete FloatD.
1057         * i386-opc.h (FloatD): Delete.
1058         (struct i386_opcode_modifier): Delete floatd.
1059         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1060         FloatD by D.
1061         * i386-tlb.h: Re-generate.
1062
1063 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1064
1065         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1066
1067 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1070         * i386-tlb.h: Re-generate.
1071
1072 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1075         forms.
1076         * i386-tlb.h: Re-generate.
1077
1078 2018-03-07  Alan Modra  <amodra@gmail.com>
1079
1080         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1081         bfd_arch_rs6000.
1082         * disassemble.h (print_insn_rs6000): Delete.
1083         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1084         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1085         (print_insn_rs6000): Delete.
1086
1087 2018-03-03  Alan Modra  <amodra@gmail.com>
1088
1089         * sysdep.h (opcodes_error_handler): Define.
1090         (_bfd_error_handler): Declare.
1091         * Makefile.am: Remove stray #.
1092         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1093         EDIT" comment.
1094         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1095         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1096         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1097         opcodes_error_handler to print errors.  Standardize error messages.
1098         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1099         and include opintl.h.
1100         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1101         * i386-gen.c: Standardize error messages.
1102         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1103         * Makefile.in: Regenerate.
1104         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1105         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1106         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1107         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1108         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1109         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1110         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1111         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1112         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1113         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1114         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1115         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1116         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1117
1118 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1119
1120         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1121         vpsub[bwdq] instructions.
1122         * i386-tbl.h: Regenerated.
1123
1124 2018-03-01  Alan Modra  <amodra@gmail.com>
1125
1126         * configure.ac (ALL_LINGUAS): Sort.
1127         * configure: Regenerate.
1128
1129 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1130
1131         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1132         macro by assignements.
1133
1134 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1135
1136         PR gas/22871
1137         * i386-gen.c (opcode_modifiers): Add Optimize.
1138         * i386-opc.h (Optimize): New enum.
1139         (i386_opcode_modifier): Add optimize.
1140         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1141         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1142         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1143         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1144         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1145         vpxord and vpxorq.
1146         * i386-tbl.h: Regenerated.
1147
1148 2018-02-26  Alan Modra  <amodra@gmail.com>
1149
1150         * crx-dis.c (getregliststring): Allocate a large enough buffer
1151         to silence false positive gcc8 warning.
1152
1153 2018-02-22  Shea Levy <shea@shealevy.com>
1154
1155         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1156
1157 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1158
1159         * i386-opc.tbl: Add {rex},
1160         * i386-tbl.h: Regenerated.
1161
1162 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1163
1164         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1165         (mips16_opcodes): Replace `M' with `m' for "restore".
1166
1167 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1168
1169         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1170
1171 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1172
1173         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1174         variable to `function_index'.
1175
1176 2018-02-13  Nick Clifton  <nickc@redhat.com>
1177
1178         PR 22823
1179         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1180         about truncation of printing.
1181
1182 2018-02-12  Henry Wong <henry@stuffedcow.net>
1183
1184         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1185
1186 2018-02-05  Nick Clifton  <nickc@redhat.com>
1187
1188         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1189
1190 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1191
1192         * i386-dis.c (enum): Add pconfig.
1193         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1194         (cpu_flags): Add CpuPCONFIG.
1195         * i386-opc.h (enum): Add CpuPCONFIG.
1196         (i386_cpu_flags): Add cpupconfig.
1197         * i386-opc.tbl: Add PCONFIG instruction.
1198         * i386-init.h: Regenerate.
1199         * i386-tbl.h: Likewise.
1200
1201 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1202
1203         * i386-dis.c (enum): Add PREFIX_0F09.
1204         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1205         (cpu_flags): Add CpuWBNOINVD.
1206         * i386-opc.h (enum): Add CpuWBNOINVD.
1207         (i386_cpu_flags): Add cpuwbnoinvd.
1208         * i386-opc.tbl: Add WBNOINVD instruction.
1209         * i386-init.h: Regenerate.
1210         * i386-tbl.h: Likewise.
1211
1212 2018-01-17  Jim Wilson  <jimw@sifive.com>
1213
1214         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1215
1216 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1217
1218         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1219         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1220         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1221         (cpu_flags): Add CpuIBT, CpuSHSTK.
1222         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1223         (i386_cpu_flags): Add cpuibt, cpushstk.
1224         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1225         * i386-init.h: Regenerate.
1226         * i386-tbl.h: Likewise.
1227
1228 2018-01-16  Nick Clifton  <nickc@redhat.com>
1229
1230         * po/pt_BR.po: Updated Brazilian Portugese translation.
1231         * po/de.po: Updated German translation.
1232
1233 2018-01-15  Jim Wilson  <jimw@sifive.com>
1234
1235         * riscv-opc.c (match_c_nop): New.
1236         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1237
1238 2018-01-15  Nick Clifton  <nickc@redhat.com>
1239
1240         * po/uk.po: Updated Ukranian translation.
1241
1242 2018-01-13  Nick Clifton  <nickc@redhat.com>
1243
1244         * po/opcodes.pot: Regenerated.
1245
1246 2018-01-13  Nick Clifton  <nickc@redhat.com>
1247
1248         * configure: Regenerate.
1249
1250 2018-01-13  Nick Clifton  <nickc@redhat.com>
1251
1252         2.30 branch created.
1253
1254 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1255
1256         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1257         * i386-tbl.h: Regenerate.
1258
1259 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1260
1261         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1262         * i386-tbl.h: Re-generate.
1263
1264 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1265
1266         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1267         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1268         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1269         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1270         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1271         Disp8MemShift of AVX512VL forms.
1272         * i386-tbl.h: Re-generate.
1273
1274 2018-01-09  Jim Wilson  <jimw@sifive.com>
1275
1276         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1277         then the hi_addr value is zero.
1278
1279 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1280
1281         * arm-dis.c (arm_opcodes): Add csdb.
1282         (thumb32_opcodes): Add csdb.
1283
1284 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1285
1286         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1287         * aarch64-asm-2.c: Regenerate.
1288         * aarch64-dis-2.c: Regenerate.
1289         * aarch64-opc-2.c: Regenerate.
1290
1291 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1292
1293         PR gas/22681
1294         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1295         Remove AVX512 vmovd with 64-bit operands.
1296         * i386-tbl.h: Regenerated.
1297
1298 2018-01-05  Jim Wilson  <jimw@sifive.com>
1299
1300         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1301         jalr.
1302
1303 2018-01-03  Alan Modra  <amodra@gmail.com>
1304
1305         Update year range in copyright notice of all files.
1306
1307 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1308
1309         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1310         and OPERAND_TYPE_REGZMM entries.
1311
1312 For older changes see ChangeLog-2017
1313 \f
1314 Copyright (C) 2018 Free Software Foundation, Inc.
1315
1316 Copying and distribution of this file, with or without modification,
1317 are permitted in any medium without royalty provided the copyright
1318 notice and this notice are preserved.
1319
1320 Local Variables:
1321 mode: change-log
1322 left-margin: 8
1323 fill-column: 74
1324 version-control: never
1325 End: