1 2020-09-10 Alan Modra <amodra@gmail.com>
3 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
5 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
7 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
10 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
12 * csky-dis.c (csky_output_operand): Add handlers for
13 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
14 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
15 to support FPUV3 instructions.
16 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
17 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
18 OPRND_TYPE_DFLOAT_FMOVI.
19 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
20 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
21 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
22 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
23 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
24 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
25 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
26 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
27 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
28 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
29 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
30 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
31 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
32 (csky_v2_opcodes): Add FPUV3 instructions.
34 2020-09-08 Alex Coplan <alex.coplan@arm.com>
36 * aarch64-dis.c (print_operands): Pass CPU features to
37 aarch64_print_operand().
38 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
39 preferred disassembly of system registers.
40 (SR_RNG): Refactor to use new SR_FEAT2 macro.
47 (SR_EXPAND_EL12): New.
48 (aarch64_sys_regs): Specify which registers are only on
49 A-profile, add R-profile system registers.
53 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
56 2020-09-08 Alex Coplan <alex.coplan@arm.com>
58 * aarch64-tbl.h (aarch64_feature_v8_r): New.
61 (aarch64_opcode_table): Add dfb.
62 * aarch64-opc-2.c: Regenerate.
63 * aarch64-asm-2.c: Regenerate.
64 * aarch64-dis-2.c: Regenerate.
66 2020-09-08 Alex Coplan <alex.coplan@arm.com>
68 * aarch64-dis.c (arch_variant): New.
69 (determine_disassembling_preference): Disassemble according to
71 (select_aarch64_variant): New.
72 (print_insn_aarch64): Set feature set.
74 2020-09-02 Alan Modra <amodra@gmail.com>
76 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
77 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
78 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
79 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
80 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
81 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
82 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
83 for value parameter and update code to suit.
84 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
85 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
87 2020-09-02 Alan Modra <amodra@gmail.com>
89 * i386-dis.c (OP_E_memory): Don't cast to signed type when
91 (get32, get32s): Use unsigned types in shift expressions.
93 2020-09-02 Alan Modra <amodra@gmail.com>
95 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
97 2020-09-02 Alan Modra <amodra@gmail.com>
99 * crx-dis.c: Whitespace.
100 (print_arg): Use unsigned type for longdisp and mask variables,
101 and for left shift constant.
103 2020-09-02 Alan Modra <amodra@gmail.com>
105 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
106 * bpf-ibld.c: Regenerate.
107 * epiphany-ibld.c: Regenerate.
108 * fr30-ibld.c: Regenerate.
109 * frv-ibld.c: Regenerate.
110 * ip2k-ibld.c: Regenerate.
111 * iq2000-ibld.c: Regenerate.
112 * lm32-ibld.c: Regenerate.
113 * m32c-ibld.c: Regenerate.
114 * m32r-ibld.c: Regenerate.
115 * mep-ibld.c: Regenerate.
116 * mt-ibld.c: Regenerate.
117 * or1k-ibld.c: Regenerate.
118 * xc16x-ibld.c: Regenerate.
119 * xstormy16-ibld.c: Regenerate.
121 2020-09-02 Alan Modra <amodra@gmail.com>
123 * bfin-dis.c (MASKBITS): Use SIGNBIT.
125 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
127 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
128 to CSKYV2_ISA_3E3R3 instruction set.
130 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
132 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
134 2020-09-01 Alan Modra <amodra@gmail.com>
136 * mep-ibld.c: Regenerate.
138 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
140 * csky-dis.c (csky_output_operand): Assign dis_info.value for
143 2020-08-30 Alan Modra <amodra@gmail.com>
145 * cr16-dis.c: Formatting.
146 (parameter): Delete struct typedef. Use dwordU instead
148 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
150 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
152 2020-08-29 Alan Modra <amodra@gmail.com>
155 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
156 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
158 2020-08-28 Alan Modra <amodra@gmail.com>
162 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
163 (extract_normal): Likewise.
164 (insert_normal): Likewise, and move past zero length test.
165 (put_insn_int_value): Handle mask for zero length, use 1UL.
166 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
167 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
168 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
169 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
171 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
173 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
174 (csky_dis_info): Add member isa.
175 (csky_find_inst_info): Skip instructions that do not belong to
177 (csky_get_disassembler): Get infomation from attribute section.
178 (print_insn_csky): Set defualt ISA flag.
179 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
180 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
181 isa_flag32'type to unsigned 64 bits.
183 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
185 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
187 2020-08-26 David Faust <david.faust@oracle.com>
189 * bpf-desc.c: Regenerate.
190 * bpf-desc.h: Likewise.
191 * bpf-opc.c: Likewise.
192 * bpf-opc.h: Likewise.
193 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
194 ISA when appropriate.
196 2020-08-25 Alan Modra <amodra@gmail.com>
199 * vax-dis.c (parse_disassembler_options): Always add at least one
200 to entry_addr_total_slots.
202 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
204 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
205 in other CPUs to speed up disassembling.
206 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
207 Change plsli.u16 to plsli.16, change sync's operand format.
209 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
211 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
213 2020-08-21 Nick Clifton <nickc@redhat.com>
215 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
218 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
220 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
222 2020-08-19 Alan Modra <amodra@gmail.com>
224 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
227 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
229 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
230 <xvcvbf16spn>: ...to this.
232 2020-08-12 Alex Coplan <alex.coplan@arm.com>
234 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
236 2020-08-12 Nick Clifton <nickc@redhat.com>
238 * po/sr.po: Updated Serbian translation.
240 2020-08-11 Alan Modra <amodra@gmail.com>
242 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
244 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
246 * aarch64-opc.c (aarch64_print_operand):
247 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
248 (aarch64_sys_reg_supported_p): Function removed.
249 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
250 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
253 2020-08-10 Alan Modra <amodra@gmail.com>
255 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
258 2020-08-10 Alan Modra <amodra@gmail.com>
260 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
261 Enable icbt for power5, miso for power8.
263 2020-08-10 Alan Modra <amodra@gmail.com>
265 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
266 mtvsrd, and similarly for mfvsrd.
268 2020-08-04 Christian Groessler <chris@groessler.org>
269 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
271 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
272 opcodes (special "out" to absolute address).
273 * z8k-opc.h: Regenerate.
275 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
278 * i386-opc.h (Prefix_Disp8): New.
279 (Prefix_Disp16): Likewise.
280 (Prefix_Disp32): Likewise.
281 (Prefix_Load): Likewise.
282 (Prefix_Store): Likewise.
283 (Prefix_VEX): Likewise.
284 (Prefix_VEX3): Likewise.
285 (Prefix_EVEX): Likewise.
286 (Prefix_REX): Likewise.
287 (Prefix_NoOptimize): Likewise.
288 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
289 * i386-tbl.h: Regenerated.
291 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
293 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
294 default case with abort() instead of printing an error message and
295 continuing, to avoid a maybe-uninitialized warning.
297 2020-07-24 Nick Clifton <nickc@redhat.com>
299 * po/de.po: Updated German translation.
301 2020-07-21 Jan Beulich <jbeulich@suse.com>
303 * i386-dis.c (OP_E_memory): Revert previous change.
305 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
308 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
309 without base nor index registers.
311 2020-07-15 Jan Beulich <jbeulich@suse.com>
313 * i386-dis.c (putop): Move 'V' and 'W' handling.
315 2020-07-15 Jan Beulich <jbeulich@suse.com>
317 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
318 construct for push/pop of register.
319 (putop): Honor cond when handling 'P'. Drop handling of plain
322 2020-07-15 Jan Beulich <jbeulich@suse.com>
324 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
325 description. Drop '&' description. Use P for push of immediate,
326 pushf/popf, enter, and leave. Use %LP for lret/retf.
327 (dis386_twobyte): Use P for push/pop of fs/gs.
328 (reg_table): Use P for push/pop. Use @ for near call/jmp.
329 (x86_64_table): Use P for far call/jmp.
330 (putop): Drop handling of 'U' and '&'. Move and adjust handling
331 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
333 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
334 and dqw_mode (unconditional).
336 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
339 * i386-dis.c (OP_E_memory): Without base nor index registers,
340 32-bit displacement to 64 bits.
342 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
344 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
345 faulty double register pair is detected.
347 2020-07-14 Jan Beulich <jbeulich@suse.com>
349 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
351 2020-07-14 Jan Beulich <jbeulich@suse.com>
353 * i386-dis.c (OP_R, Rm): Delete.
354 (MOD_0F24, MOD_0F26): Rename to ...
355 (X86_64_0F24, X86_64_0F26): ... respectively.
356 (dis386): Update 'L' and 'Z' comments.
357 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
359 (mod_table): Move opcode 0F24 and 0F26 entries ...
360 (x86_64_table): ... here.
361 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
364 2020-07-14 Jan Beulich <jbeulich@suse.com>
366 * i386-dis.c (Rd, Rdq, MaskR): Delete.
367 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
368 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
369 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
370 MOD_EVEX_0F387C): New enumerators.
371 (reg_table): Use Edq for rdssp.
372 (prefix_table): Use Edq for incssp.
373 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
374 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
375 ktest*, and kshift*. Use Edq / MaskE for kmov*.
376 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
377 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
378 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
379 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
380 0F3828_P_1 and 0F3838_P_1.
381 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
382 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
384 2020-07-14 Jan Beulich <jbeulich@suse.com>
386 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
387 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
388 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
389 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
390 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
391 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
392 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
393 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
394 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
395 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
396 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
397 (reg_table, prefix_table, three_byte_table, vex_table,
398 vex_len_table, mod_table, rm_table): Replace / remove respective
400 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
401 of PREFIX_DATA in used_prefixes.
403 2020-07-14 Jan Beulich <jbeulich@suse.com>
405 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
406 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
407 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
408 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
409 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
410 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
411 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
412 VEX_W_0F3A33_L_0): Delete.
413 (dis386): Adjust "BW" description.
414 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
415 0F3A31, 0F3A32, and 0F3A33.
416 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
418 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
421 2020-07-14 Jan Beulich <jbeulich@suse.com>
423 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
424 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
425 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
426 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
427 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
428 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
429 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
430 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
431 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
432 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
433 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
434 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
435 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
436 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
437 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
438 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
439 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
440 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
441 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
442 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
443 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
444 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
445 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
446 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
447 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
448 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
449 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
450 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
451 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
452 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
453 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
454 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
455 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
456 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
457 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
458 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
459 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
460 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
461 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
462 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
463 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
464 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
465 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
466 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
467 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
468 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
469 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
470 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
471 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
472 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
473 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
474 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
475 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
476 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
477 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
478 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
479 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
480 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
481 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
482 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
483 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
484 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
485 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
486 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
487 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
488 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
489 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
490 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
491 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
492 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
493 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
494 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
495 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
496 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
497 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
498 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
499 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
500 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
501 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
502 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
503 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
504 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
505 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
506 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
507 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
508 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
509 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
510 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
511 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
512 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
513 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
514 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
515 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
516 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
517 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
518 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
519 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
520 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
521 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
522 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
523 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
524 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
525 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
526 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
527 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
528 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
529 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
530 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
531 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
532 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
533 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
534 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
535 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
536 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
537 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
538 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
539 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
540 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
541 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
542 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
543 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
544 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
545 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
546 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
547 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
548 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
549 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
550 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
551 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
552 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
553 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
554 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
555 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
556 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
557 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
558 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
559 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
560 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
561 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
562 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
563 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
564 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
565 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
566 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
567 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
568 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
569 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
570 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
571 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
572 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
573 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
574 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
575 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
576 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
577 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
578 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
579 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
580 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
581 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
582 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
583 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
584 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
585 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
586 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
587 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
588 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
589 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
590 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
591 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
592 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
593 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
594 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
595 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
596 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
597 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
598 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
599 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
600 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
601 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
602 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
603 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
604 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
605 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
606 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
607 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
608 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
609 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
610 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
611 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
612 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
613 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
614 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
615 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
616 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
617 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
618 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
619 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
620 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
621 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
622 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
623 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
624 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
625 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
626 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
627 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
628 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
629 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
630 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
631 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
632 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
633 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
634 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
635 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
636 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
637 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
638 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
639 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
640 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
641 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
642 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
643 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
644 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
645 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
646 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
647 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
648 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
649 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
650 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
651 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
652 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
653 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
654 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
655 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
656 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
657 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
658 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
659 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
660 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
661 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
662 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
663 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
664 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
665 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
666 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
667 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
668 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
669 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
670 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
671 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
672 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
673 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
674 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
675 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
676 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
677 EVEX_W_0F3A72_P_2): Rename to ...
678 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
679 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
680 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
681 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
682 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
683 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
684 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
685 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
686 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
687 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
688 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
689 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
690 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
691 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
692 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
693 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
694 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
695 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
696 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
697 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
698 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
699 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
700 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
701 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
702 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
703 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
704 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
705 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
706 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
707 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
708 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
709 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
710 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
711 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
712 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
713 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
714 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
715 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
716 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
717 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
718 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
719 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
720 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
721 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
722 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
723 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
724 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
725 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
726 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
727 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
728 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
729 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
730 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
731 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
732 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
733 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
734 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
735 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
736 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
737 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
738 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
739 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
740 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
741 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
742 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
743 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
744 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
745 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
746 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
747 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
748 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
749 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
751 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
752 vex_w_table, mod_table): Replace / remove respective entries.
753 (print_insn): Move up dp->prefix_requirement handling. Handle
755 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
756 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
757 Replace / remove respective entries.
759 2020-07-14 Jan Beulich <jbeulich@suse.com>
761 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
762 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
763 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
764 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
765 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
767 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
768 0F2C, 0F2D, 0F2E, and 0F2F.
769 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
772 2020-07-14 Jan Beulich <jbeulich@suse.com>
774 * i386-dis.c (OP_VexR, VexScalarR): New.
775 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
776 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
777 need_vex_reg): Delete.
778 (prefix_table): Replace VexScalar by VexScalarR and
779 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
780 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
781 (vex_len_table): Replace EXqVexScalarS by EXqS.
782 (get_valid_dis386): Don't set need_vex_reg.
783 (print_insn): Don't initialize need_vex_reg.
784 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
785 q_scalar_swap_mode cases.
786 (OP_EX): Don't check for d_scalar_swap_mode and
788 (OP_VEX): Done check need_vex_reg.
789 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
790 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
791 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
793 2020-07-14 Jan Beulich <jbeulich@suse.com>
795 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
796 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
797 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
798 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
799 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
800 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
801 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
802 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
803 (vex_table): Replace Vex128 by Vex.
804 (vex_len_table): Likewise. Adjust referenced enum names.
805 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
806 referenced enum names.
807 (OP_VEX): Drop vex128_mode and vex256_mode cases.
808 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
810 2020-07-14 Jan Beulich <jbeulich@suse.com>
812 * i386-dis.c (dis386): "LW" description now applies to "DQ".
813 (putop): Handle "DQ". Don't handle "LW" anymore.
814 (prefix_table, mod_table): Replace %LW by %DQ.
815 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
817 2020-07-14 Jan Beulich <jbeulich@suse.com>
819 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
820 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
821 d_scalar_swap_mode case handling. Move shift adjsutment into
822 the case its applicable to.
824 2020-07-14 Jan Beulich <jbeulich@suse.com>
826 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
827 (EXbScalar, EXwScalar): Fold to ...
828 (EXbwUnit): ... this.
829 (b_scalar_mode, w_scalar_mode): Fold to ...
830 (bw_unit_mode): ... this.
831 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
832 w_scalar_mode handling by bw_unit_mode one.
833 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
835 * i386-dis-evex-prefix.h: ... here.
837 2020-07-14 Jan Beulich <jbeulich@suse.com>
839 * i386-dis.c (PCMPESTR_Fixup): Delete.
840 (dis386): Adjust "LQ" description.
841 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
842 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
843 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
844 vpcmpestrm, and vpcmpestri.
845 (putop): Honor "cond" when handling LQ.
846 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
847 vcvtsi2ss and vcvtusi2ss.
848 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
849 vcvtsi2sd and vcvtusi2sd.
851 2020-07-14 Jan Beulich <jbeulich@suse.com>
853 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
854 (simd_cmp_op): Add const.
855 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
856 (CMP_Fixup): Handle VEX case.
857 (prefix_table): Replace VCMP by CMP.
858 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
860 2020-07-14 Jan Beulich <jbeulich@suse.com>
862 * i386-dis.c (MOVBE_Fixup): Delete.
864 (prefix_table): Use Mv for movbe entries.
866 2020-07-14 Jan Beulich <jbeulich@suse.com>
868 * i386-dis.c (CRC32_Fixup): Delete.
869 (prefix_table): Use Eb/Ev for crc32 entries.
871 2020-07-14 Jan Beulich <jbeulich@suse.com>
873 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
874 Conditionalize invocations of "USED_REX (0)".
876 2020-07-14 Jan Beulich <jbeulich@suse.com>
878 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
879 CH, DH, BH, AX, DX): Delete.
880 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
881 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
882 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
884 2020-07-10 Lili Cui <lili.cui@intel.com>
886 * i386-dis.c (TMM): New.
889 (MVexSIBMEM): Likewise.
890 (tmm_mode): Likewise.
891 (vex_sibmem_mode): Likewise.
892 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
893 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
894 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
895 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
896 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
897 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
898 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
899 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
900 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
901 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
902 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
903 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
904 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
905 (PREFIX_VEX_0F3849_X86_64): Likewise.
906 (PREFIX_VEX_0F384B_X86_64): Likewise.
907 (PREFIX_VEX_0F385C_X86_64): Likewise.
908 (PREFIX_VEX_0F385E_X86_64): Likewise.
909 (X86_64_VEX_0F3849): Likewise.
910 (X86_64_VEX_0F384B): Likewise.
911 (X86_64_VEX_0F385C): Likewise.
912 (X86_64_VEX_0F385E): Likewise.
913 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
914 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
915 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
916 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
917 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
918 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
919 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
920 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
921 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
922 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
923 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
924 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
925 (VEX_W_0F3849_X86_64_P_0): Likewise.
926 (VEX_W_0F3849_X86_64_P_2): Likewise.
927 (VEX_W_0F3849_X86_64_P_3): Likewise.
928 (VEX_W_0F384B_X86_64_P_1): Likewise.
929 (VEX_W_0F384B_X86_64_P_2): Likewise.
930 (VEX_W_0F384B_X86_64_P_3): Likewise.
931 (VEX_W_0F385C_X86_64_P_1): Likewise.
932 (VEX_W_0F385E_X86_64_P_0): Likewise.
933 (VEX_W_0F385E_X86_64_P_1): Likewise.
934 (VEX_W_0F385E_X86_64_P_2): Likewise.
935 (VEX_W_0F385E_X86_64_P_3): Likewise.
936 (names_tmm): Likewise.
937 (att_names_tmm): Likewise.
938 (intel_operand_size): Handle void_mode.
939 (OP_XMM): Handle tmm_mode.
942 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
943 CpuAMX_BF16 and CpuAMX_TILE.
944 (operand_type_shorthands): Add RegTMM.
945 (operand_type_init): Likewise.
946 (operand_types): Add Tmmword.
947 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
948 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
949 * i386-opc.h (CpuAMX_INT8): New.
950 (CpuAMX_BF16): Likewise.
951 (CpuAMX_TILE): Likewise.
954 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
955 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
956 (i386_operand_type): Add tmmword.
957 * i386-opc.tbl: Add AMX instructions.
958 * i386-reg.tbl: Add AMX registers.
959 * i386-init.h: Regenerated.
960 * i386-tbl.h: Likewise.
962 2020-07-08 Jan Beulich <jbeulich@suse.com>
964 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
965 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
967 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
968 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
970 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
971 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
972 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
973 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
974 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
975 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
976 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
977 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
978 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
979 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
980 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
981 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
982 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
983 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
984 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
985 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
986 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
987 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
988 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
989 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
990 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
991 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
992 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
993 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
994 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
995 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
996 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
997 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
998 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
999 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1000 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1001 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1002 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1003 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1004 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1005 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1006 (reg_table): Re-order XOP entries. Adjust their operands.
1007 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1008 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1009 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1010 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1011 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1012 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1013 entries by references ...
1014 (vex_len_table): ... to resepctive new entries here. For several
1015 new and existing entries reference ...
1016 (vex_w_table): ... new entries here.
1017 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1019 2020-07-08 Jan Beulich <jbeulich@suse.com>
1021 * i386-dis.c (XMVexScalarI4): Define.
1022 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1023 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1024 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1025 (vex_len_table): Move scalar FMA4 entries ...
1026 (prefix_table): ... here.
1027 (OP_REG_VexI4): Handle scalar_mode.
1028 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1029 * i386-tbl.h: Re-generate.
1031 2020-07-08 Jan Beulich <jbeulich@suse.com>
1033 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1034 Vex_2src_2): Delete.
1035 (OP_VexW, VexW): New.
1036 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1037 for shifts and rotates by register.
1039 2020-07-08 Jan Beulich <jbeulich@suse.com>
1041 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1042 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1043 OP_EX_VexReg): Delete.
1044 (OP_VexI4, VexI4): New.
1045 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1046 (prefix_table): ... here.
1047 (print_insn): Drop setting of vex_w_done.
1049 2020-07-08 Jan Beulich <jbeulich@suse.com>
1051 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1052 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1053 (xop_table): Replace operands of 4-operand insns.
1054 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1056 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1058 * arc-opc.c (insert_rbd): New function.
1061 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1064 2020-07-07 Jan Beulich <jbeulich@suse.com>
1066 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1067 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1068 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1069 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1071 (putop): Handle "BW".
1072 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1073 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1075 * i386-dis-evex-prefix.h: ... here.
1077 2020-07-06 Jan Beulich <jbeulich@suse.com>
1079 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1080 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1081 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1082 VEX_W_0FXOP_09_83): New enumerators.
1083 (xop_table): Reference the above.
1084 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1085 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1086 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1087 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1089 2020-07-06 Jan Beulich <jbeulich@suse.com>
1091 * i386-dis.c (EVEX_W_0F3838_P_1,
1092 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1093 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1094 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1095 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1096 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1097 (putop): Centralize management of last[]. Delete SAVE_LAST.
1098 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1099 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1100 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1101 * i386-dis-evex-prefix.h: here.
1103 2020-07-06 Jan Beulich <jbeulich@suse.com>
1105 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1106 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1107 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1108 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1110 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1111 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1112 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1113 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1114 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1115 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1116 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1117 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1118 these, respectively.
1119 * i386-dis-evex-len.h: Adjust comments.
1120 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1121 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1122 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1123 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1124 MOD_EVEX_0F385B_P_2_W_1 table entries.
1125 * i386-dis-evex-w.h: Reference mod_table[] for
1126 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1129 2020-07-06 Jan Beulich <jbeulich@suse.com>
1131 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1132 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1134 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1135 Likewise. Mark 256-bit entries invalid.
1137 2020-07-06 Jan Beulich <jbeulich@suse.com>
1139 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1140 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1141 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1142 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1143 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1144 PREFIX_EVEX_0F382B): Delete.
1145 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1146 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1147 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1148 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1149 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1151 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1152 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1153 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1154 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1156 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1157 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1158 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1159 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1160 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1161 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1162 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1163 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1164 PREFIX_EVEX_0F382B): Remove table entries.
1165 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1166 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1167 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1169 2020-07-06 Jan Beulich <jbeulich@suse.com>
1171 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1172 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1174 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1175 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1176 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1177 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1180 2020-07-06 Jan Beulich <jbeulich@suse.com>
1182 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1183 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1184 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1185 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1186 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1187 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1188 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1189 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1190 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1193 2020-07-06 Jan Beulich <jbeulich@suse.com>
1195 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1196 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1197 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1199 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1201 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1203 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1205 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1207 2020-07-06 Jan Beulich <jbeulich@suse.com>
1209 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1210 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1211 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1212 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1213 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1214 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1215 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1216 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1217 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1218 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1219 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1220 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1221 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1222 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1223 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1224 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1225 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1226 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1227 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1228 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1229 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1230 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1231 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1232 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1233 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1234 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1235 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1236 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1237 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1238 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1239 (prefix_table): Add EXxEVexR to FMA table entries.
1240 (OP_Rounding): Move abort() invocation.
1241 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1242 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1243 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1244 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1245 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1246 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1247 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1248 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1249 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1250 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1252 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1253 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1254 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1255 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1256 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1257 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1258 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1259 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1260 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1261 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1262 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1263 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1264 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1265 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1266 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1267 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1268 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1269 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1270 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1271 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1272 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1273 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1274 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1275 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1276 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1277 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1278 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1279 Delete table entries.
1280 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1281 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1282 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1285 2020-07-06 Jan Beulich <jbeulich@suse.com>
1287 * i386-dis.c (EXqScalarS): Delete.
1288 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1289 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1291 2020-07-06 Jan Beulich <jbeulich@suse.com>
1293 * i386-dis.c (safe-ctype.h): Include.
1294 (EXdScalar, EXqScalar): Delete.
1295 (d_scalar_mode, q_scalar_mode): Delete.
1296 (prefix_table, vex_len_table): Use EXxmm_md in place of
1297 EXdScalar and EXxmm_mq in place of EXqScalar.
1298 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1299 d_scalar_mode and q_scalar_mode.
1300 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1301 (vmovsd): Use EXxmm_mq.
1303 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1306 * arc-dis.c: Fix spelling mistake.
1307 * po/opcodes.pot: Regenerate.
1309 2020-07-06 Nick Clifton <nickc@redhat.com>
1311 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1312 * po/uk.po: Updated Ukranian translation.
1314 2020-07-04 Nick Clifton <nickc@redhat.com>
1316 * configure: Regenerate.
1317 * po/opcodes.pot: Regenerate.
1319 2020-07-04 Nick Clifton <nickc@redhat.com>
1321 Binutils 2.35 branch created.
1323 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1325 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1326 * i386-opc.h (VexSwapSources): New.
1327 (i386_opcode_modifier): Add vexswapsources.
1328 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1329 with two source operands swapped.
1330 * i386-tbl.h: Regenerated.
1332 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1334 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1335 unprivileged CSR can also be initialized.
1337 2020-06-29 Alan Modra <amodra@gmail.com>
1339 * arm-dis.c: Use C style comments.
1340 * cr16-opc.c: Likewise.
1341 * ft32-dis.c: Likewise.
1342 * moxie-opc.c: Likewise.
1343 * tic54x-dis.c: Likewise.
1344 * s12z-opc.c: Remove useless comment.
1345 * xgate-dis.c: Likewise.
1347 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1349 * i386-opc.tbl: Add a blank line.
1351 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1353 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1354 (VecSIB128): Renamed to ...
1356 (VecSIB256): Renamed to ...
1358 (VecSIB512): Renamed to ...
1360 (VecSIB): Renamed to ...
1362 (i386_opcode_modifier): Replace vecsib with sib.
1363 * i386-opc.tbl (VecSIB128): New.
1364 (VecSIB256): Likewise.
1365 (VecSIB512): Likewise.
1366 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1367 and VecSIB512, respectively.
1369 2020-06-26 Jan Beulich <jbeulich@suse.com>
1371 * i386-dis.c: Adjust description of I macro.
1372 (x86_64_table): Drop use of I.
1373 (float_mem): Replace use of I.
1374 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1376 2020-06-26 Jan Beulich <jbeulich@suse.com>
1378 * i386-dis.c: (print_insn): Avoid straight assignment to
1379 priv.orig_sizeflag when processing -M sub-options.
1381 2020-06-25 Jan Beulich <jbeulich@suse.com>
1383 * i386-dis.c: Adjust description of J macro.
1384 (dis386, x86_64_table, mod_table): Replace J.
1385 (putop): Remove handling of J.
1387 2020-06-25 Jan Beulich <jbeulich@suse.com>
1389 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1391 2020-06-25 Jan Beulich <jbeulich@suse.com>
1393 * i386-dis.c: Adjust description of "LQ" macro.
1394 (dis386_twobyte): Use LQ for sysret.
1395 (putop): Adjust handling of LQ.
1397 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1399 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1400 * riscv-dis.c: Include elfxx-riscv.h.
1402 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1404 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1406 2020-06-17 Lili Cui <lili.cui@intel.com>
1408 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1410 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1413 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1414 * i386-opc.tbl: Likewise.
1415 * i386-tbl.h: Regenerated.
1417 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1419 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1421 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1423 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1424 (SR_CORE): Likewise.
1425 (SR_FEAT): Likewise.
1427 (SR_V8_1): Likewise.
1428 (SR_V8_2): Likewise.
1429 (SR_V8_3): Likewise.
1430 (SR_V8_4): Likewise.
1433 (SR_SSBS): Likewise.
1435 (SR_ID_PFR2): Likewise.
1436 (SR_PROFILE): Likewise.
1437 (SR_MEMTAG): Likewise.
1438 (SR_SCXTNUM): Likewise.
1439 (aarch64_sys_regs): Refactor to store feature information in the table.
1440 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1441 that now describe their own features.
1442 (aarch64_pstatefield_supported_p): Likewise.
1444 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1446 * i386-dis.c (prefix_table): Fix a typo in comments.
1448 2020-06-09 Jan Beulich <jbeulich@suse.com>
1450 * i386-dis.c (rex_ignored): Delete.
1451 (ckprefix): Drop rex_ignored initialization.
1452 (get_valid_dis386): Drop setting of rex_ignored.
1453 (print_insn): Drop checking of rex_ignored. Don't record data
1454 size prefix as used with VEX-and-alike encodings.
1456 2020-06-09 Jan Beulich <jbeulich@suse.com>
1458 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1459 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1460 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1461 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1462 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1463 VEX_0F12, and VEX_0F16.
1464 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1465 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1466 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1467 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1468 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1469 MOD_VEX_0F16_PREFIX_2 entries.
1471 2020-06-09 Jan Beulich <jbeulich@suse.com>
1473 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1474 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1475 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1476 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1477 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1478 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1479 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1480 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1481 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1482 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1483 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1484 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1485 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1486 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1487 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1488 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1489 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1490 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1491 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1492 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1493 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1494 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1495 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1496 EVEX_W_0FC6_P_2): Delete.
1497 (print_insn): Add EVEX.W vs embedded prefix consistency check
1498 to prefix validation.
1499 * i386-dis-evex.h (evex_table): Don't further descend for
1500 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1501 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1503 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1504 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1505 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1506 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1507 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1508 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1509 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1510 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1511 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1512 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1513 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1514 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1515 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1516 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1517 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1518 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1519 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1520 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1521 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1522 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1523 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1524 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1525 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1526 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1527 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1528 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1529 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1531 2020-06-09 Jan Beulich <jbeulich@suse.com>
1533 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1534 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1535 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1537 (print_insn): Drop pointless check against bad_opcode. Split
1538 prefix validation into legacy and VEX-and-alike parts.
1539 (putop): Re-work 'X' macro handling.
1541 2020-06-09 Jan Beulich <jbeulich@suse.com>
1543 * i386-dis.c (MOD_0F51): Rename to ...
1544 (MOD_0F50): ... this.
1546 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1548 * arm-dis.c (arm_opcodes): Add dfb.
1549 (thumb32_opcodes): Add dfb.
1551 2020-06-08 Jan Beulich <jbeulich@suse.com>
1553 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1555 2020-06-06 Alan Modra <amodra@gmail.com>
1557 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1559 2020-06-05 Alan Modra <amodra@gmail.com>
1561 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1562 size is large enough.
1564 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1566 * disassemble.c (disassemble_init_for_target): Set endian_code for
1568 * bpf-desc.c: Regenerate.
1569 * bpf-opc.c: Likewise.
1570 * bpf-dis.c: Likewise.
1572 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1574 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1575 (cgen_put_insn_value): Likewise.
1576 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1577 * cgen-dis.in (print_insn): Likewise.
1578 * cgen-ibld.in (insert_1): Likewise.
1579 (insert_1): Likewise.
1580 (insert_insn_normal): Likewise.
1581 (extract_1): Likewise.
1582 * bpf-dis.c: Regenerate.
1583 * bpf-ibld.c: Likewise.
1584 * bpf-ibld.c: Likewise.
1585 * cgen-dis.in: Likewise.
1586 * cgen-ibld.in: Likewise.
1587 * cgen-opc.c: Likewise.
1588 * epiphany-dis.c: Likewise.
1589 * epiphany-ibld.c: Likewise.
1590 * fr30-dis.c: Likewise.
1591 * fr30-ibld.c: Likewise.
1592 * frv-dis.c: Likewise.
1593 * frv-ibld.c: Likewise.
1594 * ip2k-dis.c: Likewise.
1595 * ip2k-ibld.c: Likewise.
1596 * iq2000-dis.c: Likewise.
1597 * iq2000-ibld.c: Likewise.
1598 * lm32-dis.c: Likewise.
1599 * lm32-ibld.c: Likewise.
1600 * m32c-dis.c: Likewise.
1601 * m32c-ibld.c: Likewise.
1602 * m32r-dis.c: Likewise.
1603 * m32r-ibld.c: Likewise.
1604 * mep-dis.c: Likewise.
1605 * mep-ibld.c: Likewise.
1606 * mt-dis.c: Likewise.
1607 * mt-ibld.c: Likewise.
1608 * or1k-dis.c: Likewise.
1609 * or1k-ibld.c: Likewise.
1610 * xc16x-dis.c: Likewise.
1611 * xc16x-ibld.c: Likewise.
1612 * xstormy16-dis.c: Likewise.
1613 * xstormy16-ibld.c: Likewise.
1615 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1617 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1618 (print_insn_): Handle instruction endian.
1619 * bpf-dis.c: Regenerate.
1620 * bpf-desc.c: Regenerate.
1621 * epiphany-dis.c: Likewise.
1622 * epiphany-desc.c: Likewise.
1623 * fr30-dis.c: Likewise.
1624 * fr30-desc.c: Likewise.
1625 * frv-dis.c: Likewise.
1626 * frv-desc.c: Likewise.
1627 * ip2k-dis.c: Likewise.
1628 * ip2k-desc.c: Likewise.
1629 * iq2000-dis.c: Likewise.
1630 * iq2000-desc.c: Likewise.
1631 * lm32-dis.c: Likewise.
1632 * lm32-desc.c: Likewise.
1633 * m32c-dis.c: Likewise.
1634 * m32c-desc.c: Likewise.
1635 * m32r-dis.c: Likewise.
1636 * m32r-desc.c: Likewise.
1637 * mep-dis.c: Likewise.
1638 * mep-desc.c: Likewise.
1639 * mt-dis.c: Likewise.
1640 * mt-desc.c: Likewise.
1641 * or1k-dis.c: Likewise.
1642 * or1k-desc.c: Likewise.
1643 * xc16x-dis.c: Likewise.
1644 * xc16x-desc.c: Likewise.
1645 * xstormy16-dis.c: Likewise.
1646 * xstormy16-desc.c: Likewise.
1648 2020-06-03 Nick Clifton <nickc@redhat.com>
1650 * po/sr.po: Updated Serbian translation.
1652 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1654 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1655 (riscv_get_priv_spec_class): Likewise.
1657 2020-06-01 Alan Modra <amodra@gmail.com>
1659 * bpf-desc.c: Regenerate.
1661 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1662 David Faust <david.faust@oracle.com>
1664 * bpf-desc.c: Regenerate.
1665 * bpf-opc.h: Likewise.
1666 * bpf-opc.c: Likewise.
1667 * bpf-dis.c: Likewise.
1669 2020-05-28 Alan Modra <amodra@gmail.com>
1671 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1674 2020-05-28 Alan Modra <amodra@gmail.com>
1676 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1678 (print_insn_ns32k): Revert last change.
1680 2020-05-28 Nick Clifton <nickc@redhat.com>
1682 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1685 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1687 Fix extraction of signed constants in nios2 disassembler (again).
1689 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1690 extractions of signed fields.
1692 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1694 * s390-opc.txt: Relocate vector load/store instructions with
1695 additional alignment parameter and change architecture level
1696 constraint from z14 to z13.
1698 2020-05-21 Alan Modra <amodra@gmail.com>
1700 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1701 * sparc-dis.c: Likewise.
1702 * tic4x-dis.c: Likewise.
1703 * xtensa-dis.c: Likewise.
1704 * bpf-desc.c: Regenerate.
1705 * epiphany-desc.c: Regenerate.
1706 * fr30-desc.c: Regenerate.
1707 * frv-desc.c: Regenerate.
1708 * ip2k-desc.c: Regenerate.
1709 * iq2000-desc.c: Regenerate.
1710 * lm32-desc.c: Regenerate.
1711 * m32c-desc.c: Regenerate.
1712 * m32r-desc.c: Regenerate.
1713 * mep-asm.c: Regenerate.
1714 * mep-desc.c: Regenerate.
1715 * mt-desc.c: Regenerate.
1716 * or1k-desc.c: Regenerate.
1717 * xc16x-desc.c: Regenerate.
1718 * xstormy16-desc.c: Regenerate.
1720 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1722 * riscv-opc.c (riscv_ext_version_table): The table used to store
1723 all information about the supported spec and the corresponding ISA
1724 versions. Currently, only Zicsr is supported to verify the
1725 correctness of Z sub extension settings. Others will be supported
1726 in the future patches.
1727 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1728 classes and the corresponding strings.
1729 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1730 spec class by giving a ISA spec string.
1731 * riscv-opc.c (struct priv_spec_t): New structure.
1732 (struct priv_spec_t priv_specs): List for all supported privilege spec
1733 classes and the corresponding strings.
1734 (riscv_get_priv_spec_class): New function. Get the corresponding
1735 privilege spec class by giving a spec string.
1736 (riscv_get_priv_spec_name): New function. Get the corresponding
1737 privilege spec string by giving a CSR version class.
1738 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1739 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1740 according to the chosen version. Build a hash table riscv_csr_hash to
1741 store the valid CSR for the chosen pirv verison. Dump the direct
1742 CSR address rather than it's name if it is invalid.
1743 (parse_riscv_dis_option_without_args): New function. Parse the options
1745 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1746 parse the options without arguments first, and then handle the options
1747 with arguments. Add the new option -Mpriv-spec, which has argument.
1748 * riscv-dis.c (print_riscv_disassembler_options): Add description
1749 about the new OBJDUMP option.
1751 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1753 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1754 WC values on POWER10 sync, dcbf and wait instructions.
1755 (insert_pl, extract_pl): New functions.
1756 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1757 (LS3): New , 3-bit L for sync.
1758 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1759 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1760 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1761 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1762 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1763 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1764 <wait>: Enable PL operand on POWER10.
1765 <dcbf>: Enable L3OPT operand on POWER10.
1766 <sync>: Enable SC2 operand on POWER10.
1768 2020-05-19 Stafford Horne <shorne@gmail.com>
1771 * or1k-asm.c: Regenerate.
1772 * or1k-desc.c: Regenerate.
1773 * or1k-desc.h: Regenerate.
1774 * or1k-dis.c: Regenerate.
1775 * or1k-ibld.c: Regenerate.
1776 * or1k-opc.c: Regenerate.
1777 * or1k-opc.h: Regenerate.
1778 * or1k-opinst.c: Regenerate.
1780 2020-05-11 Alan Modra <amodra@gmail.com>
1782 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1785 2020-05-11 Alan Modra <amodra@gmail.com>
1787 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1788 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1790 2020-05-11 Alan Modra <amodra@gmail.com>
1792 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1794 2020-05-11 Alan Modra <amodra@gmail.com>
1796 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1797 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1799 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1801 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1804 2020-05-11 Alan Modra <amodra@gmail.com>
1806 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1807 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1808 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1809 (prefix_opcodes): Add xxeval.
1811 2020-05-11 Alan Modra <amodra@gmail.com>
1813 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1814 xxgenpcvwm, xxgenpcvdm.
1816 2020-05-11 Alan Modra <amodra@gmail.com>
1818 * ppc-opc.c (MP, VXVAM_MASK): Define.
1819 (VXVAPS_MASK): Use VXVA_MASK.
1820 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1821 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1822 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1823 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1825 2020-05-11 Alan Modra <amodra@gmail.com>
1826 Peter Bergner <bergner@linux.ibm.com>
1828 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1830 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1831 YMSK2, XA6a, XA6ap, XB6a entries.
1832 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1833 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1835 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1836 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1837 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1838 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1839 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1840 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1841 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1842 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1843 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1844 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1845 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1846 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1847 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1848 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1850 2020-05-11 Alan Modra <amodra@gmail.com>
1852 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1853 (insert_xts, extract_xts): New functions.
1854 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1855 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1856 (VXRC_MASK, VXSH_MASK): Define.
1857 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1858 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1859 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1860 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1861 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1862 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1863 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1865 2020-05-11 Alan Modra <amodra@gmail.com>
1867 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1868 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1869 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1870 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1871 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1873 2020-05-11 Alan Modra <amodra@gmail.com>
1875 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1876 (XTP, DQXP, DQXP_MASK): Define.
1877 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1878 (prefix_opcodes): Add plxvp and pstxvp.
1880 2020-05-11 Alan Modra <amodra@gmail.com>
1882 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1883 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1884 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1886 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1888 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1890 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1892 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1894 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1896 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1898 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1900 2020-05-11 Alan Modra <amodra@gmail.com>
1902 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1904 2020-05-11 Alan Modra <amodra@gmail.com>
1906 * ppc-dis.c (ppc_opts): Add "power10" entry.
1907 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1908 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1910 2020-05-11 Nick Clifton <nickc@redhat.com>
1912 * po/fr.po: Updated French translation.
1914 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1916 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1917 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1918 (operand_general_constraint_met_p): validate
1919 AARCH64_OPND_UNDEFINED.
1920 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1922 * aarch64-asm-2.c: Regenerated.
1923 * aarch64-dis-2.c: Regenerated.
1924 * aarch64-opc-2.c: Regenerated.
1926 2020-04-29 Nick Clifton <nickc@redhat.com>
1929 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1932 2020-04-29 Nick Clifton <nickc@redhat.com>
1934 * po/sv.po: Updated Swedish translation.
1936 2020-04-29 Nick Clifton <nickc@redhat.com>
1939 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1940 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1941 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1944 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1947 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1948 cmpi only on m68020up and cpu32.
1950 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1952 * aarch64-asm.c (aarch64_ins_none): New.
1953 * aarch64-asm.h (ins_none): New declaration.
1954 * aarch64-dis.c (aarch64_ext_none): New.
1955 * aarch64-dis.h (ext_none): New declaration.
1956 * aarch64-opc.c (aarch64_print_operand): Update case for
1957 AARCH64_OPND_BARRIER_PSB.
1958 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1959 (AARCH64_OPERANDS): Update inserter/extracter for
1960 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1961 * aarch64-asm-2.c: Regenerated.
1962 * aarch64-dis-2.c: Regenerated.
1963 * aarch64-opc-2.c: Regenerated.
1965 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1967 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1968 (aarch64_feature_ras, RAS): Likewise.
1969 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1970 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1971 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1972 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1973 * aarch64-asm-2.c: Regenerated.
1974 * aarch64-dis-2.c: Regenerated.
1975 * aarch64-opc-2.c: Regenerated.
1977 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1979 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1980 (print_insn_neon): Support disassembly of conditional
1983 2020-02-16 David Faust <david.faust@oracle.com>
1985 * bpf-desc.c: Regenerate.
1986 * bpf-desc.h: Likewise.
1987 * bpf-opc.c: Regenerate.
1988 * bpf-opc.h: Likewise.
1990 2020-04-07 Lili Cui <lili.cui@intel.com>
1992 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1993 (prefix_table): New instructions (see prefixes above).
1994 (rm_table): Likewise
1995 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1996 CPU_ANY_TSXLDTRK_FLAGS.
1997 (cpu_flags): Add CpuTSXLDTRK.
1998 * i386-opc.h (enum): Add CpuTSXLDTRK.
1999 (i386_cpu_flags): Add cputsxldtrk.
2000 * i386-opc.tbl: Add XSUSPLDTRK insns.
2001 * i386-init.h: Regenerate.
2002 * i386-tbl.h: Likewise.
2004 2020-04-02 Lili Cui <lili.cui@intel.com>
2006 * i386-dis.c (prefix_table): New instructions serialize.
2007 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2008 CPU_ANY_SERIALIZE_FLAGS.
2009 (cpu_flags): Add CpuSERIALIZE.
2010 * i386-opc.h (enum): Add CpuSERIALIZE.
2011 (i386_cpu_flags): Add cpuserialize.
2012 * i386-opc.tbl: Add SERIALIZE insns.
2013 * i386-init.h: Regenerate.
2014 * i386-tbl.h: Likewise.
2016 2020-03-26 Alan Modra <amodra@gmail.com>
2018 * disassemble.h (opcodes_assert): Declare.
2019 (OPCODES_ASSERT): Define.
2020 * disassemble.c: Don't include assert.h. Include opintl.h.
2021 (opcodes_assert): New function.
2022 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2023 (bfd_h8_disassemble): Reduce size of data array. Correctly
2024 calculate maxlen. Omit insn decoding when insn length exceeds
2025 maxlen. Exit from nibble loop when looking for E, before
2026 accessing next data byte. Move processing of E outside loop.
2027 Replace tests of maxlen in loop with assertions.
2029 2020-03-26 Alan Modra <amodra@gmail.com>
2031 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2033 2020-03-25 Alan Modra <amodra@gmail.com>
2035 * z80-dis.c (suffix): Init mybuf.
2037 2020-03-22 Alan Modra <amodra@gmail.com>
2039 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2040 successflly read from section.
2042 2020-03-22 Alan Modra <amodra@gmail.com>
2044 * arc-dis.c (find_format): Use ISO C string concatenation rather
2045 than line continuation within a string. Don't access needs_limm
2046 before testing opcode != NULL.
2048 2020-03-22 Alan Modra <amodra@gmail.com>
2050 * ns32k-dis.c (print_insn_arg): Update comment.
2051 (print_insn_ns32k): Reduce size of index_offset array, and
2052 initialize, passing -1 to print_insn_arg for args that are not
2053 an index. Don't exit arg loop early. Abort on bad arg number.
2055 2020-03-22 Alan Modra <amodra@gmail.com>
2057 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2058 * s12z-opc.c: Formatting.
2059 (operands_f): Return an int.
2060 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2061 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2062 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2063 (exg_sex_discrim): Likewise.
2064 (create_immediate_operand, create_bitfield_operand),
2065 (create_register_operand_with_size, create_register_all_operand),
2066 (create_register_all16_operand, create_simple_memory_operand),
2067 (create_memory_operand, create_memory_auto_operand): Don't
2068 segfault on malloc failure.
2069 (z_ext24_decode): Return an int status, negative on fail, zero
2071 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2072 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2073 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2074 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2075 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2076 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2077 (loop_primitive_decode, shift_decode, psh_pul_decode),
2078 (bit_field_decode): Similarly.
2079 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2080 to return value, update callers.
2081 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2082 Don't segfault on NULL operand.
2083 (decode_operation): Return OP_INVALID on first fail.
2084 (decode_s12z): Check all reads, returning -1 on fail.
2086 2020-03-20 Alan Modra <amodra@gmail.com>
2088 * metag-dis.c (print_insn_metag): Don't ignore status from
2091 2020-03-20 Alan Modra <amodra@gmail.com>
2093 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2094 Initialize parts of buffer not written when handling a possible
2095 2-byte insn at end of section. Don't attempt decoding of such
2096 an insn by the 4-byte machinery.
2098 2020-03-20 Alan Modra <amodra@gmail.com>
2100 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2101 partially filled buffer. Prevent lookup of 4-byte insns when
2102 only VLE 2-byte insns are possible due to section size. Print
2103 ".word" rather than ".long" for 2-byte leftovers.
2105 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2108 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2110 2020-03-13 Jan Beulich <jbeulich@suse.com>
2112 * i386-dis.c (X86_64_0D): Rename to ...
2113 (X86_64_0E): ... this.
2115 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2117 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2118 * Makefile.in: Regenerated.
2120 2020-03-09 Jan Beulich <jbeulich@suse.com>
2122 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2124 * i386-tbl.h: Re-generate.
2126 2020-03-09 Jan Beulich <jbeulich@suse.com>
2128 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2129 vprot*, vpsha*, and vpshl*.
2130 * i386-tbl.h: Re-generate.
2132 2020-03-09 Jan Beulich <jbeulich@suse.com>
2134 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2135 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2136 * i386-tbl.h: Re-generate.
2138 2020-03-09 Jan Beulich <jbeulich@suse.com>
2140 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2141 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2142 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2143 * i386-tbl.h: Re-generate.
2145 2020-03-09 Jan Beulich <jbeulich@suse.com>
2147 * i386-gen.c (struct template_arg, struct template_instance,
2148 struct template_param, struct template, templates,
2149 parse_template, expand_templates): New.
2150 (process_i386_opcodes): Various local variables moved to
2151 expand_templates. Call parse_template and expand_templates.
2152 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2153 * i386-tbl.h: Re-generate.
2155 2020-03-06 Jan Beulich <jbeulich@suse.com>
2157 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2158 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2159 register and memory source templates. Replace VexW= by VexW*
2161 * i386-tbl.h: Re-generate.
2163 2020-03-06 Jan Beulich <jbeulich@suse.com>
2165 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2166 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2167 * i386-tbl.h: Re-generate.
2169 2020-03-06 Jan Beulich <jbeulich@suse.com>
2171 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2172 * i386-tbl.h: Re-generate.
2174 2020-03-06 Jan Beulich <jbeulich@suse.com>
2176 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2177 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2178 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2179 VexW0 on SSE2AVX variants.
2180 (vmovq): Drop NoRex64 from XMM/XMM variants.
2181 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2182 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2183 applicable use VexW0.
2184 * i386-tbl.h: Re-generate.
2186 2020-03-06 Jan Beulich <jbeulich@suse.com>
2188 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2189 * i386-opc.h (Rex64): Delete.
2190 (struct i386_opcode_modifier): Remove rex64 field.
2191 * i386-opc.tbl (crc32): Drop Rex64.
2192 Replace Rex64 with Size64 everywhere else.
2193 * i386-tbl.h: Re-generate.
2195 2020-03-06 Jan Beulich <jbeulich@suse.com>
2197 * i386-dis.c (OP_E_memory): Exclude recording of used address
2198 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2199 addressed memory operands for MPX insns.
2201 2020-03-06 Jan Beulich <jbeulich@suse.com>
2203 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2204 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2205 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2206 (ptwrite): Split into non-64-bit and 64-bit forms.
2207 * i386-tbl.h: Re-generate.
2209 2020-03-06 Jan Beulich <jbeulich@suse.com>
2211 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2213 * i386-tbl.h: Re-generate.
2215 2020-03-04 Jan Beulich <jbeulich@suse.com>
2217 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2218 (prefix_table): Move vmmcall here. Add vmgexit.
2219 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2220 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2221 (cpu_flags): Add CpuSEV_ES entry.
2222 * i386-opc.h (CpuSEV_ES): New.
2223 (union i386_cpu_flags): Add cpusev_es field.
2224 * i386-opc.tbl (vmgexit): New.
2225 * i386-init.h, i386-tbl.h: Re-generate.
2227 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2229 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2231 * i386-opc.h (IGNORESIZE): New.
2232 (DEFAULTSIZE): Likewise.
2233 (IgnoreSize): Removed.
2234 (DefaultSize): Likewise.
2235 (MnemonicSize): New.
2236 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2238 * i386-opc.tbl (IgnoreSize): New.
2239 (DefaultSize): Likewise.
2240 * i386-tbl.h: Regenerated.
2242 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2245 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2248 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2251 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2252 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2253 * i386-tbl.h: Regenerated.
2255 2020-02-26 Alan Modra <amodra@gmail.com>
2257 * aarch64-asm.c: Indent labels correctly.
2258 * aarch64-dis.c: Likewise.
2259 * aarch64-gen.c: Likewise.
2260 * aarch64-opc.c: Likewise.
2261 * alpha-dis.c: Likewise.
2262 * i386-dis.c: Likewise.
2263 * nds32-asm.c: Likewise.
2264 * nfp-dis.c: Likewise.
2265 * visium-dis.c: Likewise.
2267 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2269 * arc-regs.h (int_vector_base): Make it available for all ARC
2272 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2274 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2277 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2279 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2280 c.mv/c.li if rs1 is zero.
2282 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2284 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2285 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2287 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2288 * i386-opc.h (CpuABM): Removed.
2290 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2291 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2292 popcnt. Remove CpuABM from lzcnt.
2293 * i386-init.h: Regenerated.
2294 * i386-tbl.h: Likewise.
2296 2020-02-17 Jan Beulich <jbeulich@suse.com>
2298 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2299 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2300 VexW1 instead of open-coding them.
2301 * i386-tbl.h: Re-generate.
2303 2020-02-17 Jan Beulich <jbeulich@suse.com>
2305 * i386-opc.tbl (AddrPrefixOpReg): Define.
2306 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2307 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2308 templates. Drop NoRex64.
2309 * i386-tbl.h: Re-generate.
2311 2020-02-17 Jan Beulich <jbeulich@suse.com>
2314 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2315 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2316 into Intel syntax instance (with Unpsecified) and AT&T one
2318 (vcvtneps2bf16): Likewise, along with folding the two so far
2320 * i386-tbl.h: Re-generate.
2322 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2324 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2325 CPU_ANY_SSE4A_FLAGS.
2327 2020-02-17 Alan Modra <amodra@gmail.com>
2329 * i386-gen.c (cpu_flag_init): Correct last change.
2331 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2333 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2336 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2338 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2341 2020-02-14 Jan Beulich <jbeulich@suse.com>
2344 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2345 destination for Cpu64-only variant.
2346 (movzx): Fold patterns.
2347 * i386-tbl.h: Re-generate.
2349 2020-02-13 Jan Beulich <jbeulich@suse.com>
2351 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2352 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2353 CPU_ANY_SSE4_FLAGS entry.
2354 * i386-init.h: Re-generate.
2356 2020-02-12 Jan Beulich <jbeulich@suse.com>
2358 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2359 with Unspecified, making the present one AT&T syntax only.
2360 * i386-tbl.h: Re-generate.
2362 2020-02-12 Jan Beulich <jbeulich@suse.com>
2364 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2365 * i386-tbl.h: Re-generate.
2367 2020-02-12 Jan Beulich <jbeulich@suse.com>
2370 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2371 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2372 Amd64 and Intel64 templates.
2373 (call, jmp): Likewise for far indirect variants. Dro
2375 * i386-tbl.h: Re-generate.
2377 2020-02-11 Jan Beulich <jbeulich@suse.com>
2379 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2380 * i386-opc.h (ShortForm): Delete.
2381 (struct i386_opcode_modifier): Remove shortform field.
2382 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2383 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2384 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2385 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2387 * i386-tbl.h: Re-generate.
2389 2020-02-11 Jan Beulich <jbeulich@suse.com>
2391 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2392 fucompi): Drop ShortForm from operand-less templates.
2393 * i386-tbl.h: Re-generate.
2395 2020-02-11 Alan Modra <amodra@gmail.com>
2397 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2398 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2399 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2400 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2401 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2403 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2405 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2406 (cde_opcodes): Add VCX* instructions.
2408 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2409 Matthew Malcomson <matthew.malcomson@arm.com>
2411 * arm-dis.c (struct cdeopcode32): New.
2412 (CDE_OPCODE): New macro.
2413 (cde_opcodes): New disassembly table.
2414 (regnames): New option to table.
2415 (cde_coprocs): New global variable.
2416 (print_insn_cde): New
2417 (print_insn_thumb32): Use print_insn_cde.
2418 (parse_arm_disassembler_options): Parse coprocN args.
2420 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2423 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2425 * i386-opc.h (AMD64): Removed.
2426 (Intel64): Likewose.
2428 (INTEL64): Likewise.
2429 (INTEL64ONLY): Likewise.
2430 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2431 * i386-opc.tbl (Amd64): New.
2432 (Intel64): Likewise.
2433 (Intel64Only): Likewise.
2434 Replace AMD64 with Amd64. Update sysenter/sysenter with
2435 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2436 * i386-tbl.h: Regenerated.
2438 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2441 * z80-dis.c: Add support for GBZ80 opcodes.
2443 2020-02-04 Alan Modra <amodra@gmail.com>
2445 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2447 2020-02-03 Alan Modra <amodra@gmail.com>
2449 * m32c-ibld.c: Regenerate.
2451 2020-02-01 Alan Modra <amodra@gmail.com>
2453 * frv-ibld.c: Regenerate.
2455 2020-01-31 Jan Beulich <jbeulich@suse.com>
2457 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2458 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2459 (OP_E_memory): Replace xmm_mdq_mode case label by
2460 vex_scalar_w_dq_mode one.
2461 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2463 2020-01-31 Jan Beulich <jbeulich@suse.com>
2465 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2466 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2467 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2468 (intel_operand_size): Drop vex_w_dq_mode case label.
2470 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2472 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2473 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2475 2020-01-30 Alan Modra <amodra@gmail.com>
2477 * m32c-ibld.c: Regenerate.
2479 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2481 * bpf-opc.c: Regenerate.
2483 2020-01-30 Jan Beulich <jbeulich@suse.com>
2485 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2486 (dis386): Use them to replace C2/C3 table entries.
2487 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2488 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2489 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2490 * i386-tbl.h: Re-generate.
2492 2020-01-30 Jan Beulich <jbeulich@suse.com>
2494 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2496 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2498 * i386-tbl.h: Re-generate.
2500 2020-01-30 Alan Modra <amodra@gmail.com>
2502 * tic4x-dis.c (tic4x_dp): Make unsigned.
2504 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2505 Jan Beulich <jbeulich@suse.com>
2508 * i386-dis.c (MOVSXD_Fixup): New function.
2509 (movsxd_mode): New enum.
2510 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2511 (intel_operand_size): Handle movsxd_mode.
2512 (OP_E_register): Likewise.
2514 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2515 register on movsxd. Add movsxd with 16-bit destination register
2516 for AMD64 and Intel64 ISAs.
2517 * i386-tbl.h: Regenerated.
2519 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2522 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2523 * aarch64-asm-2.c: Regenerate
2524 * aarch64-dis-2.c: Likewise.
2525 * aarch64-opc-2.c: Likewise.
2527 2020-01-21 Jan Beulich <jbeulich@suse.com>
2529 * i386-opc.tbl (sysret): Drop DefaultSize.
2530 * i386-tbl.h: Re-generate.
2532 2020-01-21 Jan Beulich <jbeulich@suse.com>
2534 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2536 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2537 * i386-tbl.h: Re-generate.
2539 2020-01-20 Nick Clifton <nickc@redhat.com>
2541 * po/de.po: Updated German translation.
2542 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2543 * po/uk.po: Updated Ukranian translation.
2545 2020-01-20 Alan Modra <amodra@gmail.com>
2547 * hppa-dis.c (fput_const): Remove useless cast.
2549 2020-01-20 Alan Modra <amodra@gmail.com>
2551 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2553 2020-01-18 Nick Clifton <nickc@redhat.com>
2555 * configure: Regenerate.
2556 * po/opcodes.pot: Regenerate.
2558 2020-01-18 Nick Clifton <nickc@redhat.com>
2560 Binutils 2.34 branch created.
2562 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2564 * opintl.h: Fix spelling error (seperate).
2566 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2568 * i386-opc.tbl: Add {vex} pseudo prefix.
2569 * i386-tbl.h: Regenerated.
2571 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2574 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2575 (neon_opcodes): Likewise.
2576 (select_arm_features): Make sure we enable MVE bits when selecting
2577 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2580 2020-01-16 Jan Beulich <jbeulich@suse.com>
2582 * i386-opc.tbl: Drop stale comment from XOP section.
2584 2020-01-16 Jan Beulich <jbeulich@suse.com>
2586 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2587 (extractps): Add VexWIG to SSE2AVX forms.
2588 * i386-tbl.h: Re-generate.
2590 2020-01-16 Jan Beulich <jbeulich@suse.com>
2592 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2593 Size64 from and use VexW1 on SSE2AVX forms.
2594 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2595 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2596 * i386-tbl.h: Re-generate.
2598 2020-01-15 Alan Modra <amodra@gmail.com>
2600 * tic4x-dis.c (tic4x_version): Make unsigned long.
2601 (optab, optab_special, registernames): New file scope vars.
2602 (tic4x_print_register): Set up registernames rather than
2603 malloc'd registertable.
2604 (tic4x_disassemble): Delete optable and optable_special. Use
2605 optab and optab_special instead. Throw away old optab,
2606 optab_special and registernames when info->mach changes.
2608 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2611 * z80-dis.c (suffix): Use .db instruction to generate double
2614 2020-01-14 Alan Modra <amodra@gmail.com>
2616 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2617 values to unsigned before shifting.
2619 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2621 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2623 (print_insn_thumb16, print_insn_thumb32): Likewise.
2624 (print_insn): Initialize the insn info.
2625 * i386-dis.c (print_insn): Initialize the insn info fields, and
2628 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2630 * arc-opc.c (C_NE): Make it required.
2632 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2634 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2635 reserved register name.
2637 2020-01-13 Alan Modra <amodra@gmail.com>
2639 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2640 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2642 2020-01-13 Alan Modra <amodra@gmail.com>
2644 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2645 result of wasm_read_leb128 in a uint64_t and check that bits
2646 are not lost when copying to other locals. Use uint32_t for
2647 most locals. Use PRId64 when printing int64_t.
2649 2020-01-13 Alan Modra <amodra@gmail.com>
2651 * score-dis.c: Formatting.
2652 * score7-dis.c: Formatting.
2654 2020-01-13 Alan Modra <amodra@gmail.com>
2656 * score-dis.c (print_insn_score48): Use unsigned variables for
2657 unsigned values. Don't left shift negative values.
2658 (print_insn_score32): Likewise.
2659 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2661 2020-01-13 Alan Modra <amodra@gmail.com>
2663 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2665 2020-01-13 Alan Modra <amodra@gmail.com>
2667 * fr30-ibld.c: Regenerate.
2669 2020-01-13 Alan Modra <amodra@gmail.com>
2671 * xgate-dis.c (print_insn): Don't left shift signed value.
2672 (ripBits): Formatting, use 1u.
2674 2020-01-10 Alan Modra <amodra@gmail.com>
2676 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2677 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2679 2020-01-10 Alan Modra <amodra@gmail.com>
2681 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2682 and XRREG value earlier to avoid a shift with negative exponent.
2683 * m10200-dis.c (disassemble): Similarly.
2685 2020-01-09 Nick Clifton <nickc@redhat.com>
2688 * z80-dis.c (ld_ii_ii): Use correct cast.
2690 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2693 * z80-dis.c (ld_ii_ii): Use character constant when checking
2696 2020-01-09 Jan Beulich <jbeulich@suse.com>
2698 * i386-dis.c (SEP_Fixup): New.
2700 (dis386_twobyte): Use it for sysenter/sysexit.
2701 (enum x86_64_isa): Change amd64 enumerator to value 1.
2702 (OP_J): Compare isa64 against intel64 instead of amd64.
2703 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2705 * i386-tbl.h: Re-generate.
2707 2020-01-08 Alan Modra <amodra@gmail.com>
2709 * z8k-dis.c: Include libiberty.h
2710 (instr_data_s): Make max_fetched unsigned.
2711 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2712 Don't exceed byte_info bounds.
2713 (output_instr): Make num_bytes unsigned.
2714 (unpack_instr): Likewise for nibl_count and loop.
2715 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2717 * z8k-opc.h: Regenerate.
2719 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2721 * arc-tbl.h (llock): Use 'LLOCK' as class.
2723 (scond): Use 'SCOND' as class.
2725 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2728 2020-01-06 Alan Modra <amodra@gmail.com>
2730 * m32c-ibld.c: Regenerate.
2732 2020-01-06 Alan Modra <amodra@gmail.com>
2735 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2736 Peek at next byte to prevent recursion on repeated prefix bytes.
2737 Ensure uninitialised "mybuf" is not accessed.
2738 (print_insn_z80): Don't zero n_fetch and n_used here,..
2739 (print_insn_z80_buf): ..do it here instead.
2741 2020-01-04 Alan Modra <amodra@gmail.com>
2743 * m32r-ibld.c: Regenerate.
2745 2020-01-04 Alan Modra <amodra@gmail.com>
2747 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2749 2020-01-04 Alan Modra <amodra@gmail.com>
2751 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2753 2020-01-04 Alan Modra <amodra@gmail.com>
2755 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2757 2020-01-03 Jan Beulich <jbeulich@suse.com>
2759 * aarch64-tbl.h (aarch64_opcode_table): Use
2760 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2762 2020-01-03 Jan Beulich <jbeulich@suse.com>
2764 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2765 forms of SUDOT and USDOT.
2767 2020-01-03 Jan Beulich <jbeulich@suse.com>
2769 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2771 * opcodes/aarch64-dis-2.c: Re-generate.
2773 2020-01-03 Jan Beulich <jbeulich@suse.com>
2775 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2777 * opcodes/aarch64-dis-2.c: Re-generate.
2779 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2781 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2783 2020-01-01 Alan Modra <amodra@gmail.com>
2785 Update year range in copyright notice of all files.
2787 For older changes see ChangeLog-2019
2789 Copyright (C) 2020 Free Software Foundation, Inc.
2791 Copying and distribution of this file, with or without modification,
2792 are permitted in any medium without royalty provided the copyright
2793 notice and this notice are preserved.
2799 version-control: never
projects / thirdparty / binutils-gdb.git / blob