opcodes/ChangeLog

   1 2018-07-11  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (operand_type_init): Remove
   4         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
   5         OPERAND_TYPE_INOUTPORTREG.
   6         * i386-init.h: Re-generate.
   7
   8 2018-07-11  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-opc.tbl (wrssd, wrussd): Add Dword.
  11         (wrssq, wrussq): Add Qword.
  12         * i386-tbl.h: Re-generate.
  13
  14 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  15
  16         * i386-opc.h: Rename OTMax to OTNum.
  17         (OTNumOfUints): Adjust calculation.
  18         (OTUnused): Directly alias to OTNum.
  19
  20 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
  21
  22         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
  23         `reg_xys'.
  24         (lea_reg_xys): Likewise.
  25         (print_insn_loop_primitive): Rename `reg' local variable to
  26         `reg_dxy'.
  27
  28 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
  29
  30         PR binutils/23242
  31         * aarch64-tbl.h (ldarh): Fix disassembly mask.
  32
  33 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
  34
  35         PR binutils/23369
  36         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
  37         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
  38
  39 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
  40
  41         PR tdep/8282
  42         * mips-dis.c (mips_option_arg_t): New enumeration.
  43         (mips_options): New variable.
  44         (disassembler_options_mips): New function.
  45         (print_mips_disassembler_options): Reimplement in terms of
  46         `disassembler_options_mips'.
  47         * arm-dis.c (disassembler_options_arm): Adapt to using the
  48         `disasm_options_and_args_t' structure.
  49         * ppc-dis.c (disassembler_options_powerpc): Likewise.
  50         * s390-dis.c (disassembler_options_s390): Likewise.
  51
  52 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  53
  54         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
  55         expected result.
  56         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
  57         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
  58         * testsuite/ld-arm/tls-longplt.d: Likewise.
  59
  60 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
  61
  62         PR binutils/23192
  63         * aarch64-asm-2.c: Regenerate.
  64         * aarch64-dis-2.c: Likewise.
  65         * aarch64-opc-2.c: Likewise.
  66         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
  67         * aarch64-opc.c (operand_general_constraint_met_p,
  68         aarch64_print_operand): Likewise.
  69         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
  70         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
  71         fmlal2, fmlsl2.
  72         (AARCH64_OPERANDS): Add Em2.
  73
  74 2018-06-26  Nick Clifton  <nickc@redhat.com>
  75
  76         * po/uk.po: Updated Ukranian translation.
  77         * po/de.po: Updated German translation.
  78         * po/pt_BR.po: Updated Brazilian Portuguese translation.
  79
  80 2018-06-26  Nick Clifton  <nickc@redhat.com>
  81
  82         * nfp-dis.c: Fix spelling mistake.
  83
  84 2018-06-24  Nick Clifton  <nickc@redhat.com>
  85
  86         * configure: Regenerate.
  87         * po/opcodes.pot: Regenerate.
  88
  89 2018-06-24  Nick Clifton  <nickc@redhat.com>
  90
  91         2.31 branch created.
  92
  93 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
  94
  95         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
  96         * aarch64-asm-2.c: Regenerate.
  97         * aarch64-dis-2.c: Likewise.
  98
  99 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 100
 101         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 102         `-M ginv' option description.
 103
 104 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 105
 106         PR gas/23305
 107         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 108         la and lla.
 109
 110 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 111
 112         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 113         * configure.ac: Remove AC_PREREQ.
 114         * Makefile.in: Re-generate.
 115         * aclocal.m4: Re-generate.
 116         * configure: Re-generate.
 117
 118 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 119
 120         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 121         mips64r6 descriptors.
 122         (parse_mips_ase_option): Handle -Mginv option.
 123         (print_mips_disassembler_options): Document -Mginv.
 124         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 125         (GINV): New macro.
 126         (mips_opcodes): Define ginvi and ginvt.
 127
 128 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 129             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 130
 131         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 132         * mips-opc.c (CRC, CRC64): New macros.
 133         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 134         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 135         crc32cd for CRC64.
 136
 137 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 138
 139         PR 20319
 140         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 141         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 142
 143 2018-06-06  Alan Modra  <amodra@gmail.com>
 144
 145         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 146         setjmp.  Move init for some other vars later too.
 147
 148 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 149
 150         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 151         (dis_private): Add new fields for property section tracking.
 152         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 153         (xtensa_instruction_fits): New functions.
 154         (fetch_data): Bump minimal fetch size to 4.
 155         (print_insn_xtensa): Make struct dis_private static.
 156         Load and prepare property table on section change.
 157         Don't disassemble literals. Don't disassemble instructions that
 158         cross property table boundaries.
 159
 160 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 161
 162         * configure: Regenerated.
 163
 164 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 167         * i386-tbl.h: Re-generate.
 168
 169 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-opc.tbl (sldt, str): Add NoRex64.
 172         * i386-tbl.h: Re-generate.
 173
 174 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-opc.tbl (invpcid): Add Oword.
 177         * i386-tbl.h: Re-generate.
 178
 179 2018-06-01  Alan Modra  <amodra@gmail.com>
 180
 181         * sysdep.h (_bfd_error_handler): Don't declare.
 182         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 183         * rl78-decode.opc: Likewise.
 184         * msp430-decode.c: Regenerate.
 185         * rl78-decode.c: Regenerate.
 186
 187 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 188
 189         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 190         * i386-init.h : Regenerated.
 191
 192 2018-05-25  Alan Modra  <amodra@gmail.com>
 193
 194         * Makefile.in: Regenerate.
 195         * po/POTFILES.in: Regenerate.
 196
 197 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 198
 199         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 200         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 201         (insert_bab, extract_bab, insert_btab, extract_btab,
 202         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 203         (BAT, BBA VBA RBS XB6S): Delete macros.
 204         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 205         (BB, BD, RBX, XC6): Update for new macros.
 206         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 207         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 208         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 209         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 210
 211 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 212
 213         * Makefile.am: Add support for s12z architecture.
 214         * configure.ac: Likewise.
 215         * disassemble.c: Likewise.
 216         * disassemble.h: Likewise.
 217         * Makefile.in: Regenerate.
 218         * configure: Regenerate.
 219         * s12z-dis.c: New file.
 220         * s12z.h: New file.
 221
 222 2018-05-18  Alan Modra  <amodra@gmail.com>
 223
 224         * nfp-dis.c: Don't #include libbfd.h.
 225         (init_nfp3200_priv): Use bfd_get_section_contents.
 226         (nit_nfp6000_mecsr_sec): Likewise.
 227
 228 2018-05-17  Nick Clifton  <nickc@redhat.com>
 229
 230         * po/zh_CN.po: Updated simplified Chinese translation.
 231
 232 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 233
 234         PR binutils/23109
 235         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 236         * aarch64-dis-2.c: Regenerate.
 237
 238 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 239
 240         PR binutils/21446
 241         * aarch64-asm.c (opintl.h): Include.
 242         (aarch64_ins_sysreg): Enforce read/write constraints.
 243         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 244         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 245         (F_REG_READ, F_REG_WRITE): New.
 246         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 247         AARCH64_OPND_SYSREG.
 248         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 249         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 250         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 251         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 252         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 253         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 254         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 255         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 256         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 257         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 258         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 259         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 260         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 261         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 262         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 263         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 264         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 265
 266 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 267
 268         PR binutils/21446
 269         * aarch64-dis.c (no_notes: New.
 270         (parse_aarch64_dis_option): Support notes.
 271         (aarch64_decode_insn, print_operands): Likewise.
 272         (print_aarch64_disassembler_options): Document notes.
 273         * aarch64-opc.c (aarch64_print_operand): Support notes.
 274
 275 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 276
 277         PR binutils/21446
 278         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 279         and take error struct.
 280         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 281         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 282         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 283         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 284         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 285         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 286         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 287         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 288         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 289         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 290         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 291         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 292         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 293         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 294         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 295         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 296         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 297         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 298         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 299         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 300         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 301         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 302         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 303         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 304         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 305         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 306         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 307         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 308         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 309         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 310         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 311         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 312         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 313         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 314         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 315         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 316         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 317         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 318         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 319         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 320         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 321         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 322         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 323         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 324         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 325         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 326         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 327         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 328         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 329         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 330         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 331         (determine_disassembling_preference, aarch64_decode_insn,
 332         print_insn_aarch64_word, print_insn_data): Take errors struct.
 333         (print_insn_aarch64): Use errors.
 334         * aarch64-asm-2.c: Regenerate.
 335         * aarch64-dis-2.c: Regenerate.
 336         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 337         boolean in aarch64_insert_operan.
 338         (print_operand_extractor): Likewise.
 339         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 340
 341 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 342
 343         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 344
 345 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 346
 347         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 348
 349 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 350
 351         * cr16-opc.c (cr16_instruction): Comment typo fix.
 352         * hppa-dis.c (print_insn_hppa): Likewise.
 353
 354 2018-05-08  Jim Wilson  <jimw@sifive.com>
 355
 356         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 357         (match_c_slli64, match_srxi_as_c_srxi): New.
 358         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 359         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 360         <c.slli, c.srli, c.srai>: Use match_s_slli.
 361         <c.slli64, c.srli64, c.srai64>: New.
 362
 363 2018-05-08  Alan Modra  <amodra@gmail.com>
 364
 365         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 366         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 367         partition opcode space for index lookup.
 368
 369 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 370
 371         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 372         <insn_length>: ...with this.  Update usage.
 373         Remove duplicate call to *info->memory_error_func.
 374
 375 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 376             H.J. Lu  <hongjiu.lu@intel.com>
 377
 378         * i386-dis.c (Gva): New.
 379         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 380         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 381         (prefix_table): New instructions (see prefix above).
 382         (mod_table): New instructions (see prefix above).
 383         (OP_G): Handle va_mode.
 384         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 385         CPU_MOVDIR64B_FLAGS.
 386         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 387         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 388         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 389         * i386-opc.tbl: Add movidir{i,64b}.
 390         * i386-init.h: Regenerated.
 391         * i386-tbl.h: Likewise.
 392
 393 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 396         AddrPrefixOpReg.
 397         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 398         (AddrPrefixOpReg): This.
 399         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 400         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 401
 402 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 403
 404         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 405         (vle_num_opcodes): Likewise.
 406         (spe2_num_opcodes): Likewise.
 407         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 408         initialization loop.
 409         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 410         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 411         only once.
 412
 413 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 414
 415         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 416
 417 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 418
 419         Makefile.am: Added nfp-dis.c.
 420         configure.ac: Added bfd_nfp_arch.
 421         disassemble.h: Added print_insn_nfp prototype.
 422         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 423         nfp-dis.c: New, for NFP support.
 424         po/POTFILES.in: Added nfp-dis.c to the list.
 425         Makefile.in: Regenerate.
 426         configure: Regenerate.
 427
 428 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 431         templates into their base ones.
 432         * i386-tlb.h: Re-generate.
 433
 434 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 435
 436         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 437         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 438         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 439         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 440         * i386-init.h: Re-generate.
 441
 442 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 445         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 446         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 447         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 448         comment.
 449         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 450         and CpuRegMask.
 451         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 452         CpuRegMask: Delete.
 453         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 454         cpuregzmm, and cpuregmask.
 455         * i386-init.h: Re-generate.
 456         * i386-tbl.h: Re-generate.
 457
 458 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 461         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 462         * i386-init.h: Re-generate.
 463
 464 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-gen.c (VexImmExt): Delete.
 467         * i386-opc.h (VexImmExt, veximmext): Delete.
 468         * i386-opc.tbl: Drop all VexImmExt uses.
 469         * i386-tlb.h: Re-generate.
 470
 471 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 472
 473         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 474         register-only forms.
 475         * i386-tlb.h: Re-generate.
 476
 477 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 478
 479         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 480
 481 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 482
 483         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 484         PREFIX_0F1C.
 485         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 486         (cpu_flags): Add CpuCLDEMOTE.
 487         * i386-init.h: Regenerate.
 488         * i386-opc.h (enum): Add CpuCLDEMOTE,
 489         (i386_cpu_flags): Add cpucldemote.
 490         * i386-opc.tbl: Add cldemote.
 491         * i386-tbl.h: Regenerate.
 492
 493 2018-04-16  Alan Modra  <amodra@gmail.com>
 494
 495         * Makefile.am: Remove sh5 and sh64 support.
 496         * configure.ac: Likewise.
 497         * disassemble.c: Likewise.
 498         * disassemble.h: Likewise.
 499         * sh-dis.c: Likewise.
 500         * sh64-dis.c: Delete.
 501         * sh64-opc.c: Delete.
 502         * sh64-opc.h: Delete.
 503         * Makefile.in: Regenerate.
 504         * configure: Regenerate.
 505         * po/POTFILES.in: Regenerate.
 506
 507 2018-04-16  Alan Modra  <amodra@gmail.com>
 508
 509         * Makefile.am: Remove w65 support.
 510         * configure.ac: Likewise.
 511         * disassemble.c: Likewise.
 512         * disassemble.h: Likewise.
 513         * w65-dis.c: Delete.
 514         * w65-opc.h: Delete.
 515         * Makefile.in: Regenerate.
 516         * configure: Regenerate.
 517         * po/POTFILES.in: Regenerate.
 518
 519 2018-04-16  Alan Modra  <amodra@gmail.com>
 520
 521         * configure.ac: Remove we32k support.
 522         * configure: Regenerate.
 523
 524 2018-04-16  Alan Modra  <amodra@gmail.com>
 525
 526         * Makefile.am: Remove m88k support.
 527         * configure.ac: Likewise.
 528         * disassemble.c: Likewise.
 529         * disassemble.h: Likewise.
 530         * m88k-dis.c: Delete.
 531         * Makefile.in: Regenerate.
 532         * configure: Regenerate.
 533         * po/POTFILES.in: Regenerate.
 534
 535 2018-04-16  Alan Modra  <amodra@gmail.com>
 536
 537         * Makefile.am: Remove i370 support.
 538         * configure.ac: Likewise.
 539         * disassemble.c: Likewise.
 540         * disassemble.h: Likewise.
 541         * i370-dis.c: Delete.
 542         * i370-opc.c: Delete.
 543         * Makefile.in: Regenerate.
 544         * configure: Regenerate.
 545         * po/POTFILES.in: Regenerate.
 546
 547 2018-04-16  Alan Modra  <amodra@gmail.com>
 548
 549         * Makefile.am: Remove h8500 support.
 550         * configure.ac: Likewise.
 551         * disassemble.c: Likewise.
 552         * disassemble.h: Likewise.
 553         * h8500-dis.c: Delete.
 554         * h8500-opc.h: Delete.
 555         * Makefile.in: Regenerate.
 556         * configure: Regenerate.
 557         * po/POTFILES.in: Regenerate.
 558
 559 2018-04-16  Alan Modra  <amodra@gmail.com>
 560
 561         * configure.ac: Remove tahoe support.
 562         * configure: Regenerate.
 563
 564 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 565
 566         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 567         umwait.
 568         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 569         64-bit mode.
 570         * i386-tbl.h: Regenerated.
 571
 572 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 573
 574         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 575         PREFIX_MOD_1_0FAE_REG_6.
 576         (va_mode): New.
 577         (OP_E_register): Use va_mode.
 578         * i386-dis-evex.h (prefix_table):
 579         New instructions (see prefixes above).
 580         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 581         (cpu_flags): Likewise.
 582         * i386-opc.h (enum): Likewise.
 583         (i386_cpu_flags): Likewise.
 584         * i386-opc.tbl: Add umonitor, umwait, tpause.
 585         * i386-init.h: Regenerate.
 586         * i386-tbl.h: Likewise.
 587
 588 2018-04-11  Alan Modra  <amodra@gmail.com>
 589
 590         * opcodes/i860-dis.c: Delete.
 591         * opcodes/i960-dis.c: Delete.
 592         * Makefile.am: Remove i860 and i960 support.
 593         * configure.ac: Likewise.
 594         * disassemble.c: Likewise.
 595         * disassemble.h: Likewise.
 596         * Makefile.in: Regenerate.
 597         * configure: Regenerate.
 598         * po/POTFILES.in: Regenerate.
 599
 600 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 601
 602         PR binutils/23025
 603         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 604         to 0.
 605         (print_insn): Clear vex instead of vex.evex.
 606
 607 2018-04-04  Nick Clifton  <nickc@redhat.com>
 608
 609         * po/es.po: Updated Spanish translation.
 610
 611 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-gen.c (opcode_modifiers): Delete VecESize.
 614         * i386-opc.h (VecESize): Delete.
 615         (struct i386_opcode_modifier): Delete vecesize.
 616         * i386-opc.tbl: Drop VecESize.
 617         * i386-tlb.h: Re-generate.
 618
 619 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 620
 621         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 622         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 623         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 624         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 625         * i386-tlb.h: Re-generate.
 626
 627 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 630         Fold AVX512 forms
 631         * i386-tlb.h: Re-generate.
 632
 633 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 634
 635         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 636         (vex_len_table): Drop Y for vcvt*2si.
 637         (putop): Replace plain 'Y' handling by abort().
 638
 639 2018-03-28  Nick Clifton  <nickc@redhat.com>
 640
 641         PR 22988
 642         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 643         instructions with only a base address register.
 644         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 645         handle AARHC64_OPND_SVE_ADDR_R.
 646         (aarch64_print_operand): Likewise.
 647         * aarch64-asm-2.c: Regenerate.
 648         * aarch64_dis-2.c: Regenerate.
 649         * aarch64-opc-2.c: Regenerate.
 650
 651 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-opc.tbl: Drop VecESize from register only insn forms and
 654         memory forms not allowing broadcast.
 655         * i386-tlb.h: Re-generate.
 656
 657 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 660         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 661         sha256*): Drop Disp<N>.
 662
 663 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 664
 665         * i386-dis.c (EbndS, bnd_swap_mode): New.
 666         (prefix_table): Use EbndS.
 667         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 668         * i386-opc.tbl (bndmov): Move misplaced Load.
 669         * i386-tlb.h: Re-generate.
 670
 671 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 672
 673         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 674         templates allowing memory operands and folded ones for register
 675         only flavors.
 676         * i386-tlb.h: Re-generate.
 677
 678 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 681         256-bit templates. Drop redundant leftover Disp<N>.
 682         * i386-tlb.h: Re-generate.
 683
 684 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 685
 686         * riscv-opc.c (riscv_insn_types): New.
 687
 688 2018-03-13  Nick Clifton  <nickc@redhat.com>
 689
 690         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 691
 692 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 693
 694         * i386-opc.tbl: Add Optimize to clr.
 695         * i386-tbl.h: Regenerated.
 696
 697 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 698
 699         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 700         * i386-opc.h (OldGcc): Removed.
 701         (i386_opcode_modifier): Remove oldgcc.
 702         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 703         instructions for old (<= 2.8.1) versions of gcc.
 704         * i386-tbl.h: Regenerated.
 705
 706 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-opc.h (EVEXDYN): New.
 709         * i386-opc.tbl: Fold various AVX512VL templates.
 710         * i386-tlb.h: Re-generate.
 711
 712 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 715         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 716         vpexpandd, vpexpandq): Fold AFX512VF templates.
 717         * i386-tlb.h: Re-generate.
 718
 719 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 720
 721         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 722         Fold 128- and 256-bit VEX-encoded templates.
 723         * i386-tlb.h: Re-generate.
 724
 725 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 728         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 729         vpexpandd, vpexpandq): Fold AVX512F templates.
 730         * i386-tlb.h: Re-generate.
 731
 732 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 733
 734         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 735         64-bit templates. Drop Disp<N>.
 736         * i386-tlb.h: Re-generate.
 737
 738 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 739
 740         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 741         and 256-bit templates.
 742         * i386-tlb.h: Re-generate.
 743
 744 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 745
 746         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 747         * i386-tlb.h: Re-generate.
 748
 749 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 750
 751         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 752         Drop NoAVX.
 753         * i386-tlb.h: Re-generate.
 754
 755 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 756
 757         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 758         * i386-tlb.h: Re-generate.
 759
 760 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-gen.c (opcode_modifiers): Delete FloatD.
 763         * i386-opc.h (FloatD): Delete.
 764         (struct i386_opcode_modifier): Delete floatd.
 765         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 766         FloatD by D.
 767         * i386-tlb.h: Re-generate.
 768
 769 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 772
 773 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 774
 775         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 776         * i386-tlb.h: Re-generate.
 777
 778 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 779
 780         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 781         forms.
 782         * i386-tlb.h: Re-generate.
 783
 784 2018-03-07  Alan Modra  <amodra@gmail.com>
 785
 786         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 787         bfd_arch_rs6000.
 788         * disassemble.h (print_insn_rs6000): Delete.
 789         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 790         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 791         (print_insn_rs6000): Delete.
 792
 793 2018-03-03  Alan Modra  <amodra@gmail.com>
 794
 795         * sysdep.h (opcodes_error_handler): Define.
 796         (_bfd_error_handler): Declare.
 797         * Makefile.am: Remove stray #.
 798         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 799         EDIT" comment.
 800         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 801         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 802         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 803         opcodes_error_handler to print errors.  Standardize error messages.
 804         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 805         and include opintl.h.
 806         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 807         * i386-gen.c: Standardize error messages.
 808         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 809         * Makefile.in: Regenerate.
 810         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 811         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 812         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 813         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 814         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 815         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 816         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 817         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 818         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 819         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 820         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 821         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 822         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 823
 824 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 825
 826         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 827         vpsub[bwdq] instructions.
 828         * i386-tbl.h: Regenerated.
 829
 830 2018-03-01  Alan Modra  <amodra@gmail.com>
 831
 832         * configure.ac (ALL_LINGUAS): Sort.
 833         * configure: Regenerate.
 834
 835 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 836
 837         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 838         macro by assignements.
 839
 840 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 841
 842         PR gas/22871
 843         * i386-gen.c (opcode_modifiers): Add Optimize.
 844         * i386-opc.h (Optimize): New enum.
 845         (i386_opcode_modifier): Add optimize.
 846         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 847         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 848         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 849         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 850         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 851         vpxord and vpxorq.
 852         * i386-tbl.h: Regenerated.
 853
 854 2018-02-26  Alan Modra  <amodra@gmail.com>
 855
 856         * crx-dis.c (getregliststring): Allocate a large enough buffer
 857         to silence false positive gcc8 warning.
 858
 859 2018-02-22  Shea Levy <shea@shealevy.com>
 860
 861         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 862
 863 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         * i386-opc.tbl: Add {rex},
 866         * i386-tbl.h: Regenerated.
 867
 868 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 869
 870         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 871         (mips16_opcodes): Replace `M' with `m' for "restore".
 872
 873 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 874
 875         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 876
 877 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 878
 879         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 880         variable to `function_index'.
 881
 882 2018-02-13  Nick Clifton  <nickc@redhat.com>
 883
 884         PR 22823
 885         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 886         about truncation of printing.
 887
 888 2018-02-12  Henry Wong <henry@stuffedcow.net>
 889
 890         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 891
 892 2018-02-05  Nick Clifton  <nickc@redhat.com>
 893
 894         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 895
 896 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 897
 898         * i386-dis.c (enum): Add pconfig.
 899         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 900         (cpu_flags): Add CpuPCONFIG.
 901         * i386-opc.h (enum): Add CpuPCONFIG.
 902         (i386_cpu_flags): Add cpupconfig.
 903         * i386-opc.tbl: Add PCONFIG instruction.
 904         * i386-init.h: Regenerate.
 905         * i386-tbl.h: Likewise.
 906
 907 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 908
 909         * i386-dis.c (enum): Add PREFIX_0F09.
 910         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 911         (cpu_flags): Add CpuWBNOINVD.
 912         * i386-opc.h (enum): Add CpuWBNOINVD.
 913         (i386_cpu_flags): Add cpuwbnoinvd.
 914         * i386-opc.tbl: Add WBNOINVD instruction.
 915         * i386-init.h: Regenerate.
 916         * i386-tbl.h: Likewise.
 917
 918 2018-01-17  Jim Wilson  <jimw@sifive.com>
 919
 920         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 921
 922 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 923
 924         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 925         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 926         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 927         (cpu_flags): Add CpuIBT, CpuSHSTK.
 928         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 929         (i386_cpu_flags): Add cpuibt, cpushstk.
 930         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 931         * i386-init.h: Regenerate.
 932         * i386-tbl.h: Likewise.
 933
 934 2018-01-16  Nick Clifton  <nickc@redhat.com>
 935
 936         * po/pt_BR.po: Updated Brazilian Portugese translation.
 937         * po/de.po: Updated German translation.
 938
 939 2018-01-15  Jim Wilson  <jimw@sifive.com>
 940
 941         * riscv-opc.c (match_c_nop): New.
 942         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 943
 944 2018-01-15  Nick Clifton  <nickc@redhat.com>
 945
 946         * po/uk.po: Updated Ukranian translation.
 947
 948 2018-01-13  Nick Clifton  <nickc@redhat.com>
 949
 950         * po/opcodes.pot: Regenerated.
 951
 952 2018-01-13  Nick Clifton  <nickc@redhat.com>
 953
 954         * configure: Regenerate.
 955
 956 2018-01-13  Nick Clifton  <nickc@redhat.com>
 957
 958         2.30 branch created.
 959
 960 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 961
 962         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 963         * i386-tbl.h: Regenerate.
 964
 965 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 968         * i386-tbl.h: Re-generate.
 969
 970 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 973         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 974         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 975         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 976         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 977         Disp8MemShift of AVX512VL forms.
 978         * i386-tbl.h: Re-generate.
 979
 980 2018-01-09  Jim Wilson  <jimw@sifive.com>
 981
 982         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 983         then the hi_addr value is zero.
 984
 985 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 986
 987         * arm-dis.c (arm_opcodes): Add csdb.
 988         (thumb32_opcodes): Add csdb.
 989
 990 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 991
 992         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 993         * aarch64-asm-2.c: Regenerate.
 994         * aarch64-dis-2.c: Regenerate.
 995         * aarch64-opc-2.c: Regenerate.
 996
 997 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 998
 999         PR gas/22681
1000         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1001         Remove AVX512 vmovd with 64-bit operands.
1002         * i386-tbl.h: Regenerated.
1003
1004 2018-01-05  Jim Wilson  <jimw@sifive.com>
1005
1006         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1007         jalr.
1008
1009 2018-01-03  Alan Modra  <amodra@gmail.com>
1010
1011         Update year range in copyright notice of all files.
1012
1013 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1014
1015         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1016         and OPERAND_TYPE_REGZMM entries.
1017
1018 For older changes see ChangeLog-2017
1019 \f
1020 Copyright (C) 2018 Free Software Foundation, Inc.
1021
1022 Copying and distribution of this file, with or without modification,
1023 are permitted in any medium without royalty provided the copyright
1024 notice and this notice are preserved.
1025
1026 Local Variables:
1027 mode: change-log
1028 left-margin: 8
1029 fill-column: 74
1030 version-control: never
1031 End: