opcodes/ChangeLog

   1 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
   2
   3         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
   4         `-M ginv' option description.
   5
   6 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
   7
   8         PR gas/23305
   9         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
  10         la and lla.
  11
  12 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
  13
  14         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
  15         * configure.ac: Remove AC_PREREQ.
  16         * Makefile.in: Re-generate.
  17         * aclocal.m4: Re-generate.
  18         * configure: Re-generate.
  19
  20 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
  21
  22         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
  23         mips64r6 descriptors.
  24         (parse_mips_ase_option): Handle -Mginv option.
  25         (print_mips_disassembler_options): Document -Mginv.
  26         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
  27         (GINV): New macro.
  28         (mips_opcodes): Define ginvi and ginvt.
  29
  30 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
  31             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
  32
  33         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
  34         * mips-opc.c (CRC, CRC64): New macros.
  35         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
  36         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
  37         crc32cd for CRC64.
  38
  39 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
  40
  41         PR 20319
  42         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
  43         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
  44
  45 2018-06-06  Alan Modra  <amodra@gmail.com>
  46
  47         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
  48         setjmp.  Move init for some other vars later too.
  49
  50 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
  51
  52         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
  53         (dis_private): Add new fields for property section tracking.
  54         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
  55         (xtensa_instruction_fits): New functions.
  56         (fetch_data): Bump minimal fetch size to 4.
  57         (print_insn_xtensa): Make struct dis_private static.
  58         Load and prepare property table on section change.
  59         Don't disassemble literals. Don't disassemble instructions that
  60         cross property table boundaries.
  61
  62 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
  63
  64         * configure: Regenerated.
  65
  66 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
  69         * i386-tbl.h: Re-generate.
  70
  71 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  72
  73         * i386-opc.tbl (sldt, str): Add NoRex64.
  74         * i386-tbl.h: Re-generate.
  75
  76 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-opc.tbl (invpcid): Add Oword.
  79         * i386-tbl.h: Re-generate.
  80
  81 2018-06-01  Alan Modra  <amodra@gmail.com>
  82
  83         * sysdep.h (_bfd_error_handler): Don't declare.
  84         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
  85         * rl78-decode.opc: Likewise.
  86         * msp430-decode.c: Regenerate.
  87         * rl78-decode.c: Regenerate.
  88
  89 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
  90
  91         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
  92         * i386-init.h : Regenerated.
  93
  94 2018-05-25  Alan Modra  <amodra@gmail.com>
  95
  96         * Makefile.in: Regenerate.
  97         * po/POTFILES.in: Regenerate.
  98
  99 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 100
 101         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 102         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 103         (insert_bab, extract_bab, insert_btab, extract_btab,
 104         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 105         (BAT, BBA VBA RBS XB6S): Delete macros.
 106         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 107         (BB, BD, RBX, XC6): Update for new macros.
 108         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 109         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 110         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 111         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 112
 113 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 114
 115         * Makefile.am: Add support for s12z architecture.
 116         * configure.ac: Likewise.
 117         * disassemble.c: Likewise.
 118         * disassemble.h: Likewise.
 119         * Makefile.in: Regenerate.
 120         * configure: Regenerate.
 121         * s12z-dis.c: New file.
 122         * s12z.h: New file.
 123
 124 2018-05-18  Alan Modra  <amodra@gmail.com>
 125
 126         * nfp-dis.c: Don't #include libbfd.h.
 127         (init_nfp3200_priv): Use bfd_get_section_contents.
 128         (nit_nfp6000_mecsr_sec): Likewise.
 129
 130 2018-05-17  Nick Clifton  <nickc@redhat.com>
 131
 132         * po/zh_CN.po: Updated simplified Chinese translation.
 133
 134 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 135
 136         PR binutils/23109
 137         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 138         * aarch64-dis-2.c: Regenerate.
 139
 140 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 141
 142         PR binutils/21446
 143         * aarch64-asm.c (opintl.h): Include.
 144         (aarch64_ins_sysreg): Enforce read/write constraints.
 145         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 146         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 147         (F_REG_READ, F_REG_WRITE): New.
 148         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 149         AARCH64_OPND_SYSREG.
 150         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 151         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 152         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 153         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 154         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 155         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 156         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 157         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 158         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 159         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 160         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 161         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 162         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 163         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 164         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 165         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 166         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 167
 168 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 169
 170         PR binutils/21446
 171         * aarch64-dis.c (no_notes: New.
 172         (parse_aarch64_dis_option): Support notes.
 173         (aarch64_decode_insn, print_operands): Likewise.
 174         (print_aarch64_disassembler_options): Document notes.
 175         * aarch64-opc.c (aarch64_print_operand): Support notes.
 176
 177 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 178
 179         PR binutils/21446
 180         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 181         and take error struct.
 182         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 183         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 184         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 185         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 186         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 187         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 188         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 189         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 190         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 191         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 192         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 193         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 194         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 195         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 196         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 197         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 198         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 199         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 200         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 201         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 202         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 203         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 204         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 205         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 206         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 207         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 208         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 209         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 210         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 211         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 212         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 213         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 214         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 215         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 216         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 217         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 218         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 219         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 220         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 221         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 222         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 223         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 224         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 225         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 226         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 227         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 228         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 229         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 230         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 231         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 232         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 233         (determine_disassembling_preference, aarch64_decode_insn,
 234         print_insn_aarch64_word, print_insn_data): Take errors struct.
 235         (print_insn_aarch64): Use errors.
 236         * aarch64-asm-2.c: Regenerate.
 237         * aarch64-dis-2.c: Regenerate.
 238         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 239         boolean in aarch64_insert_operan.
 240         (print_operand_extractor): Likewise.
 241         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 242
 243 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 244
 245         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 246
 247 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 248
 249         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 250
 251 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 252
 253         * cr16-opc.c (cr16_instruction): Comment typo fix.
 254         * hppa-dis.c (print_insn_hppa): Likewise.
 255
 256 2018-05-08  Jim Wilson  <jimw@sifive.com>
 257
 258         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 259         (match_c_slli64, match_srxi_as_c_srxi): New.
 260         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 261         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 262         <c.slli, c.srli, c.srai>: Use match_s_slli.
 263         <c.slli64, c.srli64, c.srai64>: New.
 264
 265 2018-05-08  Alan Modra  <amodra@gmail.com>
 266
 267         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 268         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 269         partition opcode space for index lookup.
 270
 271 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 272
 273         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 274         <insn_length>: ...with this.  Update usage.
 275         Remove duplicate call to *info->memory_error_func.
 276
 277 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 278             H.J. Lu  <hongjiu.lu@intel.com>
 279
 280         * i386-dis.c (Gva): New.
 281         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 282         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 283         (prefix_table): New instructions (see prefix above).
 284         (mod_table): New instructions (see prefix above).
 285         (OP_G): Handle va_mode.
 286         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 287         CPU_MOVDIR64B_FLAGS.
 288         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 289         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 290         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 291         * i386-opc.tbl: Add movidir{i,64b}.
 292         * i386-init.h: Regenerated.
 293         * i386-tbl.h: Likewise.
 294
 295 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 296
 297         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 298         AddrPrefixOpReg.
 299         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 300         (AddrPrefixOpReg): This.
 301         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 302         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 303
 304 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 305
 306         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 307         (vle_num_opcodes): Likewise.
 308         (spe2_num_opcodes): Likewise.
 309         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 310         initialization loop.
 311         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 312         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 313         only once.
 314
 315 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 316
 317         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 318
 319 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 320
 321         Makefile.am: Added nfp-dis.c.
 322         configure.ac: Added bfd_nfp_arch.
 323         disassemble.h: Added print_insn_nfp prototype.
 324         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 325         nfp-dis.c: New, for NFP support.
 326         po/POTFILES.in: Added nfp-dis.c to the list.
 327         Makefile.in: Regenerate.
 328         configure: Regenerate.
 329
 330 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 333         templates into their base ones.
 334         * i386-tlb.h: Re-generate.
 335
 336 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 339         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 340         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 341         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 342         * i386-init.h: Re-generate.
 343
 344 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 347         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 348         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 349         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 350         comment.
 351         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 352         and CpuRegMask.
 353         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 354         CpuRegMask: Delete.
 355         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 356         cpuregzmm, and cpuregmask.
 357         * i386-init.h: Re-generate.
 358         * i386-tbl.h: Re-generate.
 359
 360 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 363         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 364         * i386-init.h: Re-generate.
 365
 366 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-gen.c (VexImmExt): Delete.
 369         * i386-opc.h (VexImmExt, veximmext): Delete.
 370         * i386-opc.tbl: Drop all VexImmExt uses.
 371         * i386-tlb.h: Re-generate.
 372
 373 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 376         register-only forms.
 377         * i386-tlb.h: Re-generate.
 378
 379 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 380
 381         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 382
 383 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 384
 385         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 386         PREFIX_0F1C.
 387         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 388         (cpu_flags): Add CpuCLDEMOTE.
 389         * i386-init.h: Regenerate.
 390         * i386-opc.h (enum): Add CpuCLDEMOTE,
 391         (i386_cpu_flags): Add cpucldemote.
 392         * i386-opc.tbl: Add cldemote.
 393         * i386-tbl.h: Regenerate.
 394
 395 2018-04-16  Alan Modra  <amodra@gmail.com>
 396
 397         * Makefile.am: Remove sh5 and sh64 support.
 398         * configure.ac: Likewise.
 399         * disassemble.c: Likewise.
 400         * disassemble.h: Likewise.
 401         * sh-dis.c: Likewise.
 402         * sh64-dis.c: Delete.
 403         * sh64-opc.c: Delete.
 404         * sh64-opc.h: Delete.
 405         * Makefile.in: Regenerate.
 406         * configure: Regenerate.
 407         * po/POTFILES.in: Regenerate.
 408
 409 2018-04-16  Alan Modra  <amodra@gmail.com>
 410
 411         * Makefile.am: Remove w65 support.
 412         * configure.ac: Likewise.
 413         * disassemble.c: Likewise.
 414         * disassemble.h: Likewise.
 415         * w65-dis.c: Delete.
 416         * w65-opc.h: Delete.
 417         * Makefile.in: Regenerate.
 418         * configure: Regenerate.
 419         * po/POTFILES.in: Regenerate.
 420
 421 2018-04-16  Alan Modra  <amodra@gmail.com>
 422
 423         * configure.ac: Remove we32k support.
 424         * configure: Regenerate.
 425
 426 2018-04-16  Alan Modra  <amodra@gmail.com>
 427
 428         * Makefile.am: Remove m88k support.
 429         * configure.ac: Likewise.
 430         * disassemble.c: Likewise.
 431         * disassemble.h: Likewise.
 432         * m88k-dis.c: Delete.
 433         * Makefile.in: Regenerate.
 434         * configure: Regenerate.
 435         * po/POTFILES.in: Regenerate.
 436
 437 2018-04-16  Alan Modra  <amodra@gmail.com>
 438
 439         * Makefile.am: Remove i370 support.
 440         * configure.ac: Likewise.
 441         * disassemble.c: Likewise.
 442         * disassemble.h: Likewise.
 443         * i370-dis.c: Delete.
 444         * i370-opc.c: Delete.
 445         * Makefile.in: Regenerate.
 446         * configure: Regenerate.
 447         * po/POTFILES.in: Regenerate.
 448
 449 2018-04-16  Alan Modra  <amodra@gmail.com>
 450
 451         * Makefile.am: Remove h8500 support.
 452         * configure.ac: Likewise.
 453         * disassemble.c: Likewise.
 454         * disassemble.h: Likewise.
 455         * h8500-dis.c: Delete.
 456         * h8500-opc.h: Delete.
 457         * Makefile.in: Regenerate.
 458         * configure: Regenerate.
 459         * po/POTFILES.in: Regenerate.
 460
 461 2018-04-16  Alan Modra  <amodra@gmail.com>
 462
 463         * configure.ac: Remove tahoe support.
 464         * configure: Regenerate.
 465
 466 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 467
 468         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 469         umwait.
 470         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 471         64-bit mode.
 472         * i386-tbl.h: Regenerated.
 473
 474 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 475
 476         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 477         PREFIX_MOD_1_0FAE_REG_6.
 478         (va_mode): New.
 479         (OP_E_register): Use va_mode.
 480         * i386-dis-evex.h (prefix_table):
 481         New instructions (see prefixes above).
 482         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 483         (cpu_flags): Likewise.
 484         * i386-opc.h (enum): Likewise.
 485         (i386_cpu_flags): Likewise.
 486         * i386-opc.tbl: Add umonitor, umwait, tpause.
 487         * i386-init.h: Regenerate.
 488         * i386-tbl.h: Likewise.
 489
 490 2018-04-11  Alan Modra  <amodra@gmail.com>
 491
 492         * opcodes/i860-dis.c: Delete.
 493         * opcodes/i960-dis.c: Delete.
 494         * Makefile.am: Remove i860 and i960 support.
 495         * configure.ac: Likewise.
 496         * disassemble.c: Likewise.
 497         * disassemble.h: Likewise.
 498         * Makefile.in: Regenerate.
 499         * configure: Regenerate.
 500         * po/POTFILES.in: Regenerate.
 501
 502 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 503
 504         PR binutils/23025
 505         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 506         to 0.
 507         (print_insn): Clear vex instead of vex.evex.
 508
 509 2018-04-04  Nick Clifton  <nickc@redhat.com>
 510
 511         * po/es.po: Updated Spanish translation.
 512
 513 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-gen.c (opcode_modifiers): Delete VecESize.
 516         * i386-opc.h (VecESize): Delete.
 517         (struct i386_opcode_modifier): Delete vecesize.
 518         * i386-opc.tbl: Drop VecESize.
 519         * i386-tlb.h: Re-generate.
 520
 521 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 524         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 525         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 526         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 527         * i386-tlb.h: Re-generate.
 528
 529 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 530
 531         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 532         Fold AVX512 forms
 533         * i386-tlb.h: Re-generate.
 534
 535 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 538         (vex_len_table): Drop Y for vcvt*2si.
 539         (putop): Replace plain 'Y' handling by abort().
 540
 541 2018-03-28  Nick Clifton  <nickc@redhat.com>
 542
 543         PR 22988
 544         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 545         instructions with only a base address register.
 546         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 547         handle AARHC64_OPND_SVE_ADDR_R.
 548         (aarch64_print_operand): Likewise.
 549         * aarch64-asm-2.c: Regenerate.
 550         * aarch64_dis-2.c: Regenerate.
 551         * aarch64-opc-2.c: Regenerate.
 552
 553 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 554
 555         * i386-opc.tbl: Drop VecESize from register only insn forms and
 556         memory forms not allowing broadcast.
 557         * i386-tlb.h: Re-generate.
 558
 559 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 562         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 563         sha256*): Drop Disp<N>.
 564
 565 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 566
 567         * i386-dis.c (EbndS, bnd_swap_mode): New.
 568         (prefix_table): Use EbndS.
 569         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 570         * i386-opc.tbl (bndmov): Move misplaced Load.
 571         * i386-tlb.h: Re-generate.
 572
 573 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 576         templates allowing memory operands and folded ones for register
 577         only flavors.
 578         * i386-tlb.h: Re-generate.
 579
 580 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 581
 582         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 583         256-bit templates. Drop redundant leftover Disp<N>.
 584         * i386-tlb.h: Re-generate.
 585
 586 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 587
 588         * riscv-opc.c (riscv_insn_types): New.
 589
 590 2018-03-13  Nick Clifton  <nickc@redhat.com>
 591
 592         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 593
 594 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * i386-opc.tbl: Add Optimize to clr.
 597         * i386-tbl.h: Regenerated.
 598
 599 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 600
 601         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 602         * i386-opc.h (OldGcc): Removed.
 603         (i386_opcode_modifier): Remove oldgcc.
 604         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 605         instructions for old (<= 2.8.1) versions of gcc.
 606         * i386-tbl.h: Regenerated.
 607
 608 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-opc.h (EVEXDYN): New.
 611         * i386-opc.tbl: Fold various AVX512VL templates.
 612         * i386-tlb.h: Re-generate.
 613
 614 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 617         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 618         vpexpandd, vpexpandq): Fold AFX512VF templates.
 619         * i386-tlb.h: Re-generate.
 620
 621 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 624         Fold 128- and 256-bit VEX-encoded templates.
 625         * i386-tlb.h: Re-generate.
 626
 627 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 630         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 631         vpexpandd, vpexpandq): Fold AVX512F templates.
 632         * i386-tlb.h: Re-generate.
 633
 634 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 635
 636         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 637         64-bit templates. Drop Disp<N>.
 638         * i386-tlb.h: Re-generate.
 639
 640 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 643         and 256-bit templates.
 644         * i386-tlb.h: Re-generate.
 645
 646 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 649         * i386-tlb.h: Re-generate.
 650
 651 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 654         Drop NoAVX.
 655         * i386-tlb.h: Re-generate.
 656
 657 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 660         * i386-tlb.h: Re-generate.
 661
 662 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 663
 664         * i386-gen.c (opcode_modifiers): Delete FloatD.
 665         * i386-opc.h (FloatD): Delete.
 666         (struct i386_opcode_modifier): Delete floatd.
 667         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 668         FloatD by D.
 669         * i386-tlb.h: Re-generate.
 670
 671 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 672
 673         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 674
 675 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 676
 677         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 678         * i386-tlb.h: Re-generate.
 679
 680 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 683         forms.
 684         * i386-tlb.h: Re-generate.
 685
 686 2018-03-07  Alan Modra  <amodra@gmail.com>
 687
 688         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 689         bfd_arch_rs6000.
 690         * disassemble.h (print_insn_rs6000): Delete.
 691         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 692         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 693         (print_insn_rs6000): Delete.
 694
 695 2018-03-03  Alan Modra  <amodra@gmail.com>
 696
 697         * sysdep.h (opcodes_error_handler): Define.
 698         (_bfd_error_handler): Declare.
 699         * Makefile.am: Remove stray #.
 700         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 701         EDIT" comment.
 702         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 703         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 704         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 705         opcodes_error_handler to print errors.  Standardize error messages.
 706         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 707         and include opintl.h.
 708         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 709         * i386-gen.c: Standardize error messages.
 710         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 711         * Makefile.in: Regenerate.
 712         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 713         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 714         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 715         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 716         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 717         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 718         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 719         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 720         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 721         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 722         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 723         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 724         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 725
 726 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 727
 728         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 729         vpsub[bwdq] instructions.
 730         * i386-tbl.h: Regenerated.
 731
 732 2018-03-01  Alan Modra  <amodra@gmail.com>
 733
 734         * configure.ac (ALL_LINGUAS): Sort.
 735         * configure: Regenerate.
 736
 737 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 738
 739         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 740         macro by assignements.
 741
 742 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 743
 744         PR gas/22871
 745         * i386-gen.c (opcode_modifiers): Add Optimize.
 746         * i386-opc.h (Optimize): New enum.
 747         (i386_opcode_modifier): Add optimize.
 748         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 749         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 750         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 751         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 752         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 753         vpxord and vpxorq.
 754         * i386-tbl.h: Regenerated.
 755
 756 2018-02-26  Alan Modra  <amodra@gmail.com>
 757
 758         * crx-dis.c (getregliststring): Allocate a large enough buffer
 759         to silence false positive gcc8 warning.
 760
 761 2018-02-22  Shea Levy <shea@shealevy.com>
 762
 763         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 764
 765 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         * i386-opc.tbl: Add {rex},
 768         * i386-tbl.h: Regenerated.
 769
 770 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 771
 772         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 773         (mips16_opcodes): Replace `M' with `m' for "restore".
 774
 775 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 776
 777         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 778
 779 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 780
 781         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 782         variable to `function_index'.
 783
 784 2018-02-13  Nick Clifton  <nickc@redhat.com>
 785
 786         PR 22823
 787         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 788         about truncation of printing.
 789
 790 2018-02-12  Henry Wong <henry@stuffedcow.net>
 791
 792         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 793
 794 2018-02-05  Nick Clifton  <nickc@redhat.com>
 795
 796         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 797
 798 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 799
 800         * i386-dis.c (enum): Add pconfig.
 801         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 802         (cpu_flags): Add CpuPCONFIG.
 803         * i386-opc.h (enum): Add CpuPCONFIG.
 804         (i386_cpu_flags): Add cpupconfig.
 805         * i386-opc.tbl: Add PCONFIG instruction.
 806         * i386-init.h: Regenerate.
 807         * i386-tbl.h: Likewise.
 808
 809 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 810
 811         * i386-dis.c (enum): Add PREFIX_0F09.
 812         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 813         (cpu_flags): Add CpuWBNOINVD.
 814         * i386-opc.h (enum): Add CpuWBNOINVD.
 815         (i386_cpu_flags): Add cpuwbnoinvd.
 816         * i386-opc.tbl: Add WBNOINVD instruction.
 817         * i386-init.h: Regenerate.
 818         * i386-tbl.h: Likewise.
 819
 820 2018-01-17  Jim Wilson  <jimw@sifive.com>
 821
 822         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 823
 824 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 825
 826         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 827         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 828         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 829         (cpu_flags): Add CpuIBT, CpuSHSTK.
 830         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 831         (i386_cpu_flags): Add cpuibt, cpushstk.
 832         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 833         * i386-init.h: Regenerate.
 834         * i386-tbl.h: Likewise.
 835
 836 2018-01-16  Nick Clifton  <nickc@redhat.com>
 837
 838         * po/pt_BR.po: Updated Brazilian Portugese translation.
 839         * po/de.po: Updated German translation.
 840
 841 2018-01-15  Jim Wilson  <jimw@sifive.com>
 842
 843         * riscv-opc.c (match_c_nop): New.
 844         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 845
 846 2018-01-15  Nick Clifton  <nickc@redhat.com>
 847
 848         * po/uk.po: Updated Ukranian translation.
 849
 850 2018-01-13  Nick Clifton  <nickc@redhat.com>
 851
 852         * po/opcodes.pot: Regenerated.
 853
 854 2018-01-13  Nick Clifton  <nickc@redhat.com>
 855
 856         * configure: Regenerate.
 857
 858 2018-01-13  Nick Clifton  <nickc@redhat.com>
 859
 860         2.30 branch created.
 861
 862 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 863
 864         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 865         * i386-tbl.h: Regenerate.
 866
 867 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 870         * i386-tbl.h: Re-generate.
 871
 872 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 875         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 876         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 877         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 878         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 879         Disp8MemShift of AVX512VL forms.
 880         * i386-tbl.h: Re-generate.
 881
 882 2018-01-09  Jim Wilson  <jimw@sifive.com>
 883
 884         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 885         then the hi_addr value is zero.
 886
 887 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 888
 889         * arm-dis.c (arm_opcodes): Add csdb.
 890         (thumb32_opcodes): Add csdb.
 891
 892 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 893
 894         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 895         * aarch64-asm-2.c: Regenerate.
 896         * aarch64-dis-2.c: Regenerate.
 897         * aarch64-opc-2.c: Regenerate.
 898
 899 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 900
 901         PR gas/22681
 902         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 903         Remove AVX512 vmovd with 64-bit operands.
 904         * i386-tbl.h: Regenerated.
 905
 906 2018-01-05  Jim Wilson  <jimw@sifive.com>
 907
 908         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 909         jalr.
 910
 911 2018-01-03  Alan Modra  <amodra@gmail.com>
 912
 913         Update year range in copyright notice of all files.
 914
 915 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 918         and OPERAND_TYPE_REGZMM entries.
 919
 920 For older changes see ChangeLog-2017
 921 \f
 922 Copyright (C) 2018 Free Software Foundation, Inc.
 923
 924 Copying and distribution of this file, with or without modification,
 925 are permitted in any medium without royalty provided the copyright
 926 notice and this notice are preserved.
 927
 928 Local Variables:
 929 mode: change-log
 930 left-margin: 8
 931 fill-column: 74
 932 version-control: never
 933 End: