opcodes/ChangeLog

   1 2021-03-31  Alan Modra  <amodra@gmail.com>
   2
   3         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
   4         * aarch64-dis.h: Likewise.
   5         * aarch64-opc.c: Likewise.
   6         * avr-dis.c: Likewise.
   7         * csky-dis.c: Likewise.
   8         * nds32-asm.c: Likewise.
   9         * nds32-dis.c: Likewise.
  10         * nfp-dis.c: Likewise.
  11         * riscv-dis.c: Likewise.
  12         * s12z-dis.c: Likewise.
  13         * wasm32-dis.c: Likewise.
  14
  15 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
  18         (i386_seg_prefixes): New.
  19         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
  20         (i386_seg_prefixes): Declare.
  21
  22 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
  25
  26 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
  29         * i386-reg.tbl (st): Move down.
  30         (st(0)): Delete. Extend comment.
  31         * i386-tbl.h: Re-generate.
  32
  33 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
  36         (cmpsd): Move next to cmps.
  37         (movsd): Move next to movs.
  38         (cmpxchg16b): Move to separate section.
  39         (fisttp, fisttpll): Likewise.
  40         (monitor, mwait): Likewise.
  41         * i386-tbl.h: Re-generate.
  42
  43 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  44
  45         * i386-opc.tbl (psadbw): Add <sse2:comm>.
  46         (vpsadbw): Add C.
  47         * i386-tbl.h: Re-generate.
  48
  49 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
  52         pclmul, gfni): New templates. Use them wherever possible. Move
  53         SSE4.1 pextrw into respective section.
  54         * i386-tbl.h: Re-generate.
  55
  56 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  57
  58         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
  59         strtoull(). Bump upper loop bound. Widen masks. Sanity check
  60         "length".
  61         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
  62         Convert all of their uses to representation in opcode.
  63
  64 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
  67         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
  68         value of None. Shrink operands to 3 bits.
  69
  70 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-gen.c (process_i386_opcode_modifier): New parameter
  73         "space".
  74         (output_i386_opcode): New local variable "space". Adjust
  75         process_i386_opcode_modifier() invocation.
  76         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  77         invocation.
  78         * i386-tbl.h: Re-generate.
  79
  80 2021-03-29  Alan Modra  <amodra@gmail.com>
  81
  82         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
  83         (fp_qualifier_p, get_data_pattern): Likewise.
  84         (aarch64_get_operand_modifier_from_value): Likewise.
  85         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
  86         (operand_variant_qualifier_p): Likewise.
  87         (qualifier_value_in_range_constraint_p): Likewise.
  88         (aarch64_get_qualifier_esize): Likewise.
  89         (aarch64_get_qualifier_nelem): Likewise.
  90         (aarch64_get_qualifier_standard_value): Likewise.
  91         (get_lower_bound, get_upper_bound): Likewise.
  92         (aarch64_find_best_match, match_operands_qualifier): Likewise.
  93         (aarch64_print_operand): Likewise.
  94         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
  95         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
  96         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
  97         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
  98         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
  99         (print_insn_tic6x): Likewise.
 100
 101 2021-03-29  Alan Modra  <amodra@gmail.com>
 102
 103         * arc-dis.c (extract_operand_value): Correct NULL cast.
 104         * frv-opc.h: Regenerate.
 105
 106 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 109         MMX form.
 110         * i386-tbl.h: Re-generate.
 111
 112 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 113
 114         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 115         immediate in br.n instruction.
 116
 117 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-dis.c (XMGatherD, VexGatherD): New.
 120         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 121         (print_insn): Check masking for S/G insns.
 122         (OP_E_memory): New local variable check_gather. Extend mandatory
 123         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 124         Extend check for disallowed 16-bit addressing.
 125         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 126         if()s to switch(). Check register conflicts for (VEX-encoded)
 127         gathers. Drop no longer reachable cases.
 128         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 129         vgatherdp*.
 130
 131 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 134         zeroing-masking without masking.
 135
 136 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 137
 138         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 139         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 140         single-operand forms as deprecated.
 141         * i386-tbl.h: Re-generate.
 142
 143 2021-03-25  Alan Modra  <amodra@gmail.com>
 144
 145         PR 27647
 146         * ppc-opc.c (XLOCB_MASK): Delete.
 147         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 148         XLBH_MASK.
 149         (powerpc_opcodes): Accept a BH field on all extended forms of
 150         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 151
 152 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-gen.c (output_i386_opcode): Drop processing of
 155         opcode_length. Calculate length from base_opcode. Adjust prefix
 156         encoding determination.
 157         (process_i386_opcodes): Drop output of fake opcode_length.
 158         * i386-opc.h (struct insn_template): Drop opcode_length field.
 159         * i386-opc.tbl: Drop opcode length field from all templates.
 160         * i386-tbl.h: Re-generate.
 161
 162 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 165         parameter "prefix". Drop local variable "regular_encoding".
 166         Record prefix setting / check for consistency.
 167         (output_i386_opcode): Parse opcode_length and base_opcode
 168         earlier. Derive prefix encoding. Drop no longer applicable
 169         consistency checking. Adjust process_i386_opcode_modifier()
 170         invocation.
 171         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 172         invocation.
 173         * i386-tbl.h: Re-generate.
 174
 175 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 178         check.
 179         * i386-opc.h (Prefix_*): Move #define-s.
 180         * i386-opc.tbl: Move pseudo prefix enumerator values to
 181         extension opcode field. Introduce pseudopfx template.
 182         * i386-tbl.h: Re-generate.
 183
 184 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 187         comment.
 188         * i386-tbl.h: Re-generate.
 189
 190 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-opc.h (struct insn_template): Move cpu_flags field past
 193         opcode_modifier one.
 194         * i386-tbl.h: Re-generate.
 195
 196 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 199         * i386-opc.h (OpcodeSpace): New enumerator.
 200         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 201         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 202         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 203         (struct i386_opcode_modifier): New field opcodespace. Shrink
 204         opcodeprefix field.
 205         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 206         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 207         OpcodePrefix uses.
 208         * i386-tbl.h: Re-generate.
 209
 210 2021-03-22  Martin Liska  <mliska@suse.cz>
 211
 212         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 213         * arc-dis.c (parse_option): Likewise.
 214         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 215         * cris-dis.c (print_with_operands): Likewise.
 216         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 217         * i386-dis.c (print_insn): Likewise.
 218         * ia64-gen.c (fetch_insn_class): Likewise.
 219         (parse_resource_users): Likewise.
 220         (in_iclass): Likewise.
 221         (lookup_specifier): Likewise.
 222         (insert_opcode_dependencies): Likewise.
 223         * mips-dis.c (parse_mips_ase_option): Likewise.
 224         (parse_mips_dis_option): Likewise.
 225         * s390-dis.c (disassemble_init_s390): Likewise.
 226         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 227
 228 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 229
 230         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 231
 232 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 233
 234         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 235         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 236
 237 2021-03-12  Alan Modra  <amodra@gmail.com>
 238
 239         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 240
 241 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-dis.c (OP_XMM): Re-order checks.
 244
 245 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-dis.c (putop): Drop need_vex check when also checking
 248         vex.evex.
 249         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 250         checking vex.b.
 251
 252 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 255         checks. Move case label past broadcast check.
 256
 257 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 258
 259         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 260         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 261         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 262         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 263         EVEX_W_0F38C7_M_0_L_2): Delete.
 264         (REG_EVEX_0F38C7_M_0_L_2): New.
 265         (intel_operand_size): Handle VEX and EVEX the same for
 266         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 267         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 268         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 269         vex_vsib_q_w_d_mode uses.
 270         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 271         0F38A1, and 0F38A3 entries.
 272         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 273         entry.
 274         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 275         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 276         0F38A3 entries.
 277
 278 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 279
 280         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 281         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 282         MOD_VEX_0FXOP_09_12): Rename to ...
 283         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 284         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 285         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 286         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 287         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 288         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 289         (reg_table): Adjust comments.
 290         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 291         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 292         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 293         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 294         (vex_len_table): Adjust opcode 0A_12 entry.
 295         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 296         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 297         (rm_table): Move hreset entry.
 298
 299 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 300
 301         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 302         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 303         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 304         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 305         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 306         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 307         (get_valid_dis386): Also handle 512-bit vector length when
 308         vectoring into vex_len_table[].
 309         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 310         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 311         entries.
 312         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 313         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 314         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 315         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 316         entries.
 317
 318 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 319
 320         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 321         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 322         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 323         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 324         entries.
 325         * i386-dis-evex-len.h (evex_len_table): Likewise.
 326         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 327
 328 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 329
 330         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 331         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 332         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 333         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 334         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 335         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 336         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 337         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 338         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 339         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 340         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 341         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 342         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 343         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 344         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 345         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 346         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 347         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 348         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 349         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 350         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 351         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 352         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 353         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 354         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 355         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 356         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 357         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 358         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 359         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 360         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 361         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 362         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 363         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 364         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 365         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 366         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 367         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 368         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 369         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 370         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 371         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 372         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 373         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 374         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 375         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 376         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 377         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 378         EVEX_W_0F3A43_L_n): New.
 379         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 380         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 381         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 382         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 383         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 384         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 385         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 386         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 387         0F385B, 0F38C6, and 0F38C7 entries.
 388         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 389         0F38C6 and 0F38C7.
 390         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 391         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 392         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 393         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 394
 395 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 396
 397         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 398         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 399         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 400         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 401         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 402         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 403         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 404         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 405         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 406         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 407         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 408         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 409         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 410         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 411         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 412         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 413         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 414         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 415         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 416         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 417         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 418         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 419         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 420         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 421         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 422         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 423         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 424         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 425         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 426         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 427         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 428         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 429         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 430         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 431         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 432         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 433         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 434         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 435         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 436         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 437         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 438         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 439         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 440         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 441         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 442         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 443         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 444         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 445         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 446         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 447         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 448         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 449         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 450         VEX_W_0F99_P_2_LEN_0): Delete.
 451         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 452         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 453         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 454         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 455         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 456         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 457         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 458         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 459         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 460         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 461         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 462         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 463         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 464         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 465         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 466         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 467         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 468         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 469         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 470         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 471         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 472         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 473         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 474         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 475         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 476         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 477         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 478         (prefix_table): No longer link to vex_len_table[] for opcodes
 479         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 480         0F92, 0F93, 0F98, and 0F99.
 481         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 482         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 483         0F98, and 0F99.
 484         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 485         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 486         0F98, and 0F99.
 487         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 488         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 489         0F98, and 0F99.
 490         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 491         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 492         0F98, and 0F99.
 493
 494 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 495
 496         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 497         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 498         REG_VEX_0F73_M_0 respectively.
 499         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 500         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 501         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 502         MOD_VEX_0F73_REG_7): Delete.
 503         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 504         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 505         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 506         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 507         PREFIX_VEX_0F3AF0_L_0 respectively.
 508         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 509         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 510         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 511         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 512         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 513         VEX_LEN_0F38F7): New.
 514         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 515         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 516         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 517         0F38F3.
 518         (prefix_table): No longer link to vex_len_table[] for opcodes
 519         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 520         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 521         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 522         0F38F6, 0F38F7, and 0F3AF0.
 523         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 524         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 525         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 526         0F73.
 527
 528 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 529
 530         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 531         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 532         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 533         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 534         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 535         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 536         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 537         73.
 538         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 539         0F72, and 0F73.
 540         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 541         0F73.
 542
 543 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 544
 545         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 546         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 547         (reg_table): Don't link to mod_table[] where not needed. Add
 548         PREFIX_IGNORED to nop entries.
 549         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 550         (mod_table): Add nop entries next to prefetch ones. Drop
 551         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 552         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 553         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 554         PREFIX_OPCODE from endbr* entries.
 555         (get_valid_dis386): Also consider entry's name when zapping
 556         vindex.
 557         (print_insn): Handle PREFIX_IGNORED.
 558
 559 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 560
 561         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 562         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 563         element.
 564         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 565         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 566         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 567         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 568         (struct i386_opcode_modifier): Delete notrackprefixok,
 569         islockable, hleprefixok, and repprefixok fields. Add prefixok
 570         field.
 571         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 572         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 573         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 574         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 575         Replace HLEPrefixOk.
 576         * opcodes/i386-tbl.h: Re-generate.
 577
 578 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 579
 580         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 581         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 582         64-bit form.
 583         * opcodes/i386-tbl.h: Re-generate.
 584
 585 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 588         for {} instead of {0}. Don't look for '0'.
 589         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 590         size specifiers.
 591
 592 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 593
 594         PR 27158
 595         * riscv-dis.c (print_insn_args): Updated encoding macros.
 596         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 597         (match_c_addi16sp): Updated encoding macros.
 598         (match_c_lui): Likewise.
 599         (match_c_lui_with_hint): Likewise.
 600         (match_c_addi4spn): Likewise.
 601         (match_c_slli): Likewise.
 602         (match_slli_as_c_slli): Likewise.
 603         (match_c_slli64): Likewise.
 604         (match_srxi_as_c_srxi): Likewise.
 605         (riscv_insn_types): Added .insn css/cl/cs.
 606
 607 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 608
 609         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 610         (default_priv_spec): Updated type to riscv_spec_class.
 611         (parse_riscv_dis_option): Updated.
 612         * riscv-opc.c: Moved stuff and make the file tidy.
 613
 614 2021-02-17  Alan Modra  <amodra@gmail.com>
 615
 616         * wasm32-dis.c: Include limits.h.
 617         (CHAR_BIT): Provide backup define.
 618         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 619         Correct signed overflow checking.
 620
 621 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 624         * i386-tbl.h: Re-generate.
 625
 626 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 627
 628         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 629         Oword.
 630         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 631
 632 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 633
 634         * s390-mkopc.c (main): Accept arch14 as cpu string.
 635         * s390-opc.txt: Add new arch14 instructions.
 636
 637 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 638
 639         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 640         favour of LIBINTL.
 641         * configure: Regenerated.
 642
 643 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 644
 645         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 646         * tic54x-opc.c (regs): Rename to ...
 647         (tic54x_regs): ... this.
 648         (mmregs): Rename to ...
 649         (tic54x_mmregs): ... this.
 650         (condition_codes): Rename to ...
 651         (tic54x_condition_codes): ... this.
 652         (cc2_codes): Rename to ...
 653         (tic54x_cc2_codes): ... this.
 654         (cc3_codes): Rename to ...
 655         (tic54x_cc3_codes): ... this.
 656         (status_bits): Rename to ...
 657         (tic54x_status_bits): ... this.
 658         (misc_symbols): Rename to ...
 659         (tic54x_misc_symbols): ... this.
 660
 661 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 662
 663         * riscv-opc.c (MASK_RVB_IMM): Removed.
 664         (riscv_opcodes): Removed zb* instructions.
 665         (riscv_ext_version_table): Removed versions for zb*.
 666
 667 2021-01-26  Alan Modra  <amodra@gmail.com>
 668
 669         * i386-gen.c (parse_template): Ensure entire template_instance
 670         is initialised.
 671
 672 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 673
 674         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 675         (riscv_fpr_names_abi): Likewise.
 676         (riscv_opcodes): Likewise.
 677         (riscv_insn_types): Likewise.
 678
 679 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 680
 681         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 682
 683 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 684
 685         * riscv-dis.c: Comments tidy and improvement.
 686         * riscv-opc.c: Likewise.
 687
 688 2021-01-13  Alan Modra  <amodra@gmail.com>
 689
 690         * Makefile.in: Regenerate.
 691
 692 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 693
 694         PR binutils/26792
 695         * configure.ac: Use GNU_MAKE_JOBSERVER.
 696         * aclocal.m4: Regenerated.
 697         * configure: Likewise.
 698
 699 2021-01-12  Nick Clifton  <nickc@redhat.com>
 700
 701         * po/sr.po: Updated Serbian translation.
 702
 703 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 704
 705         PR ld/27173
 706         * configure: Regenerated.
 707
 708 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 709
 710         * aarch64-asm-2.c: Regenerate.
 711         * aarch64-dis-2.c: Likewise.
 712         * aarch64-opc-2.c: Likewise.
 713         * aarch64-opc.c (aarch64_print_operand):
 714         Delete handling of AARCH64_OPND_CSRE_CSR.
 715         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 716         (CSRE): Likewise.
 717         (_CSRE_INSN): Likewise.
 718         (aarch64_opcode_table): Delete csr.
 719
 720 2021-01-11  Nick Clifton  <nickc@redhat.com>
 721
 722         * po/de.po: Updated German translation.
 723         * po/fr.po: Updated French translation.
 724         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 725         * po/sv.po: Updated Swedish translation.
 726         * po/uk.po: Updated Ukranian translation.
 727
 728 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 729
 730         * configure: Regenerated.
 731
 732 2021-01-09  Nick Clifton  <nickc@redhat.com>
 733
 734         * configure: Regenerate.
 735         * po/opcodes.pot: Regenerate.
 736
 737 2021-01-09  Nick Clifton  <nickc@redhat.com>
 738
 739         * 2.36 release branch crated.
 740
 741 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 742
 743         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 744         (DW, (XRC_MASK): Define.
 745         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 746
 747 2021-01-09  Alan Modra  <amodra@gmail.com>
 748
 749         * configure: Regenerate.
 750
 751 2021-01-08  Nick Clifton  <nickc@redhat.com>
 752
 753         * po/sv.po: Updated Swedish translation.
 754
 755 2021-01-08  Nick Clifton  <nickc@redhat.com>
 756
 757         PR 27129
 758         * aarch64-dis.c (determine_disassembling_preference): Move call to
 759         aarch64_match_operands_constraint outside of the assertion.
 760         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 761         Replace with a return of FALSE.
 762
 763         PR 27139
 764         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 765         core system register.
 766
 767 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 768
 769         * configure: Regenerate.
 770
 771 2021-01-07  Nick Clifton  <nickc@redhat.com>
 772
 773         * po/fr.po: Updated French translation.
 774
 775 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 776
 777         * m68k-opc.c (chkl): Change minimum architecture requirement to
 778         m68020.
 779
 780 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 781
 782         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 783
 784 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 785             Jim Wilson  <jimw@sifive.com>
 786             Andrew Waterman  <andrew@sifive.com>
 787             Maxim Blinov  <maxim.blinov@embecosm.com>
 788             Kito Cheng  <kito.cheng@sifive.com>
 789             Nelson Chu  <nelson.chu@sifive.com>
 790
 791         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 792         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 793
 794 2021-01-01  Alan Modra  <amodra@gmail.com>
 795
 796         Update year range in copyright notice of all files.
 797
 798 For older changes see ChangeLog-2020
 799 \f
 800 Copyright (C) 2021 Free Software Foundation, Inc.
 801
 802 Copying and distribution of this file, with or without modification,
 803 are permitted in any medium without royalty provided the copyright
 804 notice and this notice are preserved.
 805
 806 Local Variables:
 807 mode: change-log
 808 left-margin: 8
 809 fill-column: 74
 810 version-control: never
 811 End: