opcodes/ChangeLog

   1 2018-07-24  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
   4         vcvtusi2ss, and vcvtusi2sd.
   5         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
   6         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
   7         * i386-tbl.h: Re-generate.
   8
   9 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
  10
  11         * arc-opc.c (extract_w6): Fix extending the sign.
  12
  13 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
  14
  15         * arc-tbl.h (vewt): Allow it for ARC EM family.
  16
  17 2018-07-23  Alan Modra  <amodra@gmail.com>
  18
  19         PR 23419
  20         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
  21         opcode variants for mtspr/mfspr encodings.
  22
  23 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
  24             Maciej W. Rozycki  <macro@mips.com>
  25
  26         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
  27         loongson3a descriptors.
  28         (parse_mips_ase_option): Handle -M loongson-mmi option.
  29         (print_mips_disassembler_options): Document -M loongson-mmi.
  30         * mips-opc.c (LMMI): New macro.
  31         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
  32         instructions.
  33
  34 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  37         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
  38         IgnoreSize and [XYZ]MMword where applicable.
  39         * i386-tbl.h: Re-generate.
  40
  41 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
  44         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
  45         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
  46         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
  47         * i386-tbl.h: Re-generate.
  48
  49 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
  52         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
  53         VPCLMULQDQ templates into their respective AVX512VL counterparts
  54         where possible, using Disp8ShiftVL and CheckRegSize instead of
  55         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
  56         * i386-tbl.h: Re-generate.
  57
  58 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-opc.tbl: Fold AVX512DQ templates into their respective
  61         AVX512VL counterparts where possible, using Disp8ShiftVL and
  62         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  63         IgnoreSize) as appropriate.
  64         * i386-tbl.h: Re-generate.
  65
  66 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.tbl: Fold AVX512BW templates into their respective
  69         AVX512VL counterparts where possible, using Disp8ShiftVL and
  70         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  71         IgnoreSize) as appropriate.
  72         * i386-tbl.h: Re-generate.
  73
  74 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-opc.tbl: Fold AVX512CD templates into their respective
  77         AVX512VL counterparts where possible, using Disp8ShiftVL and
  78         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  79         IgnoreSize) as appropriate.
  80         * i386-tbl.h: Re-generate.
  81
  82 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-opc.h (DISP8_SHIFT_VL): New.
  85         * i386-opc.tbl (Disp8ShiftVL):  Define.
  86         (various): Fold AVX512VL templates into their respective
  87         AVX512F counterparts where possible, using Disp8ShiftVL and
  88         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  89         IgnoreSize) as appropriate.
  90         * i386-tbl.h: Re-generate.
  91
  92 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  93
  94         * Makefile.am: Change dependencies and rule for
  95         $(srcdir)/i386-init.h.
  96         * Makefile.in: Re-generate.
  97         * i386-gen.c (process_i386_opcodes): New local variable
  98         "marker". Drop opening of input file. Recognize marker and line
  99         number directives.
 100         * i386-opc.tbl (OPCODE_I386_H): Define.
 101         (i386-opc.h): Include it.
 102         (None): Undefine.
 103
 104 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 105
 106         PR gas/23418
 107         * i386-opc.h (Byte): Update comments.
 108         (Word): Likewise.
 109         (Dword): Likewise.
 110         (Fword): Likewise.
 111         (Qword): Likewise.
 112         (Tbyte): Likewise.
 113         (Xmmword): Likewise.
 114         (Ymmword): Likewise.
 115         (Zmmword): Likewise.
 116         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 117         vcvttps2uqq.
 118         * i386-tbl.h: Regenerated.
 119
 120 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 121
 122         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 123         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 124         * aarch64-asm-2.c: Regenerate.
 125         * aarch64-dis-2.c: Regenerate.
 126         * aarch64-opc-2.c: Regenerate.
 127
 128 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 129
 130         PR binutils/23192
 131         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 132         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 133         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 134         sqdmulh, sqrdmulh): Use Em16.
 135
 136 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 137
 138         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 139         csdb together with them.
 140         (thumb32_opcodes): Likewise.
 141
 142 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 145         requiring 32-bit registers as operands 2 and 3. Improve
 146         comments.
 147         (mwait, mwaitx): Fold templates. Improve comments.
 148         OPERAND_TYPE_INOUTPORTREG.
 149         * i386-tbl.h: Re-generate.
 150
 151 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-gen.c (operand_type_init): Remove
 154         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 155         OPERAND_TYPE_INOUTPORTREG.
 156         * i386-init.h: Re-generate.
 157
 158 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 161         (wrssq, wrussq): Add Qword.
 162         * i386-tbl.h: Re-generate.
 163
 164 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-opc.h: Rename OTMax to OTNum.
 167         (OTNumOfUints): Adjust calculation.
 168         (OTUnused): Directly alias to OTNum.
 169
 170 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 171
 172         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 173         `reg_xys'.
 174         (lea_reg_xys): Likewise.
 175         (print_insn_loop_primitive): Rename `reg' local variable to
 176         `reg_dxy'.
 177
 178 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 179
 180         PR binutils/23242
 181         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 182
 183 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 184
 185         PR binutils/23369
 186         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 187         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 188
 189 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 190
 191         PR tdep/8282
 192         * mips-dis.c (mips_option_arg_t): New enumeration.
 193         (mips_options): New variable.
 194         (disassembler_options_mips): New function.
 195         (print_mips_disassembler_options): Reimplement in terms of
 196         `disassembler_options_mips'.
 197         * arm-dis.c (disassembler_options_arm): Adapt to using the
 198         `disasm_options_and_args_t' structure.
 199         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 200         * s390-dis.c (disassembler_options_s390): Likewise.
 201
 202 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 203
 204         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 205         expected result.
 206         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 207         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 208         * testsuite/ld-arm/tls-longplt.d: Likewise.
 209
 210 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 211
 212         PR binutils/23192
 213         * aarch64-asm-2.c: Regenerate.
 214         * aarch64-dis-2.c: Likewise.
 215         * aarch64-opc-2.c: Likewise.
 216         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 217         * aarch64-opc.c (operand_general_constraint_met_p,
 218         aarch64_print_operand): Likewise.
 219         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 220         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 221         fmlal2, fmlsl2.
 222         (AARCH64_OPERANDS): Add Em2.
 223
 224 2018-06-26  Nick Clifton  <nickc@redhat.com>
 225
 226         * po/uk.po: Updated Ukranian translation.
 227         * po/de.po: Updated German translation.
 228         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 229
 230 2018-06-26  Nick Clifton  <nickc@redhat.com>
 231
 232         * nfp-dis.c: Fix spelling mistake.
 233
 234 2018-06-24  Nick Clifton  <nickc@redhat.com>
 235
 236         * configure: Regenerate.
 237         * po/opcodes.pot: Regenerate.
 238
 239 2018-06-24  Nick Clifton  <nickc@redhat.com>
 240
 241         2.31 branch created.
 242
 243 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 244
 245         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 246         * aarch64-asm-2.c: Regenerate.
 247         * aarch64-dis-2.c: Likewise.
 248
 249 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 250
 251         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 252         `-M ginv' option description.
 253
 254 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 255
 256         PR gas/23305
 257         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 258         la and lla.
 259
 260 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 261
 262         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 263         * configure.ac: Remove AC_PREREQ.
 264         * Makefile.in: Re-generate.
 265         * aclocal.m4: Re-generate.
 266         * configure: Re-generate.
 267
 268 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 269
 270         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 271         mips64r6 descriptors.
 272         (parse_mips_ase_option): Handle -Mginv option.
 273         (print_mips_disassembler_options): Document -Mginv.
 274         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 275         (GINV): New macro.
 276         (mips_opcodes): Define ginvi and ginvt.
 277
 278 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 279             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 280
 281         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 282         * mips-opc.c (CRC, CRC64): New macros.
 283         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 284         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 285         crc32cd for CRC64.
 286
 287 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 288
 289         PR 20319
 290         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 291         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 292
 293 2018-06-06  Alan Modra  <amodra@gmail.com>
 294
 295         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 296         setjmp.  Move init for some other vars later too.
 297
 298 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 299
 300         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 301         (dis_private): Add new fields for property section tracking.
 302         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 303         (xtensa_instruction_fits): New functions.
 304         (fetch_data): Bump minimal fetch size to 4.
 305         (print_insn_xtensa): Make struct dis_private static.
 306         Load and prepare property table on section change.
 307         Don't disassemble literals. Don't disassemble instructions that
 308         cross property table boundaries.
 309
 310 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 311
 312         * configure: Regenerated.
 313
 314 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 317         * i386-tbl.h: Re-generate.
 318
 319 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.tbl (sldt, str): Add NoRex64.
 322         * i386-tbl.h: Re-generate.
 323
 324 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 325
 326         * i386-opc.tbl (invpcid): Add Oword.
 327         * i386-tbl.h: Re-generate.
 328
 329 2018-06-01  Alan Modra  <amodra@gmail.com>
 330
 331         * sysdep.h (_bfd_error_handler): Don't declare.
 332         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 333         * rl78-decode.opc: Likewise.
 334         * msp430-decode.c: Regenerate.
 335         * rl78-decode.c: Regenerate.
 336
 337 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 338
 339         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 340         * i386-init.h : Regenerated.
 341
 342 2018-05-25  Alan Modra  <amodra@gmail.com>
 343
 344         * Makefile.in: Regenerate.
 345         * po/POTFILES.in: Regenerate.
 346
 347 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 348
 349         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 350         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 351         (insert_bab, extract_bab, insert_btab, extract_btab,
 352         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 353         (BAT, BBA VBA RBS XB6S): Delete macros.
 354         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 355         (BB, BD, RBX, XC6): Update for new macros.
 356         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 357         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 358         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 359         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 360
 361 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 362
 363         * Makefile.am: Add support for s12z architecture.
 364         * configure.ac: Likewise.
 365         * disassemble.c: Likewise.
 366         * disassemble.h: Likewise.
 367         * Makefile.in: Regenerate.
 368         * configure: Regenerate.
 369         * s12z-dis.c: New file.
 370         * s12z.h: New file.
 371
 372 2018-05-18  Alan Modra  <amodra@gmail.com>
 373
 374         * nfp-dis.c: Don't #include libbfd.h.
 375         (init_nfp3200_priv): Use bfd_get_section_contents.
 376         (nit_nfp6000_mecsr_sec): Likewise.
 377
 378 2018-05-17  Nick Clifton  <nickc@redhat.com>
 379
 380         * po/zh_CN.po: Updated simplified Chinese translation.
 381
 382 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 383
 384         PR binutils/23109
 385         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 386         * aarch64-dis-2.c: Regenerate.
 387
 388 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 389
 390         PR binutils/21446
 391         * aarch64-asm.c (opintl.h): Include.
 392         (aarch64_ins_sysreg): Enforce read/write constraints.
 393         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 394         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 395         (F_REG_READ, F_REG_WRITE): New.
 396         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 397         AARCH64_OPND_SYSREG.
 398         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 399         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 400         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 401         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 402         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 403         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 404         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 405         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 406         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 407         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 408         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 409         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 410         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 411         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 412         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 413         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 414         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 415
 416 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 417
 418         PR binutils/21446
 419         * aarch64-dis.c (no_notes: New.
 420         (parse_aarch64_dis_option): Support notes.
 421         (aarch64_decode_insn, print_operands): Likewise.
 422         (print_aarch64_disassembler_options): Document notes.
 423         * aarch64-opc.c (aarch64_print_operand): Support notes.
 424
 425 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 426
 427         PR binutils/21446
 428         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 429         and take error struct.
 430         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 431         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 432         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 433         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 434         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 435         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 436         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 437         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 438         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 439         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 440         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 441         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 442         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 443         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 444         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 445         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 446         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 447         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 448         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 449         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 450         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 451         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 452         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 453         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 454         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 455         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 456         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 457         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 458         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 459         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 460         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 461         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 462         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 463         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 464         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 465         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 466         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 467         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 468         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 469         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 470         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 471         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 472         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 473         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 474         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 475         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 476         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 477         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 478         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 479         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 480         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 481         (determine_disassembling_preference, aarch64_decode_insn,
 482         print_insn_aarch64_word, print_insn_data): Take errors struct.
 483         (print_insn_aarch64): Use errors.
 484         * aarch64-asm-2.c: Regenerate.
 485         * aarch64-dis-2.c: Regenerate.
 486         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 487         boolean in aarch64_insert_operan.
 488         (print_operand_extractor): Likewise.
 489         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 490
 491 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 492
 493         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 494
 495 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 496
 497         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 498
 499 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 500
 501         * cr16-opc.c (cr16_instruction): Comment typo fix.
 502         * hppa-dis.c (print_insn_hppa): Likewise.
 503
 504 2018-05-08  Jim Wilson  <jimw@sifive.com>
 505
 506         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 507         (match_c_slli64, match_srxi_as_c_srxi): New.
 508         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 509         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 510         <c.slli, c.srli, c.srai>: Use match_s_slli.
 511         <c.slli64, c.srli64, c.srai64>: New.
 512
 513 2018-05-08  Alan Modra  <amodra@gmail.com>
 514
 515         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 516         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 517         partition opcode space for index lookup.
 518
 519 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 520
 521         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 522         <insn_length>: ...with this.  Update usage.
 523         Remove duplicate call to *info->memory_error_func.
 524
 525 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 526             H.J. Lu  <hongjiu.lu@intel.com>
 527
 528         * i386-dis.c (Gva): New.
 529         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 530         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 531         (prefix_table): New instructions (see prefix above).
 532         (mod_table): New instructions (see prefix above).
 533         (OP_G): Handle va_mode.
 534         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 535         CPU_MOVDIR64B_FLAGS.
 536         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 537         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 538         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 539         * i386-opc.tbl: Add movidir{i,64b}.
 540         * i386-init.h: Regenerated.
 541         * i386-tbl.h: Likewise.
 542
 543 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 544
 545         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 546         AddrPrefixOpReg.
 547         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 548         (AddrPrefixOpReg): This.
 549         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 550         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 551
 552 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 553
 554         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 555         (vle_num_opcodes): Likewise.
 556         (spe2_num_opcodes): Likewise.
 557         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 558         initialization loop.
 559         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 560         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 561         only once.
 562
 563 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 564
 565         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 566
 567 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 568
 569         Makefile.am: Added nfp-dis.c.
 570         configure.ac: Added bfd_nfp_arch.
 571         disassemble.h: Added print_insn_nfp prototype.
 572         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 573         nfp-dis.c: New, for NFP support.
 574         po/POTFILES.in: Added nfp-dis.c to the list.
 575         Makefile.in: Regenerate.
 576         configure: Regenerate.
 577
 578 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 581         templates into their base ones.
 582         * i386-tlb.h: Re-generate.
 583
 584 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 587         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 588         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 589         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 590         * i386-init.h: Re-generate.
 591
 592 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 595         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 596         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 597         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 598         comment.
 599         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 600         and CpuRegMask.
 601         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 602         CpuRegMask: Delete.
 603         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 604         cpuregzmm, and cpuregmask.
 605         * i386-init.h: Re-generate.
 606         * i386-tbl.h: Re-generate.
 607
 608 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 611         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 612         * i386-init.h: Re-generate.
 613
 614 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-gen.c (VexImmExt): Delete.
 617         * i386-opc.h (VexImmExt, veximmext): Delete.
 618         * i386-opc.tbl: Drop all VexImmExt uses.
 619         * i386-tlb.h: Re-generate.
 620
 621 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 624         register-only forms.
 625         * i386-tlb.h: Re-generate.
 626
 627 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 628
 629         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 630
 631 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 632
 633         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 634         PREFIX_0F1C.
 635         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 636         (cpu_flags): Add CpuCLDEMOTE.
 637         * i386-init.h: Regenerate.
 638         * i386-opc.h (enum): Add CpuCLDEMOTE,
 639         (i386_cpu_flags): Add cpucldemote.
 640         * i386-opc.tbl: Add cldemote.
 641         * i386-tbl.h: Regenerate.
 642
 643 2018-04-16  Alan Modra  <amodra@gmail.com>
 644
 645         * Makefile.am: Remove sh5 and sh64 support.
 646         * configure.ac: Likewise.
 647         * disassemble.c: Likewise.
 648         * disassemble.h: Likewise.
 649         * sh-dis.c: Likewise.
 650         * sh64-dis.c: Delete.
 651         * sh64-opc.c: Delete.
 652         * sh64-opc.h: Delete.
 653         * Makefile.in: Regenerate.
 654         * configure: Regenerate.
 655         * po/POTFILES.in: Regenerate.
 656
 657 2018-04-16  Alan Modra  <amodra@gmail.com>
 658
 659         * Makefile.am: Remove w65 support.
 660         * configure.ac: Likewise.
 661         * disassemble.c: Likewise.
 662         * disassemble.h: Likewise.
 663         * w65-dis.c: Delete.
 664         * w65-opc.h: Delete.
 665         * Makefile.in: Regenerate.
 666         * configure: Regenerate.
 667         * po/POTFILES.in: Regenerate.
 668
 669 2018-04-16  Alan Modra  <amodra@gmail.com>
 670
 671         * configure.ac: Remove we32k support.
 672         * configure: Regenerate.
 673
 674 2018-04-16  Alan Modra  <amodra@gmail.com>
 675
 676         * Makefile.am: Remove m88k support.
 677         * configure.ac: Likewise.
 678         * disassemble.c: Likewise.
 679         * disassemble.h: Likewise.
 680         * m88k-dis.c: Delete.
 681         * Makefile.in: Regenerate.
 682         * configure: Regenerate.
 683         * po/POTFILES.in: Regenerate.
 684
 685 2018-04-16  Alan Modra  <amodra@gmail.com>
 686
 687         * Makefile.am: Remove i370 support.
 688         * configure.ac: Likewise.
 689         * disassemble.c: Likewise.
 690         * disassemble.h: Likewise.
 691         * i370-dis.c: Delete.
 692         * i370-opc.c: Delete.
 693         * Makefile.in: Regenerate.
 694         * configure: Regenerate.
 695         * po/POTFILES.in: Regenerate.
 696
 697 2018-04-16  Alan Modra  <amodra@gmail.com>
 698
 699         * Makefile.am: Remove h8500 support.
 700         * configure.ac: Likewise.
 701         * disassemble.c: Likewise.
 702         * disassemble.h: Likewise.
 703         * h8500-dis.c: Delete.
 704         * h8500-opc.h: Delete.
 705         * Makefile.in: Regenerate.
 706         * configure: Regenerate.
 707         * po/POTFILES.in: Regenerate.
 708
 709 2018-04-16  Alan Modra  <amodra@gmail.com>
 710
 711         * configure.ac: Remove tahoe support.
 712         * configure: Regenerate.
 713
 714 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 715
 716         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 717         umwait.
 718         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 719         64-bit mode.
 720         * i386-tbl.h: Regenerated.
 721
 722 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 723
 724         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 725         PREFIX_MOD_1_0FAE_REG_6.
 726         (va_mode): New.
 727         (OP_E_register): Use va_mode.
 728         * i386-dis-evex.h (prefix_table):
 729         New instructions (see prefixes above).
 730         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 731         (cpu_flags): Likewise.
 732         * i386-opc.h (enum): Likewise.
 733         (i386_cpu_flags): Likewise.
 734         * i386-opc.tbl: Add umonitor, umwait, tpause.
 735         * i386-init.h: Regenerate.
 736         * i386-tbl.h: Likewise.
 737
 738 2018-04-11  Alan Modra  <amodra@gmail.com>
 739
 740         * opcodes/i860-dis.c: Delete.
 741         * opcodes/i960-dis.c: Delete.
 742         * Makefile.am: Remove i860 and i960 support.
 743         * configure.ac: Likewise.
 744         * disassemble.c: Likewise.
 745         * disassemble.h: Likewise.
 746         * Makefile.in: Regenerate.
 747         * configure: Regenerate.
 748         * po/POTFILES.in: Regenerate.
 749
 750 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 751
 752         PR binutils/23025
 753         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 754         to 0.
 755         (print_insn): Clear vex instead of vex.evex.
 756
 757 2018-04-04  Nick Clifton  <nickc@redhat.com>
 758
 759         * po/es.po: Updated Spanish translation.
 760
 761 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-gen.c (opcode_modifiers): Delete VecESize.
 764         * i386-opc.h (VecESize): Delete.
 765         (struct i386_opcode_modifier): Delete vecesize.
 766         * i386-opc.tbl: Drop VecESize.
 767         * i386-tlb.h: Re-generate.
 768
 769 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 772         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 773         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 774         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 775         * i386-tlb.h: Re-generate.
 776
 777 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 778
 779         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 780         Fold AVX512 forms
 781         * i386-tlb.h: Re-generate.
 782
 783 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 784
 785         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 786         (vex_len_table): Drop Y for vcvt*2si.
 787         (putop): Replace plain 'Y' handling by abort().
 788
 789 2018-03-28  Nick Clifton  <nickc@redhat.com>
 790
 791         PR 22988
 792         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 793         instructions with only a base address register.
 794         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 795         handle AARHC64_OPND_SVE_ADDR_R.
 796         (aarch64_print_operand): Likewise.
 797         * aarch64-asm-2.c: Regenerate.
 798         * aarch64_dis-2.c: Regenerate.
 799         * aarch64-opc-2.c: Regenerate.
 800
 801 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 802
 803         * i386-opc.tbl: Drop VecESize from register only insn forms and
 804         memory forms not allowing broadcast.
 805         * i386-tlb.h: Re-generate.
 806
 807 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 810         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 811         sha256*): Drop Disp<N>.
 812
 813 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 814
 815         * i386-dis.c (EbndS, bnd_swap_mode): New.
 816         (prefix_table): Use EbndS.
 817         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 818         * i386-opc.tbl (bndmov): Move misplaced Load.
 819         * i386-tlb.h: Re-generate.
 820
 821 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 822
 823         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 824         templates allowing memory operands and folded ones for register
 825         only flavors.
 826         * i386-tlb.h: Re-generate.
 827
 828 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 831         256-bit templates. Drop redundant leftover Disp<N>.
 832         * i386-tlb.h: Re-generate.
 833
 834 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 835
 836         * riscv-opc.c (riscv_insn_types): New.
 837
 838 2018-03-13  Nick Clifton  <nickc@redhat.com>
 839
 840         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 841
 842 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 843
 844         * i386-opc.tbl: Add Optimize to clr.
 845         * i386-tbl.h: Regenerated.
 846
 847 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 848
 849         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 850         * i386-opc.h (OldGcc): Removed.
 851         (i386_opcode_modifier): Remove oldgcc.
 852         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 853         instructions for old (<= 2.8.1) versions of gcc.
 854         * i386-tbl.h: Regenerated.
 855
 856 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 857
 858         * i386-opc.h (EVEXDYN): New.
 859         * i386-opc.tbl: Fold various AVX512VL templates.
 860         * i386-tlb.h: Re-generate.
 861
 862 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 863
 864         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 865         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 866         vpexpandd, vpexpandq): Fold AFX512VF templates.
 867         * i386-tlb.h: Re-generate.
 868
 869 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 870
 871         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 872         Fold 128- and 256-bit VEX-encoded templates.
 873         * i386-tlb.h: Re-generate.
 874
 875 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 876
 877         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 878         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 879         vpexpandd, vpexpandq): Fold AVX512F templates.
 880         * i386-tlb.h: Re-generate.
 881
 882 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 885         64-bit templates. Drop Disp<N>.
 886         * i386-tlb.h: Re-generate.
 887
 888 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 889
 890         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 891         and 256-bit templates.
 892         * i386-tlb.h: Re-generate.
 893
 894 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 895
 896         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 897         * i386-tlb.h: Re-generate.
 898
 899 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 902         Drop NoAVX.
 903         * i386-tlb.h: Re-generate.
 904
 905 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 906
 907         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 908         * i386-tlb.h: Re-generate.
 909
 910 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 911
 912         * i386-gen.c (opcode_modifiers): Delete FloatD.
 913         * i386-opc.h (FloatD): Delete.
 914         (struct i386_opcode_modifier): Delete floatd.
 915         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 916         FloatD by D.
 917         * i386-tlb.h: Re-generate.
 918
 919 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 920
 921         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 922
 923 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 924
 925         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 926         * i386-tlb.h: Re-generate.
 927
 928 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 931         forms.
 932         * i386-tlb.h: Re-generate.
 933
 934 2018-03-07  Alan Modra  <amodra@gmail.com>
 935
 936         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 937         bfd_arch_rs6000.
 938         * disassemble.h (print_insn_rs6000): Delete.
 939         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 940         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 941         (print_insn_rs6000): Delete.
 942
 943 2018-03-03  Alan Modra  <amodra@gmail.com>
 944
 945         * sysdep.h (opcodes_error_handler): Define.
 946         (_bfd_error_handler): Declare.
 947         * Makefile.am: Remove stray #.
 948         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 949         EDIT" comment.
 950         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 951         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 952         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 953         opcodes_error_handler to print errors.  Standardize error messages.
 954         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 955         and include opintl.h.
 956         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 957         * i386-gen.c: Standardize error messages.
 958         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 959         * Makefile.in: Regenerate.
 960         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 961         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 962         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 963         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 964         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 965         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 966         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 967         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 968         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 969         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 970         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 971         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 972         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 973
 974 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 975
 976         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 977         vpsub[bwdq] instructions.
 978         * i386-tbl.h: Regenerated.
 979
 980 2018-03-01  Alan Modra  <amodra@gmail.com>
 981
 982         * configure.ac (ALL_LINGUAS): Sort.
 983         * configure: Regenerate.
 984
 985 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 986
 987         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 988         macro by assignements.
 989
 990 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 991
 992         PR gas/22871
 993         * i386-gen.c (opcode_modifiers): Add Optimize.
 994         * i386-opc.h (Optimize): New enum.
 995         (i386_opcode_modifier): Add optimize.
 996         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 997         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 998         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 999         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1000         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1001         vpxord and vpxorq.
1002         * i386-tbl.h: Regenerated.
1003
1004 2018-02-26  Alan Modra  <amodra@gmail.com>
1005
1006         * crx-dis.c (getregliststring): Allocate a large enough buffer
1007         to silence false positive gcc8 warning.
1008
1009 2018-02-22  Shea Levy <shea@shealevy.com>
1010
1011         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1012
1013 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1014
1015         * i386-opc.tbl: Add {rex},
1016         * i386-tbl.h: Regenerated.
1017
1018 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1019
1020         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1021         (mips16_opcodes): Replace `M' with `m' for "restore".
1022
1023 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1024
1025         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1026
1027 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1028
1029         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1030         variable to `function_index'.
1031
1032 2018-02-13  Nick Clifton  <nickc@redhat.com>
1033
1034         PR 22823
1035         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1036         about truncation of printing.
1037
1038 2018-02-12  Henry Wong <henry@stuffedcow.net>
1039
1040         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1041
1042 2018-02-05  Nick Clifton  <nickc@redhat.com>
1043
1044         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1045
1046 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1047
1048         * i386-dis.c (enum): Add pconfig.
1049         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1050         (cpu_flags): Add CpuPCONFIG.
1051         * i386-opc.h (enum): Add CpuPCONFIG.
1052         (i386_cpu_flags): Add cpupconfig.
1053         * i386-opc.tbl: Add PCONFIG instruction.
1054         * i386-init.h: Regenerate.
1055         * i386-tbl.h: Likewise.
1056
1057 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1058
1059         * i386-dis.c (enum): Add PREFIX_0F09.
1060         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1061         (cpu_flags): Add CpuWBNOINVD.
1062         * i386-opc.h (enum): Add CpuWBNOINVD.
1063         (i386_cpu_flags): Add cpuwbnoinvd.
1064         * i386-opc.tbl: Add WBNOINVD instruction.
1065         * i386-init.h: Regenerate.
1066         * i386-tbl.h: Likewise.
1067
1068 2018-01-17  Jim Wilson  <jimw@sifive.com>
1069
1070         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1071
1072 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1073
1074         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1075         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1076         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1077         (cpu_flags): Add CpuIBT, CpuSHSTK.
1078         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1079         (i386_cpu_flags): Add cpuibt, cpushstk.
1080         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1081         * i386-init.h: Regenerate.
1082         * i386-tbl.h: Likewise.
1083
1084 2018-01-16  Nick Clifton  <nickc@redhat.com>
1085
1086         * po/pt_BR.po: Updated Brazilian Portugese translation.
1087         * po/de.po: Updated German translation.
1088
1089 2018-01-15  Jim Wilson  <jimw@sifive.com>
1090
1091         * riscv-opc.c (match_c_nop): New.
1092         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1093
1094 2018-01-15  Nick Clifton  <nickc@redhat.com>
1095
1096         * po/uk.po: Updated Ukranian translation.
1097
1098 2018-01-13  Nick Clifton  <nickc@redhat.com>
1099
1100         * po/opcodes.pot: Regenerated.
1101
1102 2018-01-13  Nick Clifton  <nickc@redhat.com>
1103
1104         * configure: Regenerate.
1105
1106 2018-01-13  Nick Clifton  <nickc@redhat.com>
1107
1108         2.30 branch created.
1109
1110 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1111
1112         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1113         * i386-tbl.h: Regenerate.
1114
1115 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1116
1117         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1118         * i386-tbl.h: Re-generate.
1119
1120 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1121
1122         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1123         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1124         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1125         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1126         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1127         Disp8MemShift of AVX512VL forms.
1128         * i386-tbl.h: Re-generate.
1129
1130 2018-01-09  Jim Wilson  <jimw@sifive.com>
1131
1132         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1133         then the hi_addr value is zero.
1134
1135 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1136
1137         * arm-dis.c (arm_opcodes): Add csdb.
1138         (thumb32_opcodes): Add csdb.
1139
1140 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1141
1142         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1143         * aarch64-asm-2.c: Regenerate.
1144         * aarch64-dis-2.c: Regenerate.
1145         * aarch64-opc-2.c: Regenerate.
1146
1147 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1148
1149         PR gas/22681
1150         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1151         Remove AVX512 vmovd with 64-bit operands.
1152         * i386-tbl.h: Regenerated.
1153
1154 2018-01-05  Jim Wilson  <jimw@sifive.com>
1155
1156         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1157         jalr.
1158
1159 2018-01-03  Alan Modra  <amodra@gmail.com>
1160
1161         Update year range in copyright notice of all files.
1162
1163 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1164
1165         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1166         and OPERAND_TYPE_REGZMM entries.
1167
1168 For older changes see ChangeLog-2017
1169 \f
1170 Copyright (C) 2018 Free Software Foundation, Inc.
1171
1172 Copying and distribution of this file, with or without modification,
1173 are permitted in any medium without royalty provided the copyright
1174 notice and this notice are preserved.
1175
1176 Local Variables:
1177 mode: change-log
1178 left-margin: 8
1179 fill-column: 74
1180 version-control: never
1181 End: