opcodes/ChangeLog

   1 2020-03-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
   4         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
   5         * i386-tbl.h: Re-generate.
   6
   7 2020-03-06  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
  10         * i386-tbl.h: Re-generate.
  11
  12 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
  15         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
  16         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
  17         VexW0 on SSE2AVX variants.
  18         (vmovq): Drop NoRex64 from XMM/XMM variants.
  19         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
  20         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
  21         applicable use VexW0.
  22         * i386-tbl.h: Re-generate.
  23
  24 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  25
  26         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
  27         * i386-opc.h (Rex64): Delete.
  28         (struct i386_opcode_modifier): Remove rex64 field.
  29         * i386-opc.tbl (crc32): Drop Rex64.
  30         Replace Rex64 with Size64 everywhere else.
  31         * i386-tbl.h: Re-generate.
  32
  33 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-dis.c (OP_E_memory): Exclude recording of used address
  36         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
  37         addressed memory operands for MPX insns.
  38
  39 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
  42         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
  43         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
  44         (ptwrite): Split into non-64-bit and 64-bit forms.
  45         * i386-tbl.h: Re-generate.
  46
  47 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
  50         template.
  51         * i386-tbl.h: Re-generate.
  52
  53 2020-03-04  Jan Beulich  <jbeulich@suse.com>
  54
  55         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  56         (prefix_table): Move vmmcall here. Add vmgexit.
  57         (rm_table): Replace vmmcall entry by prefix_table[] escape.
  58         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
  59         (cpu_flags): Add CpuSEV_ES entry.
  60         * i386-opc.h (CpuSEV_ES): New.
  61         (union i386_cpu_flags): Add cpusev_es field.
  62         * i386-opc.tbl (vmgexit): New.
  63         * i386-init.h, i386-tbl.h: Re-generate.
  64
  65 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
  68         with MnemonicSize.
  69         * i386-opc.h (IGNORESIZE): New.
  70         (DEFAULTSIZE): Likewise.
  71         (IgnoreSize): Removed.
  72         (DefaultSize): Likewise.
  73         (MnemonicSize): New.
  74         (i386_opcode_modifier): Replace ignoresize/defaultsize with
  75         mnemonicsize.
  76         * i386-opc.tbl (IgnoreSize): New.
  77         (DefaultSize): Likewise.
  78         * i386-tbl.h: Regenerated.
  79
  80 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
  81
  82         PR 25627
  83         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
  84         instructions.
  85
  86 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  87
  88         PR gas/25622
  89         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
  90         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
  91         * i386-tbl.h: Regenerated.
  92
  93 2020-02-26  Alan Modra  <amodra@gmail.com>
  94
  95         * aarch64-asm.c: Indent labels correctly.
  96         * aarch64-dis.c: Likewise.
  97         * aarch64-gen.c: Likewise.
  98         * aarch64-opc.c: Likewise.
  99         * alpha-dis.c: Likewise.
 100         * i386-dis.c: Likewise.
 101         * nds32-asm.c: Likewise.
 102         * nfp-dis.c: Likewise.
 103         * visium-dis.c: Likewise.
 104
 105 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 106
 107         * arc-regs.h (int_vector_base): Make it available for all ARC
 108         CPUs.
 109
 110 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 111
 112         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 113         changed.
 114
 115 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 116
 117         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 118         c.mv/c.li if rs1 is zero.
 119
 120 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 121
 122         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 123         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 124         CPU_POPCNT_FLAGS.
 125         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 126         * i386-opc.h (CpuABM): Removed.
 127         (CpuPOPCNT): New.
 128         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 129         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 130         popcnt.  Remove CpuABM from lzcnt.
 131         * i386-init.h: Regenerated.
 132         * i386-tbl.h: Likewise.
 133
 134 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 135
 136         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 137         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 138         VexW1 instead of open-coding them.
 139         * i386-tbl.h: Re-generate.
 140
 141 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-opc.tbl (AddrPrefixOpReg): Define.
 144         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 145         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 146         templates. Drop NoRex64.
 147         * i386-tbl.h: Re-generate.
 148
 149 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 150
 151         PR gas/6518
 152         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 153         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 154         into Intel syntax instance (with Unpsecified) and AT&T one
 155         (without).
 156         (vcvtneps2bf16): Likewise, along with folding the two so far
 157         separate ones.
 158         * i386-tbl.h: Re-generate.
 159
 160 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 161
 162         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 163         CPU_ANY_SSE4A_FLAGS.
 164
 165 2020-02-17  Alan Modra  <amodra@gmail.com>
 166
 167         * i386-gen.c (cpu_flag_init): Correct last change.
 168
 169 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 170
 171         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 172         CPU_ANY_SSE4_FLAGS.
 173
 174 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 175
 176         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 177         (movzx): Likewise.
 178
 179 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 180
 181         PR gas/25438
 182         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 183         destination for Cpu64-only variant.
 184         (movzx): Fold patterns.
 185         * i386-tbl.h: Re-generate.
 186
 187 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 190         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 191         CPU_ANY_SSE4_FLAGS entry.
 192         * i386-init.h: Re-generate.
 193
 194 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 197         with Unspecified, making the present one AT&T syntax only.
 198         * i386-tbl.h: Re-generate.
 199
 200 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 203         * i386-tbl.h: Re-generate.
 204
 205 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 206
 207         PR gas/24546
 208         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 209         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 210         Amd64 and Intel64 templates.
 211         (call, jmp): Likewise for far indirect variants. Dro
 212         Unspecified.
 213         * i386-tbl.h: Re-generate.
 214
 215 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 216
 217         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 218         * i386-opc.h (ShortForm): Delete.
 219         (struct i386_opcode_modifier): Remove shortform field.
 220         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 221         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 222         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 223         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 224         Drop ShortForm.
 225         * i386-tbl.h: Re-generate.
 226
 227 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 230         fucompi): Drop ShortForm from operand-less templates.
 231         * i386-tbl.h: Re-generate.
 232
 233 2020-02-11  Alan Modra  <amodra@gmail.com>
 234
 235         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 236         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 237         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 238         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 239         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 240
 241 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 242
 243         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 244         (cde_opcodes): Add VCX* instructions.
 245
 246 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 247             Matthew Malcomson  <matthew.malcomson@arm.com>
 248
 249         * arm-dis.c (struct cdeopcode32): New.
 250         (CDE_OPCODE): New macro.
 251         (cde_opcodes): New disassembly table.
 252         (regnames): New option to table.
 253         (cde_coprocs): New global variable.
 254         (print_insn_cde): New
 255         (print_insn_thumb32): Use print_insn_cde.
 256         (parse_arm_disassembler_options): Parse coprocN args.
 257
 258 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 259
 260         PR gas/25516
 261         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 262         with ISA64.
 263         * i386-opc.h (AMD64): Removed.
 264         (Intel64): Likewose.
 265         (AMD64): New.
 266         (INTEL64): Likewise.
 267         (INTEL64ONLY): Likewise.
 268         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 269         * i386-opc.tbl (Amd64): New.
 270         (Intel64): Likewise.
 271         (Intel64Only): Likewise.
 272         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 273         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 274         * i386-tbl.h: Regenerated.
 275
 276 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 277
 278         PR 25469
 279         * z80-dis.c: Add support for GBZ80 opcodes.
 280
 281 2020-02-04  Alan Modra  <amodra@gmail.com>
 282
 283         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 284
 285 2020-02-03  Alan Modra  <amodra@gmail.com>
 286
 287         * m32c-ibld.c: Regenerate.
 288
 289 2020-02-01  Alan Modra  <amodra@gmail.com>
 290
 291         * frv-ibld.c: Regenerate.
 292
 293 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 294
 295         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 296         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 297         (OP_E_memory): Replace xmm_mdq_mode case label by
 298         vex_scalar_w_dq_mode one.
 299         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 300
 301 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 304         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 305         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 306         (intel_operand_size): Drop vex_w_dq_mode case label.
 307
 308 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 309
 310         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 311         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 312
 313 2020-01-30  Alan Modra  <amodra@gmail.com>
 314
 315         * m32c-ibld.c: Regenerate.
 316
 317 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 318
 319         * bpf-opc.c: Regenerate.
 320
 321 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 324         (dis386): Use them to replace C2/C3 table entries.
 325         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 326         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 327         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 328         * i386-tbl.h: Re-generate.
 329
 330 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 333         forms.
 334         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 335         DefaultSize.
 336         * i386-tbl.h: Re-generate.
 337
 338 2020-01-30  Alan Modra  <amodra@gmail.com>
 339
 340         * tic4x-dis.c (tic4x_dp): Make unsigned.
 341
 342 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 343             Jan Beulich  <jbeulich@suse.com>
 344
 345         PR binutils/25445
 346         * i386-dis.c (MOVSXD_Fixup): New function.
 347         (movsxd_mode): New enum.
 348         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 349         (intel_operand_size): Handle movsxd_mode.
 350         (OP_E_register): Likewise.
 351         (OP_G): Likewise.
 352         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 353         register on movsxd.  Add movsxd with 16-bit destination register
 354         for AMD64 and Intel64 ISAs.
 355         * i386-tbl.h: Regenerated.
 356
 357 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 358
 359         PR 25403
 360         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 361         * aarch64-asm-2.c: Regenerate
 362         * aarch64-dis-2.c: Likewise.
 363         * aarch64-opc-2.c: Likewise.
 364
 365 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.tbl (sysret): Drop DefaultSize.
 368         * i386-tbl.h: Re-generate.
 369
 370 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 373         Dword.
 374         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 375         * i386-tbl.h: Re-generate.
 376
 377 2020-01-20  Nick Clifton  <nickc@redhat.com>
 378
 379         * po/de.po: Updated German translation.
 380         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 381         * po/uk.po: Updated Ukranian translation.
 382
 383 2020-01-20  Alan Modra  <amodra@gmail.com>
 384
 385         * hppa-dis.c (fput_const): Remove useless cast.
 386
 387 2020-01-20  Alan Modra  <amodra@gmail.com>
 388
 389         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 390
 391 2020-01-18  Nick Clifton  <nickc@redhat.com>
 392
 393         * configure: Regenerate.
 394         * po/opcodes.pot: Regenerate.
 395
 396 2020-01-18  Nick Clifton  <nickc@redhat.com>
 397
 398         Binutils 2.34 branch created.
 399
 400 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 401
 402         * opintl.h: Fix spelling error (seperate).
 403
 404 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 405
 406         * i386-opc.tbl: Add {vex} pseudo prefix.
 407         * i386-tbl.h: Regenerated.
 408
 409 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 410
 411         PR 25376
 412         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 413         (neon_opcodes): Likewise.
 414         (select_arm_features): Make sure we enable MVE bits when selecting
 415         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 416         any architecture.
 417
 418 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 419
 420         * i386-opc.tbl: Drop stale comment from XOP section.
 421
 422 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 423
 424         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 425         (extractps): Add VexWIG to SSE2AVX forms.
 426         * i386-tbl.h: Re-generate.
 427
 428 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 431         Size64 from and use VexW1 on SSE2AVX forms.
 432         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 433         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 434         * i386-tbl.h: Re-generate.
 435
 436 2020-01-15  Alan Modra  <amodra@gmail.com>
 437
 438         * tic4x-dis.c (tic4x_version): Make unsigned long.
 439         (optab, optab_special, registernames): New file scope vars.
 440         (tic4x_print_register): Set up registernames rather than
 441         malloc'd registertable.
 442         (tic4x_disassemble): Delete optable and optable_special.  Use
 443         optab and optab_special instead.  Throw away old optab,
 444         optab_special and registernames when info->mach changes.
 445
 446 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 447
 448         PR 25377
 449         * z80-dis.c (suffix): Use .db instruction to generate double
 450         prefix.
 451
 452 2020-01-14  Alan Modra  <amodra@gmail.com>
 453
 454         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 455         values to unsigned before shifting.
 456
 457 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 458
 459         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 460         flow instructions.
 461         (print_insn_thumb16, print_insn_thumb32): Likewise.
 462         (print_insn): Initialize the insn info.
 463         * i386-dis.c (print_insn): Initialize the insn info fields, and
 464         detect jumps.
 465
 466 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 467
 468         * arc-opc.c (C_NE): Make it required.
 469
 470 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 471
 472         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 473         reserved register name.
 474
 475 2020-01-13  Alan Modra  <amodra@gmail.com>
 476
 477         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 478         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 479
 480 2020-01-13  Alan Modra  <amodra@gmail.com>
 481
 482         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 483         result of wasm_read_leb128 in a uint64_t and check that bits
 484         are not lost when copying to other locals.  Use uint32_t for
 485         most locals.  Use PRId64 when printing int64_t.
 486
 487 2020-01-13  Alan Modra  <amodra@gmail.com>
 488
 489         * score-dis.c: Formatting.
 490         * score7-dis.c: Formatting.
 491
 492 2020-01-13  Alan Modra  <amodra@gmail.com>
 493
 494         * score-dis.c (print_insn_score48): Use unsigned variables for
 495         unsigned values.  Don't left shift negative values.
 496         (print_insn_score32): Likewise.
 497         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 498
 499 2020-01-13  Alan Modra  <amodra@gmail.com>
 500
 501         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 502
 503 2020-01-13  Alan Modra  <amodra@gmail.com>
 504
 505         * fr30-ibld.c: Regenerate.
 506
 507 2020-01-13  Alan Modra  <amodra@gmail.com>
 508
 509         * xgate-dis.c (print_insn): Don't left shift signed value.
 510         (ripBits): Formatting, use 1u.
 511
 512 2020-01-10  Alan Modra  <amodra@gmail.com>
 513
 514         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 515         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 516
 517 2020-01-10  Alan Modra  <amodra@gmail.com>
 518
 519         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 520         and XRREG value earlier to avoid a shift with negative exponent.
 521         * m10200-dis.c (disassemble): Similarly.
 522
 523 2020-01-09  Nick Clifton  <nickc@redhat.com>
 524
 525         PR 25224
 526         * z80-dis.c (ld_ii_ii): Use correct cast.
 527
 528 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 529
 530         PR 25224
 531         * z80-dis.c (ld_ii_ii): Use character constant when checking
 532         opcode byte value.
 533
 534 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 535
 536         * i386-dis.c (SEP_Fixup): New.
 537         (SEP): Define.
 538         (dis386_twobyte): Use it for sysenter/sysexit.
 539         (enum x86_64_isa): Change amd64 enumerator to value 1.
 540         (OP_J): Compare isa64 against intel64 instead of amd64.
 541         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 542         forms.
 543         * i386-tbl.h: Re-generate.
 544
 545 2020-01-08  Alan Modra  <amodra@gmail.com>
 546
 547         * z8k-dis.c: Include libiberty.h
 548         (instr_data_s): Make max_fetched unsigned.
 549         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 550         Don't exceed byte_info bounds.
 551         (output_instr): Make num_bytes unsigned.
 552         (unpack_instr): Likewise for nibl_count and loop.
 553         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 554         idx unsigned.
 555         * z8k-opc.h: Regenerate.
 556
 557 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 558
 559         * arc-tbl.h (llock): Use 'LLOCK' as class.
 560         (llockd): Likewise.
 561         (scond): Use 'SCOND' as class.
 562         (scondd): Likewise.
 563         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 564         (scondd): Likewise.
 565
 566 2020-01-06  Alan Modra  <amodra@gmail.com>
 567
 568         * m32c-ibld.c: Regenerate.
 569
 570 2020-01-06  Alan Modra  <amodra@gmail.com>
 571
 572         PR 25344
 573         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 574         Peek at next byte to prevent recursion on repeated prefix bytes.
 575         Ensure uninitialised "mybuf" is not accessed.
 576         (print_insn_z80): Don't zero n_fetch and n_used here,..
 577         (print_insn_z80_buf): ..do it here instead.
 578
 579 2020-01-04  Alan Modra  <amodra@gmail.com>
 580
 581         * m32r-ibld.c: Regenerate.
 582
 583 2020-01-04  Alan Modra  <amodra@gmail.com>
 584
 585         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 586
 587 2020-01-04  Alan Modra  <amodra@gmail.com>
 588
 589         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 590
 591 2020-01-04  Alan Modra  <amodra@gmail.com>
 592
 593         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 594
 595 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 596
 597         * aarch64-tbl.h (aarch64_opcode_table): Use
 598         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 599
 600 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 601
 602         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 603         forms of SUDOT and USDOT.
 604
 605 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 606
 607         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 608         uzip{1,2}.
 609         * opcodes/aarch64-dis-2.c: Re-generate.
 610
 611 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 612
 613         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 614         FMMLA encoding.
 615         * opcodes/aarch64-dis-2.c: Re-generate.
 616
 617 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 618
 619         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 620
 621 2020-01-01  Alan Modra  <amodra@gmail.com>
 622
 623         Update year range in copyright notice of all files.
 624
 625 For older changes see ChangeLog-2019
 626 \f
 627 Copyright (C) 2020 Free Software Foundation, Inc.
 628
 629 Copying and distribution of this file, with or without modification,
 630 are permitted in any medium without royalty provided the copyright
 631 notice and this notice are preserved.
 632
 633 Local Variables:
 634 mode: change-log
 635 left-margin: 8
 636 fill-column: 74
 637 version-control: never
 638 End: