opcodes/ChangeLog

   1 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * configure: Regenerated.
   4
   5 2018-06-01  Jan Beulich  <jbeulich@suse.com>
   6
   7         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
   8         * i386-tbl.h: Re-generate.
   9
  10 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  11
  12         * i386-opc.tbl (sldt, str): Add NoRex64.
  13         * i386-tbl.h: Re-generate.
  14
  15 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-opc.tbl (invpcid): Add Oword.
  18         * i386-tbl.h: Re-generate.
  19
  20 2018-06-01  Alan Modra  <amodra@gmail.com>
  21
  22         * sysdep.h (_bfd_error_handler): Don't declare.
  23         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
  24         * rl78-decode.opc: Likewise.
  25         * msp430-decode.c: Regenerate.
  26         * rl78-decode.c: Regenerate.
  27
  28 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
  29
  30         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
  31         * i386-init.h : Regenerated.
  32
  33 2018-05-25  Alan Modra  <amodra@gmail.com>
  34
  35         * Makefile.in: Regenerate.
  36         * po/POTFILES.in: Regenerate.
  37
  38 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
  39
  40         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
  41         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
  42         (insert_bab, extract_bab, insert_btab, extract_btab,
  43         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
  44         (BAT, BBA VBA RBS XB6S): Delete macros.
  45         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
  46         (BB, BD, RBX, XC6): Update for new macros.
  47         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
  48         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
  49         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
  50         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
  51
  52 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
  53
  54         * Makefile.am: Add support for s12z architecture.
  55         * configure.ac: Likewise.
  56         * disassemble.c: Likewise.
  57         * disassemble.h: Likewise.
  58         * Makefile.in: Regenerate.
  59         * configure: Regenerate.
  60         * s12z-dis.c: New file.
  61         * s12z.h: New file.
  62
  63 2018-05-18  Alan Modra  <amodra@gmail.com>
  64
  65         * nfp-dis.c: Don't #include libbfd.h.
  66         (init_nfp3200_priv): Use bfd_get_section_contents.
  67         (nit_nfp6000_mecsr_sec): Likewise.
  68
  69 2018-05-17  Nick Clifton  <nickc@redhat.com>
  70
  71         * po/zh_CN.po: Updated simplified Chinese translation.
  72
  73 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
  74
  75         PR binutils/23109
  76         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
  77         * aarch64-dis-2.c: Regenerate.
  78
  79 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
  80
  81         PR binutils/21446
  82         * aarch64-asm.c (opintl.h): Include.
  83         (aarch64_ins_sysreg): Enforce read/write constraints.
  84         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
  85         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
  86         (F_REG_READ, F_REG_WRITE): New.
  87         * aarch64-opc.c (aarch64_print_operand): Generate notes for
  88         AARCH64_OPND_SYSREG.
  89         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
  90         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
  91         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
  92         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
  93         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
  94         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
  95         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
  96         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
  97         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
  98         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
  99         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 100         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 101         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 102         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 103         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 104         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 105         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 106
 107 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 108
 109         PR binutils/21446
 110         * aarch64-dis.c (no_notes: New.
 111         (parse_aarch64_dis_option): Support notes.
 112         (aarch64_decode_insn, print_operands): Likewise.
 113         (print_aarch64_disassembler_options): Document notes.
 114         * aarch64-opc.c (aarch64_print_operand): Support notes.
 115
 116 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 117
 118         PR binutils/21446
 119         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 120         and take error struct.
 121         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 122         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 123         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 124         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 125         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 126         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 127         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 128         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 129         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 130         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 131         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 132         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 133         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 134         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 135         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 136         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 137         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 138         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 139         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 140         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 141         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 142         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 143         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 144         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 145         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 146         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 147         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 148         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 149         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 150         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 151         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 152         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 153         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 154         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 155         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 156         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 157         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 158         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 159         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 160         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 161         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 162         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 163         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 164         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 165         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 166         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 167         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 168         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 169         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 170         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 171         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 172         (determine_disassembling_preference, aarch64_decode_insn,
 173         print_insn_aarch64_word, print_insn_data): Take errors struct.
 174         (print_insn_aarch64): Use errors.
 175         * aarch64-asm-2.c: Regenerate.
 176         * aarch64-dis-2.c: Regenerate.
 177         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 178         boolean in aarch64_insert_operan.
 179         (print_operand_extractor): Likewise.
 180         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 181
 182 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 183
 184         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 185
 186 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 187
 188         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 189
 190 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 191
 192         * cr16-opc.c (cr16_instruction): Comment typo fix.
 193         * hppa-dis.c (print_insn_hppa): Likewise.
 194
 195 2018-05-08  Jim Wilson  <jimw@sifive.com>
 196
 197         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 198         (match_c_slli64, match_srxi_as_c_srxi): New.
 199         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 200         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 201         <c.slli, c.srli, c.srai>: Use match_s_slli.
 202         <c.slli64, c.srli64, c.srai64>: New.
 203
 204 2018-05-08  Alan Modra  <amodra@gmail.com>
 205
 206         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 207         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 208         partition opcode space for index lookup.
 209
 210 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 211
 212         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 213         <insn_length>: ...with this.  Update usage.
 214         Remove duplicate call to *info->memory_error_func.
 215
 216 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 217             H.J. Lu  <hongjiu.lu@intel.com>
 218
 219         * i386-dis.c (Gva): New.
 220         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 221         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 222         (prefix_table): New instructions (see prefix above).
 223         (mod_table): New instructions (see prefix above).
 224         (OP_G): Handle va_mode.
 225         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 226         CPU_MOVDIR64B_FLAGS.
 227         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 228         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 229         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 230         * i386-opc.tbl: Add movidir{i,64b}.
 231         * i386-init.h: Regenerated.
 232         * i386-tbl.h: Likewise.
 233
 234 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 237         AddrPrefixOpReg.
 238         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 239         (AddrPrefixOpReg): This.
 240         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 241         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 242
 243 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 244
 245         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 246         (vle_num_opcodes): Likewise.
 247         (spe2_num_opcodes): Likewise.
 248         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 249         initialization loop.
 250         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 251         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 252         only once.
 253
 254 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 255
 256         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 257
 258 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 259
 260         Makefile.am: Added nfp-dis.c.
 261         configure.ac: Added bfd_nfp_arch.
 262         disassemble.h: Added print_insn_nfp prototype.
 263         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 264         nfp-dis.c: New, for NFP support.
 265         po/POTFILES.in: Added nfp-dis.c to the list.
 266         Makefile.in: Regenerate.
 267         configure: Regenerate.
 268
 269 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 272         templates into their base ones.
 273         * i386-tlb.h: Re-generate.
 274
 275 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 276
 277         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 278         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 279         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 280         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 281         * i386-init.h: Re-generate.
 282
 283 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 284
 285         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 286         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 287         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 288         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 289         comment.
 290         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 291         and CpuRegMask.
 292         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 293         CpuRegMask: Delete.
 294         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 295         cpuregzmm, and cpuregmask.
 296         * i386-init.h: Re-generate.
 297         * i386-tbl.h: Re-generate.
 298
 299 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 300
 301         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 302         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 303         * i386-init.h: Re-generate.
 304
 305 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-gen.c (VexImmExt): Delete.
 308         * i386-opc.h (VexImmExt, veximmext): Delete.
 309         * i386-opc.tbl: Drop all VexImmExt uses.
 310         * i386-tlb.h: Re-generate.
 311
 312 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 315         register-only forms.
 316         * i386-tlb.h: Re-generate.
 317
 318 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 319
 320         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 321
 322 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 323
 324         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 325         PREFIX_0F1C.
 326         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 327         (cpu_flags): Add CpuCLDEMOTE.
 328         * i386-init.h: Regenerate.
 329         * i386-opc.h (enum): Add CpuCLDEMOTE,
 330         (i386_cpu_flags): Add cpucldemote.
 331         * i386-opc.tbl: Add cldemote.
 332         * i386-tbl.h: Regenerate.
 333
 334 2018-04-16  Alan Modra  <amodra@gmail.com>
 335
 336         * Makefile.am: Remove sh5 and sh64 support.
 337         * configure.ac: Likewise.
 338         * disassemble.c: Likewise.
 339         * disassemble.h: Likewise.
 340         * sh-dis.c: Likewise.
 341         * sh64-dis.c: Delete.
 342         * sh64-opc.c: Delete.
 343         * sh64-opc.h: Delete.
 344         * Makefile.in: Regenerate.
 345         * configure: Regenerate.
 346         * po/POTFILES.in: Regenerate.
 347
 348 2018-04-16  Alan Modra  <amodra@gmail.com>
 349
 350         * Makefile.am: Remove w65 support.
 351         * configure.ac: Likewise.
 352         * disassemble.c: Likewise.
 353         * disassemble.h: Likewise.
 354         * w65-dis.c: Delete.
 355         * w65-opc.h: Delete.
 356         * Makefile.in: Regenerate.
 357         * configure: Regenerate.
 358         * po/POTFILES.in: Regenerate.
 359
 360 2018-04-16  Alan Modra  <amodra@gmail.com>
 361
 362         * configure.ac: Remove we32k support.
 363         * configure: Regenerate.
 364
 365 2018-04-16  Alan Modra  <amodra@gmail.com>
 366
 367         * Makefile.am: Remove m88k support.
 368         * configure.ac: Likewise.
 369         * disassemble.c: Likewise.
 370         * disassemble.h: Likewise.
 371         * m88k-dis.c: Delete.
 372         * Makefile.in: Regenerate.
 373         * configure: Regenerate.
 374         * po/POTFILES.in: Regenerate.
 375
 376 2018-04-16  Alan Modra  <amodra@gmail.com>
 377
 378         * Makefile.am: Remove i370 support.
 379         * configure.ac: Likewise.
 380         * disassemble.c: Likewise.
 381         * disassemble.h: Likewise.
 382         * i370-dis.c: Delete.
 383         * i370-opc.c: Delete.
 384         * Makefile.in: Regenerate.
 385         * configure: Regenerate.
 386         * po/POTFILES.in: Regenerate.
 387
 388 2018-04-16  Alan Modra  <amodra@gmail.com>
 389
 390         * Makefile.am: Remove h8500 support.
 391         * configure.ac: Likewise.
 392         * disassemble.c: Likewise.
 393         * disassemble.h: Likewise.
 394         * h8500-dis.c: Delete.
 395         * h8500-opc.h: Delete.
 396         * Makefile.in: Regenerate.
 397         * configure: Regenerate.
 398         * po/POTFILES.in: Regenerate.
 399
 400 2018-04-16  Alan Modra  <amodra@gmail.com>
 401
 402         * configure.ac: Remove tahoe support.
 403         * configure: Regenerate.
 404
 405 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 406
 407         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 408         umwait.
 409         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 410         64-bit mode.
 411         * i386-tbl.h: Regenerated.
 412
 413 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 414
 415         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 416         PREFIX_MOD_1_0FAE_REG_6.
 417         (va_mode): New.
 418         (OP_E_register): Use va_mode.
 419         * i386-dis-evex.h (prefix_table):
 420         New instructions (see prefixes above).
 421         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 422         (cpu_flags): Likewise.
 423         * i386-opc.h (enum): Likewise.
 424         (i386_cpu_flags): Likewise.
 425         * i386-opc.tbl: Add umonitor, umwait, tpause.
 426         * i386-init.h: Regenerate.
 427         * i386-tbl.h: Likewise.
 428
 429 2018-04-11  Alan Modra  <amodra@gmail.com>
 430
 431         * opcodes/i860-dis.c: Delete.
 432         * opcodes/i960-dis.c: Delete.
 433         * Makefile.am: Remove i860 and i960 support.
 434         * configure.ac: Likewise.
 435         * disassemble.c: Likewise.
 436         * disassemble.h: Likewise.
 437         * Makefile.in: Regenerate.
 438         * configure: Regenerate.
 439         * po/POTFILES.in: Regenerate.
 440
 441 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         PR binutils/23025
 444         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 445         to 0.
 446         (print_insn): Clear vex instead of vex.evex.
 447
 448 2018-04-04  Nick Clifton  <nickc@redhat.com>
 449
 450         * po/es.po: Updated Spanish translation.
 451
 452 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-gen.c (opcode_modifiers): Delete VecESize.
 455         * i386-opc.h (VecESize): Delete.
 456         (struct i386_opcode_modifier): Delete vecesize.
 457         * i386-opc.tbl: Drop VecESize.
 458         * i386-tlb.h: Re-generate.
 459
 460 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 463         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 464         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 465         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 466         * i386-tlb.h: Re-generate.
 467
 468 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 471         Fold AVX512 forms
 472         * i386-tlb.h: Re-generate.
 473
 474 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 477         (vex_len_table): Drop Y for vcvt*2si.
 478         (putop): Replace plain 'Y' handling by abort().
 479
 480 2018-03-28  Nick Clifton  <nickc@redhat.com>
 481
 482         PR 22988
 483         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 484         instructions with only a base address register.
 485         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 486         handle AARHC64_OPND_SVE_ADDR_R.
 487         (aarch64_print_operand): Likewise.
 488         * aarch64-asm-2.c: Regenerate.
 489         * aarch64_dis-2.c: Regenerate.
 490         * aarch64-opc-2.c: Regenerate.
 491
 492 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 493
 494         * i386-opc.tbl: Drop VecESize from register only insn forms and
 495         memory forms not allowing broadcast.
 496         * i386-tlb.h: Re-generate.
 497
 498 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 501         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 502         sha256*): Drop Disp<N>.
 503
 504 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-dis.c (EbndS, bnd_swap_mode): New.
 507         (prefix_table): Use EbndS.
 508         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 509         * i386-opc.tbl (bndmov): Move misplaced Load.
 510         * i386-tlb.h: Re-generate.
 511
 512 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 515         templates allowing memory operands and folded ones for register
 516         only flavors.
 517         * i386-tlb.h: Re-generate.
 518
 519 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 522         256-bit templates. Drop redundant leftover Disp<N>.
 523         * i386-tlb.h: Re-generate.
 524
 525 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 526
 527         * riscv-opc.c (riscv_insn_types): New.
 528
 529 2018-03-13  Nick Clifton  <nickc@redhat.com>
 530
 531         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 532
 533 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 534
 535         * i386-opc.tbl: Add Optimize to clr.
 536         * i386-tbl.h: Regenerated.
 537
 538 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 539
 540         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 541         * i386-opc.h (OldGcc): Removed.
 542         (i386_opcode_modifier): Remove oldgcc.
 543         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 544         instructions for old (<= 2.8.1) versions of gcc.
 545         * i386-tbl.h: Regenerated.
 546
 547 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 548
 549         * i386-opc.h (EVEXDYN): New.
 550         * i386-opc.tbl: Fold various AVX512VL templates.
 551         * i386-tlb.h: Re-generate.
 552
 553 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 554
 555         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 556         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 557         vpexpandd, vpexpandq): Fold AFX512VF templates.
 558         * i386-tlb.h: Re-generate.
 559
 560 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 561
 562         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 563         Fold 128- and 256-bit VEX-encoded templates.
 564         * i386-tlb.h: Re-generate.
 565
 566 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 569         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 570         vpexpandd, vpexpandq): Fold AVX512F templates.
 571         * i386-tlb.h: Re-generate.
 572
 573 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 576         64-bit templates. Drop Disp<N>.
 577         * i386-tlb.h: Re-generate.
 578
 579 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 582         and 256-bit templates.
 583         * i386-tlb.h: Re-generate.
 584
 585 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 588         * i386-tlb.h: Re-generate.
 589
 590 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 591
 592         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 593         Drop NoAVX.
 594         * i386-tlb.h: Re-generate.
 595
 596 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 599         * i386-tlb.h: Re-generate.
 600
 601 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 602
 603         * i386-gen.c (opcode_modifiers): Delete FloatD.
 604         * i386-opc.h (FloatD): Delete.
 605         (struct i386_opcode_modifier): Delete floatd.
 606         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 607         FloatD by D.
 608         * i386-tlb.h: Re-generate.
 609
 610 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 611
 612         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 613
 614 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 617         * i386-tlb.h: Re-generate.
 618
 619 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 620
 621         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 622         forms.
 623         * i386-tlb.h: Re-generate.
 624
 625 2018-03-07  Alan Modra  <amodra@gmail.com>
 626
 627         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 628         bfd_arch_rs6000.
 629         * disassemble.h (print_insn_rs6000): Delete.
 630         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 631         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 632         (print_insn_rs6000): Delete.
 633
 634 2018-03-03  Alan Modra  <amodra@gmail.com>
 635
 636         * sysdep.h (opcodes_error_handler): Define.
 637         (_bfd_error_handler): Declare.
 638         * Makefile.am: Remove stray #.
 639         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 640         EDIT" comment.
 641         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 642         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 643         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 644         opcodes_error_handler to print errors.  Standardize error messages.
 645         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 646         and include opintl.h.
 647         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 648         * i386-gen.c: Standardize error messages.
 649         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 650         * Makefile.in: Regenerate.
 651         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 652         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 653         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 654         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 655         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 656         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 657         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 658         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 659         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 660         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 661         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 662         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 663         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 664
 665 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 666
 667         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 668         vpsub[bwdq] instructions.
 669         * i386-tbl.h: Regenerated.
 670
 671 2018-03-01  Alan Modra  <amodra@gmail.com>
 672
 673         * configure.ac (ALL_LINGUAS): Sort.
 674         * configure: Regenerate.
 675
 676 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 677
 678         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 679         macro by assignements.
 680
 681 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         PR gas/22871
 684         * i386-gen.c (opcode_modifiers): Add Optimize.
 685         * i386-opc.h (Optimize): New enum.
 686         (i386_opcode_modifier): Add optimize.
 687         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 688         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 689         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 690         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 691         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 692         vpxord and vpxorq.
 693         * i386-tbl.h: Regenerated.
 694
 695 2018-02-26  Alan Modra  <amodra@gmail.com>
 696
 697         * crx-dis.c (getregliststring): Allocate a large enough buffer
 698         to silence false positive gcc8 warning.
 699
 700 2018-02-22  Shea Levy <shea@shealevy.com>
 701
 702         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 703
 704 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 705
 706         * i386-opc.tbl: Add {rex},
 707         * i386-tbl.h: Regenerated.
 708
 709 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 710
 711         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 712         (mips16_opcodes): Replace `M' with `m' for "restore".
 713
 714 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 715
 716         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 717
 718 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 719
 720         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 721         variable to `function_index'.
 722
 723 2018-02-13  Nick Clifton  <nickc@redhat.com>
 724
 725         PR 22823
 726         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 727         about truncation of printing.
 728
 729 2018-02-12  Henry Wong <henry@stuffedcow.net>
 730
 731         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 732
 733 2018-02-05  Nick Clifton  <nickc@redhat.com>
 734
 735         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 736
 737 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 738
 739         * i386-dis.c (enum): Add pconfig.
 740         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 741         (cpu_flags): Add CpuPCONFIG.
 742         * i386-opc.h (enum): Add CpuPCONFIG.
 743         (i386_cpu_flags): Add cpupconfig.
 744         * i386-opc.tbl: Add PCONFIG instruction.
 745         * i386-init.h: Regenerate.
 746         * i386-tbl.h: Likewise.
 747
 748 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 749
 750         * i386-dis.c (enum): Add PREFIX_0F09.
 751         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 752         (cpu_flags): Add CpuWBNOINVD.
 753         * i386-opc.h (enum): Add CpuWBNOINVD.
 754         (i386_cpu_flags): Add cpuwbnoinvd.
 755         * i386-opc.tbl: Add WBNOINVD instruction.
 756         * i386-init.h: Regenerate.
 757         * i386-tbl.h: Likewise.
 758
 759 2018-01-17  Jim Wilson  <jimw@sifive.com>
 760
 761         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 762
 763 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 764
 765         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 766         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 767         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 768         (cpu_flags): Add CpuIBT, CpuSHSTK.
 769         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 770         (i386_cpu_flags): Add cpuibt, cpushstk.
 771         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 772         * i386-init.h: Regenerate.
 773         * i386-tbl.h: Likewise.
 774
 775 2018-01-16  Nick Clifton  <nickc@redhat.com>
 776
 777         * po/pt_BR.po: Updated Brazilian Portugese translation.
 778         * po/de.po: Updated German translation.
 779
 780 2018-01-15  Jim Wilson  <jimw@sifive.com>
 781
 782         * riscv-opc.c (match_c_nop): New.
 783         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 784
 785 2018-01-15  Nick Clifton  <nickc@redhat.com>
 786
 787         * po/uk.po: Updated Ukranian translation.
 788
 789 2018-01-13  Nick Clifton  <nickc@redhat.com>
 790
 791         * po/opcodes.pot: Regenerated.
 792
 793 2018-01-13  Nick Clifton  <nickc@redhat.com>
 794
 795         * configure: Regenerate.
 796
 797 2018-01-13  Nick Clifton  <nickc@redhat.com>
 798
 799         2.30 branch created.
 800
 801 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 802
 803         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 804         * i386-tbl.h: Regenerate.
 805
 806 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 807
 808         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 809         * i386-tbl.h: Re-generate.
 810
 811 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 812
 813         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 814         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 815         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 816         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 817         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 818         Disp8MemShift of AVX512VL forms.
 819         * i386-tbl.h: Re-generate.
 820
 821 2018-01-09  Jim Wilson  <jimw@sifive.com>
 822
 823         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 824         then the hi_addr value is zero.
 825
 826 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 827
 828         * arm-dis.c (arm_opcodes): Add csdb.
 829         (thumb32_opcodes): Add csdb.
 830
 831 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 832
 833         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 834         * aarch64-asm-2.c: Regenerate.
 835         * aarch64-dis-2.c: Regenerate.
 836         * aarch64-opc-2.c: Regenerate.
 837
 838 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 839
 840         PR gas/22681
 841         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 842         Remove AVX512 vmovd with 64-bit operands.
 843         * i386-tbl.h: Regenerated.
 844
 845 2018-01-05  Jim Wilson  <jimw@sifive.com>
 846
 847         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 848         jalr.
 849
 850 2018-01-03  Alan Modra  <amodra@gmail.com>
 851
 852         Update year range in copyright notice of all files.
 853
 854 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 857         and OPERAND_TYPE_REGZMM entries.
 858
 859 For older changes see ChangeLog-2017
 860 \f
 861 Copyright (C) 2018 Free Software Foundation, Inc.
 862
 863 Copying and distribution of this file, with or without modification,
 864 are permitted in any medium without royalty provided the copyright
 865 notice and this notice are preserved.
 866
 867 Local Variables:
 868 mode: change-log
 869 left-margin: 8
 870 fill-column: 74
 871 version-control: never
 872 End: