opcodes/ChangeLog

   1 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
   2
   3         PR binutils/21446
   4         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
   5         and take error struct.
   6         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
   7         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
   8         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
   9         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
  10         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
  11         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
  12         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
  13         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
  14         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
  15         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
  16         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
  17         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
  18         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
  19         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
  20         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
  21         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
  22         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
  23         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
  24         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
  25         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
  26         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
  27         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
  28         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
  29         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
  30         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
  31         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
  32         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
  33         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
  34         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
  35         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
  36         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
  37         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
  38         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
  39         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
  40         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
  41         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
  42         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
  43         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
  44         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
  45         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
  46         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
  47         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
  48         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
  49         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
  50         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
  51         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
  52         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
  53         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
  54         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
  55         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
  56         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
  57         (determine_disassembling_preference, aarch64_decode_insn,
  58         print_insn_aarch64_word, print_insn_data): Take errors struct.
  59         (print_insn_aarch64): Use errors.
  60         * aarch64-asm-2.c: Regenerate.
  61         * aarch64-dis-2.c: Regenerate.
  62         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
  63         boolean in aarch64_insert_operan.
  64         (print_operand_extractor): Likewise.
  65         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
  66
  67 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
  68
  69         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
  70
  71 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
  72
  73         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
  74
  75 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
  76
  77         * cr16-opc.c (cr16_instruction): Comment typo fix.
  78         * hppa-dis.c (print_insn_hppa): Likewise.
  79
  80 2018-05-08  Jim Wilson  <jimw@sifive.com>
  81
  82         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
  83         (match_c_slli64, match_srxi_as_c_srxi): New.
  84         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
  85         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
  86         <c.slli, c.srli, c.srai>: Use match_s_slli.
  87         <c.slli64, c.srli64, c.srai64>: New.
  88
  89 2018-05-08  Alan Modra  <amodra@gmail.com>
  90
  91         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
  92         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
  93         partition opcode space for index lookup.
  94
  95 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
  96
  97         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
  98         <insn_length>: ...with this.  Update usage.
  99         Remove duplicate call to *info->memory_error_func.
 100
 101 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 102             H.J. Lu  <hongjiu.lu@intel.com>
 103
 104         * i386-dis.c (Gva): New.
 105         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 106         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 107         (prefix_table): New instructions (see prefix above).
 108         (mod_table): New instructions (see prefix above).
 109         (OP_G): Handle va_mode.
 110         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 111         CPU_MOVDIR64B_FLAGS.
 112         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 113         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 114         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 115         * i386-opc.tbl: Add movidir{i,64b}.
 116         * i386-init.h: Regenerated.
 117         * i386-tbl.h: Likewise.
 118
 119 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 122         AddrPrefixOpReg.
 123         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 124         (AddrPrefixOpReg): This.
 125         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 126         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 127
 128 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 129
 130         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 131         (vle_num_opcodes): Likewise.
 132         (spe2_num_opcodes): Likewise.
 133         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 134         initialization loop.
 135         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 136         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 137         only once.
 138
 139 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 140
 141         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 142
 143 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 144
 145         Makefile.am: Added nfp-dis.c.
 146         configure.ac: Added bfd_nfp_arch.
 147         disassemble.h: Added print_insn_nfp prototype.
 148         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 149         nfp-dis.c: New, for NFP support.
 150         po/POTFILES.in: Added nfp-dis.c to the list.
 151         Makefile.in: Regenerate.
 152         configure: Regenerate.
 153
 154 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 157         templates into their base ones.
 158         * i386-tlb.h: Re-generate.
 159
 160 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 161
 162         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 163         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 164         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 165         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 166         * i386-init.h: Re-generate.
 167
 168 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 171         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 172         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 173         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 174         comment.
 175         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 176         and CpuRegMask.
 177         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 178         CpuRegMask: Delete.
 179         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 180         cpuregzmm, and cpuregmask.
 181         * i386-init.h: Re-generate.
 182         * i386-tbl.h: Re-generate.
 183
 184 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 187         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 188         * i386-init.h: Re-generate.
 189
 190 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-gen.c (VexImmExt): Delete.
 193         * i386-opc.h (VexImmExt, veximmext): Delete.
 194         * i386-opc.tbl: Drop all VexImmExt uses.
 195         * i386-tlb.h: Re-generate.
 196
 197 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 200         register-only forms.
 201         * i386-tlb.h: Re-generate.
 202
 203 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 204
 205         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 206
 207 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 208
 209         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 210         PREFIX_0F1C.
 211         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 212         (cpu_flags): Add CpuCLDEMOTE.
 213         * i386-init.h: Regenerate.
 214         * i386-opc.h (enum): Add CpuCLDEMOTE,
 215         (i386_cpu_flags): Add cpucldemote.
 216         * i386-opc.tbl: Add cldemote.
 217         * i386-tbl.h: Regenerate.
 218
 219 2018-04-16  Alan Modra  <amodra@gmail.com>
 220
 221         * Makefile.am: Remove sh5 and sh64 support.
 222         * configure.ac: Likewise.
 223         * disassemble.c: Likewise.
 224         * disassemble.h: Likewise.
 225         * sh-dis.c: Likewise.
 226         * sh64-dis.c: Delete.
 227         * sh64-opc.c: Delete.
 228         * sh64-opc.h: Delete.
 229         * Makefile.in: Regenerate.
 230         * configure: Regenerate.
 231         * po/POTFILES.in: Regenerate.
 232
 233 2018-04-16  Alan Modra  <amodra@gmail.com>
 234
 235         * Makefile.am: Remove w65 support.
 236         * configure.ac: Likewise.
 237         * disassemble.c: Likewise.
 238         * disassemble.h: Likewise.
 239         * w65-dis.c: Delete.
 240         * w65-opc.h: Delete.
 241         * Makefile.in: Regenerate.
 242         * configure: Regenerate.
 243         * po/POTFILES.in: Regenerate.
 244
 245 2018-04-16  Alan Modra  <amodra@gmail.com>
 246
 247         * configure.ac: Remove we32k support.
 248         * configure: Regenerate.
 249
 250 2018-04-16  Alan Modra  <amodra@gmail.com>
 251
 252         * Makefile.am: Remove m88k support.
 253         * configure.ac: Likewise.
 254         * disassemble.c: Likewise.
 255         * disassemble.h: Likewise.
 256         * m88k-dis.c: Delete.
 257         * Makefile.in: Regenerate.
 258         * configure: Regenerate.
 259         * po/POTFILES.in: Regenerate.
 260
 261 2018-04-16  Alan Modra  <amodra@gmail.com>
 262
 263         * Makefile.am: Remove i370 support.
 264         * configure.ac: Likewise.
 265         * disassemble.c: Likewise.
 266         * disassemble.h: Likewise.
 267         * i370-dis.c: Delete.
 268         * i370-opc.c: Delete.
 269         * Makefile.in: Regenerate.
 270         * configure: Regenerate.
 271         * po/POTFILES.in: Regenerate.
 272
 273 2018-04-16  Alan Modra  <amodra@gmail.com>
 274
 275         * Makefile.am: Remove h8500 support.
 276         * configure.ac: Likewise.
 277         * disassemble.c: Likewise.
 278         * disassemble.h: Likewise.
 279         * h8500-dis.c: Delete.
 280         * h8500-opc.h: Delete.
 281         * Makefile.in: Regenerate.
 282         * configure: Regenerate.
 283         * po/POTFILES.in: Regenerate.
 284
 285 2018-04-16  Alan Modra  <amodra@gmail.com>
 286
 287         * configure.ac: Remove tahoe support.
 288         * configure: Regenerate.
 289
 290 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 291
 292         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 293         umwait.
 294         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 295         64-bit mode.
 296         * i386-tbl.h: Regenerated.
 297
 298 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 299
 300         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 301         PREFIX_MOD_1_0FAE_REG_6.
 302         (va_mode): New.
 303         (OP_E_register): Use va_mode.
 304         * i386-dis-evex.h (prefix_table):
 305         New instructions (see prefixes above).
 306         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 307         (cpu_flags): Likewise.
 308         * i386-opc.h (enum): Likewise.
 309         (i386_cpu_flags): Likewise.
 310         * i386-opc.tbl: Add umonitor, umwait, tpause.
 311         * i386-init.h: Regenerate.
 312         * i386-tbl.h: Likewise.
 313
 314 2018-04-11  Alan Modra  <amodra@gmail.com>
 315
 316         * opcodes/i860-dis.c: Delete.
 317         * opcodes/i960-dis.c: Delete.
 318         * Makefile.am: Remove i860 and i960 support.
 319         * configure.ac: Likewise.
 320         * disassemble.c: Likewise.
 321         * disassemble.h: Likewise.
 322         * Makefile.in: Regenerate.
 323         * configure: Regenerate.
 324         * po/POTFILES.in: Regenerate.
 325
 326 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         PR binutils/23025
 329         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 330         to 0.
 331         (print_insn): Clear vex instead of vex.evex.
 332
 333 2018-04-04  Nick Clifton  <nickc@redhat.com>
 334
 335         * po/es.po: Updated Spanish translation.
 336
 337 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-gen.c (opcode_modifiers): Delete VecESize.
 340         * i386-opc.h (VecESize): Delete.
 341         (struct i386_opcode_modifier): Delete vecesize.
 342         * i386-opc.tbl: Drop VecESize.
 343         * i386-tlb.h: Re-generate.
 344
 345 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 348         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 349         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 350         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 351         * i386-tlb.h: Re-generate.
 352
 353 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 354
 355         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 356         Fold AVX512 forms
 357         * i386-tlb.h: Re-generate.
 358
 359 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 360
 361         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 362         (vex_len_table): Drop Y for vcvt*2si.
 363         (putop): Replace plain 'Y' handling by abort().
 364
 365 2018-03-28  Nick Clifton  <nickc@redhat.com>
 366
 367         PR 22988
 368         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 369         instructions with only a base address register.
 370         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 371         handle AARHC64_OPND_SVE_ADDR_R.
 372         (aarch64_print_operand): Likewise.
 373         * aarch64-asm-2.c: Regenerate.
 374         * aarch64_dis-2.c: Regenerate.
 375         * aarch64-opc-2.c: Regenerate.
 376
 377 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 378
 379         * i386-opc.tbl: Drop VecESize from register only insn forms and
 380         memory forms not allowing broadcast.
 381         * i386-tlb.h: Re-generate.
 382
 383 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 384
 385         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 386         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 387         sha256*): Drop Disp<N>.
 388
 389 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 390
 391         * i386-dis.c (EbndS, bnd_swap_mode): New.
 392         (prefix_table): Use EbndS.
 393         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 394         * i386-opc.tbl (bndmov): Move misplaced Load.
 395         * i386-tlb.h: Re-generate.
 396
 397 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 398
 399         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 400         templates allowing memory operands and folded ones for register
 401         only flavors.
 402         * i386-tlb.h: Re-generate.
 403
 404 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 405
 406         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 407         256-bit templates. Drop redundant leftover Disp<N>.
 408         * i386-tlb.h: Re-generate.
 409
 410 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 411
 412         * riscv-opc.c (riscv_insn_types): New.
 413
 414 2018-03-13  Nick Clifton  <nickc@redhat.com>
 415
 416         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 417
 418 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 419
 420         * i386-opc.tbl: Add Optimize to clr.
 421         * i386-tbl.h: Regenerated.
 422
 423 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 424
 425         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 426         * i386-opc.h (OldGcc): Removed.
 427         (i386_opcode_modifier): Remove oldgcc.
 428         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 429         instructions for old (<= 2.8.1) versions of gcc.
 430         * i386-tbl.h: Regenerated.
 431
 432 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 433
 434         * i386-opc.h (EVEXDYN): New.
 435         * i386-opc.tbl: Fold various AVX512VL templates.
 436         * i386-tlb.h: Re-generate.
 437
 438 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 439
 440         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 441         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 442         vpexpandd, vpexpandq): Fold AFX512VF templates.
 443         * i386-tlb.h: Re-generate.
 444
 445 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 448         Fold 128- and 256-bit VEX-encoded templates.
 449         * i386-tlb.h: Re-generate.
 450
 451 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 452
 453         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 454         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 455         vpexpandd, vpexpandq): Fold AVX512F templates.
 456         * i386-tlb.h: Re-generate.
 457
 458 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 461         64-bit templates. Drop Disp<N>.
 462         * i386-tlb.h: Re-generate.
 463
 464 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 467         and 256-bit templates.
 468         * i386-tlb.h: Re-generate.
 469
 470 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 473         * i386-tlb.h: Re-generate.
 474
 475 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 476
 477         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 478         Drop NoAVX.
 479         * i386-tlb.h: Re-generate.
 480
 481 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 484         * i386-tlb.h: Re-generate.
 485
 486 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-gen.c (opcode_modifiers): Delete FloatD.
 489         * i386-opc.h (FloatD): Delete.
 490         (struct i386_opcode_modifier): Delete floatd.
 491         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 492         FloatD by D.
 493         * i386-tlb.h: Re-generate.
 494
 495 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 498
 499 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 500
 501         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 502         * i386-tlb.h: Re-generate.
 503
 504 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 507         forms.
 508         * i386-tlb.h: Re-generate.
 509
 510 2018-03-07  Alan Modra  <amodra@gmail.com>
 511
 512         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 513         bfd_arch_rs6000.
 514         * disassemble.h (print_insn_rs6000): Delete.
 515         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 516         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 517         (print_insn_rs6000): Delete.
 518
 519 2018-03-03  Alan Modra  <amodra@gmail.com>
 520
 521         * sysdep.h (opcodes_error_handler): Define.
 522         (_bfd_error_handler): Declare.
 523         * Makefile.am: Remove stray #.
 524         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 525         EDIT" comment.
 526         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 527         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 528         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 529         opcodes_error_handler to print errors.  Standardize error messages.
 530         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 531         and include opintl.h.
 532         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 533         * i386-gen.c: Standardize error messages.
 534         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 535         * Makefile.in: Regenerate.
 536         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 537         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 538         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 539         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 540         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 541         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 542         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 543         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 544         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 545         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 546         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 547         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 548         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 549
 550 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 551
 552         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 553         vpsub[bwdq] instructions.
 554         * i386-tbl.h: Regenerated.
 555
 556 2018-03-01  Alan Modra  <amodra@gmail.com>
 557
 558         * configure.ac (ALL_LINGUAS): Sort.
 559         * configure: Regenerate.
 560
 561 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 562
 563         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 564         macro by assignements.
 565
 566 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 567
 568         PR gas/22871
 569         * i386-gen.c (opcode_modifiers): Add Optimize.
 570         * i386-opc.h (Optimize): New enum.
 571         (i386_opcode_modifier): Add optimize.
 572         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 573         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 574         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 575         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 576         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 577         vpxord and vpxorq.
 578         * i386-tbl.h: Regenerated.
 579
 580 2018-02-26  Alan Modra  <amodra@gmail.com>
 581
 582         * crx-dis.c (getregliststring): Allocate a large enough buffer
 583         to silence false positive gcc8 warning.
 584
 585 2018-02-22  Shea Levy <shea@shealevy.com>
 586
 587         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 588
 589 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 590
 591         * i386-opc.tbl: Add {rex},
 592         * i386-tbl.h: Regenerated.
 593
 594 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 595
 596         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 597         (mips16_opcodes): Replace `M' with `m' for "restore".
 598
 599 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 600
 601         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 602
 603 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 604
 605         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 606         variable to `function_index'.
 607
 608 2018-02-13  Nick Clifton  <nickc@redhat.com>
 609
 610         PR 22823
 611         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 612         about truncation of printing.
 613
 614 2018-02-12  Henry Wong <henry@stuffedcow.net>
 615
 616         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 617
 618 2018-02-05  Nick Clifton  <nickc@redhat.com>
 619
 620         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 621
 622 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 623
 624         * i386-dis.c (enum): Add pconfig.
 625         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 626         (cpu_flags): Add CpuPCONFIG.
 627         * i386-opc.h (enum): Add CpuPCONFIG.
 628         (i386_cpu_flags): Add cpupconfig.
 629         * i386-opc.tbl: Add PCONFIG instruction.
 630         * i386-init.h: Regenerate.
 631         * i386-tbl.h: Likewise.
 632
 633 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 634
 635         * i386-dis.c (enum): Add PREFIX_0F09.
 636         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 637         (cpu_flags): Add CpuWBNOINVD.
 638         * i386-opc.h (enum): Add CpuWBNOINVD.
 639         (i386_cpu_flags): Add cpuwbnoinvd.
 640         * i386-opc.tbl: Add WBNOINVD instruction.
 641         * i386-init.h: Regenerate.
 642         * i386-tbl.h: Likewise.
 643
 644 2018-01-17  Jim Wilson  <jimw@sifive.com>
 645
 646         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 647
 648 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 649
 650         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 651         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 652         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 653         (cpu_flags): Add CpuIBT, CpuSHSTK.
 654         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 655         (i386_cpu_flags): Add cpuibt, cpushstk.
 656         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 657         * i386-init.h: Regenerate.
 658         * i386-tbl.h: Likewise.
 659
 660 2018-01-16  Nick Clifton  <nickc@redhat.com>
 661
 662         * po/pt_BR.po: Updated Brazilian Portugese translation.
 663         * po/de.po: Updated German translation.
 664
 665 2018-01-15  Jim Wilson  <jimw@sifive.com>
 666
 667         * riscv-opc.c (match_c_nop): New.
 668         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 669
 670 2018-01-15  Nick Clifton  <nickc@redhat.com>
 671
 672         * po/uk.po: Updated Ukranian translation.
 673
 674 2018-01-13  Nick Clifton  <nickc@redhat.com>
 675
 676         * po/opcodes.pot: Regenerated.
 677
 678 2018-01-13  Nick Clifton  <nickc@redhat.com>
 679
 680         * configure: Regenerate.
 681
 682 2018-01-13  Nick Clifton  <nickc@redhat.com>
 683
 684         2.30 branch created.
 685
 686 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 687
 688         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 689         * i386-tbl.h: Regenerate.
 690
 691 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 694         * i386-tbl.h: Re-generate.
 695
 696 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 699         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 700         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 701         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 702         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 703         Disp8MemShift of AVX512VL forms.
 704         * i386-tbl.h: Re-generate.
 705
 706 2018-01-09  Jim Wilson  <jimw@sifive.com>
 707
 708         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 709         then the hi_addr value is zero.
 710
 711 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 712
 713         * arm-dis.c (arm_opcodes): Add csdb.
 714         (thumb32_opcodes): Add csdb.
 715
 716 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 717
 718         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 719         * aarch64-asm-2.c: Regenerate.
 720         * aarch64-dis-2.c: Regenerate.
 721         * aarch64-opc-2.c: Regenerate.
 722
 723 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 724
 725         PR gas/22681
 726         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 727         Remove AVX512 vmovd with 64-bit operands.
 728         * i386-tbl.h: Regenerated.
 729
 730 2018-01-05  Jim Wilson  <jimw@sifive.com>
 731
 732         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 733         jalr.
 734
 735 2018-01-03  Alan Modra  <amodra@gmail.com>
 736
 737         Update year range in copyright notice of all files.
 738
 739 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 742         and OPERAND_TYPE_REGZMM entries.
 743
 744 For older changes see ChangeLog-2017
 745 \f
 746 Copyright (C) 2018 Free Software Foundation, Inc.
 747
 748 Copying and distribution of this file, with or without modification,
 749 are permitted in any medium without royalty provided the copyright
 750 notice and this notice are preserved.
 751
 752 Local Variables:
 753 mode: change-log
 754 left-margin: 8
 755 fill-column: 74
 756 version-control: never
 757 End: