opcodes/ChangeLog

   1 2020-03-22  Alan Modra  <amodra@gmail.com>
   2
   3         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
   4         successflly read from section.
   5
   6 2020-03-22  Alan Modra  <amodra@gmail.com>
   7
   8         * arc-dis.c (find_format): Use ISO C string concatenation rather
   9         than line continuation within a string.  Don't access needs_limm
  10         before testing opcode != NULL.
  11
  12 2020-03-22  Alan Modra  <amodra@gmail.com>
  13
  14         * ns32k-dis.c (print_insn_arg): Update comment.
  15         (print_insn_ns32k): Reduce size of index_offset array, and
  16         initialize, passing -1 to print_insn_arg for args that are not
  17         an index.  Don't exit arg loop early.  Abort on bad arg number.
  18
  19 2020-03-22  Alan Modra  <amodra@gmail.com>
  20
  21         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
  22         * s12z-opc.c: Formatting.
  23         (operands_f): Return an int.
  24         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
  25         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
  26         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
  27         (exg_sex_discrim): Likewise.
  28         (create_immediate_operand, create_bitfield_operand),
  29         (create_register_operand_with_size, create_register_all_operand),
  30         (create_register_all16_operand, create_simple_memory_operand),
  31         (create_memory_operand, create_memory_auto_operand): Don't
  32         segfault on malloc failure.
  33         (z_ext24_decode): Return an int status, negative on fail, zero
  34         on success.
  35         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
  36         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
  37         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
  38         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
  39         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
  40         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
  41         (loop_primitive_decode, shift_decode, psh_pul_decode),
  42         (bit_field_decode): Similarly.
  43         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
  44         to return value, update callers.
  45         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
  46         Don't segfault on NULL operand.
  47         (decode_operation): Return OP_INVALID on first fail.
  48         (decode_s12z): Check all reads, returning -1 on fail.
  49
  50 2020-03-20  Alan Modra  <amodra@gmail.com>
  51
  52         * metag-dis.c (print_insn_metag): Don't ignore status from
  53         read_memory_func.
  54
  55 2020-03-20  Alan Modra  <amodra@gmail.com>
  56
  57         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
  58         Initialize parts of buffer not written when handling a possible
  59         2-byte insn at end of section.  Don't attempt decoding of such
  60         an insn by the 4-byte machinery.
  61
  62 2020-03-20  Alan Modra  <amodra@gmail.com>
  63
  64         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
  65         partially filled buffer.  Prevent lookup of 4-byte insns when
  66         only VLE 2-byte insns are possible due to section size.  Print
  67         ".word" rather than ".long" for 2-byte leftovers.
  68
  69 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
  70
  71         PR 25641
  72         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
  73
  74 2020-03-13  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-dis.c (X86_64_0D): Rename to ...
  77         (X86_64_0E): ... this.
  78
  79 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  80
  81         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
  82         * Makefile.in: Regenerated.
  83
  84 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
  87         3-operand pseudos.
  88         * i386-tbl.h: Re-generate.
  89
  90 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
  93         vprot*, vpsha*, and vpshl*.
  94         * i386-tbl.h: Re-generate.
  95
  96 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
  99         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 100         * i386-tbl.h: Re-generate.
 101
 102 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 105         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 106         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 107         * i386-tbl.h: Re-generate.
 108
 109 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 110
 111         * i386-gen.c (struct template_arg, struct template_instance,
 112         struct template_param, struct template, templates,
 113         parse_template, expand_templates): New.
 114         (process_i386_opcodes): Various local variables moved to
 115         expand_templates. Call parse_template and expand_templates.
 116         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 117         * i386-tbl.h: Re-generate.
 118
 119 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 120
 121         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 122         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 123         register and memory source templates. Replace VexW= by VexW*
 124         where applicable.
 125         * i386-tbl.h: Re-generate.
 126
 127 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 130         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 131         * i386-tbl.h: Re-generate.
 132
 133 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 136         * i386-tbl.h: Re-generate.
 137
 138 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 141         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 142         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 143         VexW0 on SSE2AVX variants.
 144         (vmovq): Drop NoRex64 from XMM/XMM variants.
 145         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 146         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 147         applicable use VexW0.
 148         * i386-tbl.h: Re-generate.
 149
 150 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 153         * i386-opc.h (Rex64): Delete.
 154         (struct i386_opcode_modifier): Remove rex64 field.
 155         * i386-opc.tbl (crc32): Drop Rex64.
 156         Replace Rex64 with Size64 everywhere else.
 157         * i386-tbl.h: Re-generate.
 158
 159 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-dis.c (OP_E_memory): Exclude recording of used address
 162         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 163         addressed memory operands for MPX insns.
 164
 165 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 166
 167         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 168         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 169         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 170         (ptwrite): Split into non-64-bit and 64-bit forms.
 171         * i386-tbl.h: Re-generate.
 172
 173 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 174
 175         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 176         template.
 177         * i386-tbl.h: Re-generate.
 178
 179 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 182         (prefix_table): Move vmmcall here. Add vmgexit.
 183         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 184         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 185         (cpu_flags): Add CpuSEV_ES entry.
 186         * i386-opc.h (CpuSEV_ES): New.
 187         (union i386_cpu_flags): Add cpusev_es field.
 188         * i386-opc.tbl (vmgexit): New.
 189         * i386-init.h, i386-tbl.h: Re-generate.
 190
 191 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 194         with MnemonicSize.
 195         * i386-opc.h (IGNORESIZE): New.
 196         (DEFAULTSIZE): Likewise.
 197         (IgnoreSize): Removed.
 198         (DefaultSize): Likewise.
 199         (MnemonicSize): New.
 200         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 201         mnemonicsize.
 202         * i386-opc.tbl (IgnoreSize): New.
 203         (DefaultSize): Likewise.
 204         * i386-tbl.h: Regenerated.
 205
 206 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 207
 208         PR 25627
 209         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 210         instructions.
 211
 212 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         PR gas/25622
 215         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 216         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 217         * i386-tbl.h: Regenerated.
 218
 219 2020-02-26  Alan Modra  <amodra@gmail.com>
 220
 221         * aarch64-asm.c: Indent labels correctly.
 222         * aarch64-dis.c: Likewise.
 223         * aarch64-gen.c: Likewise.
 224         * aarch64-opc.c: Likewise.
 225         * alpha-dis.c: Likewise.
 226         * i386-dis.c: Likewise.
 227         * nds32-asm.c: Likewise.
 228         * nfp-dis.c: Likewise.
 229         * visium-dis.c: Likewise.
 230
 231 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 232
 233         * arc-regs.h (int_vector_base): Make it available for all ARC
 234         CPUs.
 235
 236 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 237
 238         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 239         changed.
 240
 241 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 242
 243         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 244         c.mv/c.li if rs1 is zero.
 245
 246 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 247
 248         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 249         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 250         CPU_POPCNT_FLAGS.
 251         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 252         * i386-opc.h (CpuABM): Removed.
 253         (CpuPOPCNT): New.
 254         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 255         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 256         popcnt.  Remove CpuABM from lzcnt.
 257         * i386-init.h: Regenerated.
 258         * i386-tbl.h: Likewise.
 259
 260 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 263         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 264         VexW1 instead of open-coding them.
 265         * i386-tbl.h: Re-generate.
 266
 267 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-opc.tbl (AddrPrefixOpReg): Define.
 270         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 271         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 272         templates. Drop NoRex64.
 273         * i386-tbl.h: Re-generate.
 274
 275 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 276
 277         PR gas/6518
 278         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 279         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 280         into Intel syntax instance (with Unpsecified) and AT&T one
 281         (without).
 282         (vcvtneps2bf16): Likewise, along with folding the two so far
 283         separate ones.
 284         * i386-tbl.h: Re-generate.
 285
 286 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 287
 288         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 289         CPU_ANY_SSE4A_FLAGS.
 290
 291 2020-02-17  Alan Modra  <amodra@gmail.com>
 292
 293         * i386-gen.c (cpu_flag_init): Correct last change.
 294
 295 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 296
 297         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 298         CPU_ANY_SSE4_FLAGS.
 299
 300 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 303         (movzx): Likewise.
 304
 305 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 306
 307         PR gas/25438
 308         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 309         destination for Cpu64-only variant.
 310         (movzx): Fold patterns.
 311         * i386-tbl.h: Re-generate.
 312
 313 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 316         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 317         CPU_ANY_SSE4_FLAGS entry.
 318         * i386-init.h: Re-generate.
 319
 320 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 323         with Unspecified, making the present one AT&T syntax only.
 324         * i386-tbl.h: Re-generate.
 325
 326 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 329         * i386-tbl.h: Re-generate.
 330
 331 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 332
 333         PR gas/24546
 334         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 335         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 336         Amd64 and Intel64 templates.
 337         (call, jmp): Likewise for far indirect variants. Dro
 338         Unspecified.
 339         * i386-tbl.h: Re-generate.
 340
 341 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 344         * i386-opc.h (ShortForm): Delete.
 345         (struct i386_opcode_modifier): Remove shortform field.
 346         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 347         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 348         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 349         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 350         Drop ShortForm.
 351         * i386-tbl.h: Re-generate.
 352
 353 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 354
 355         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 356         fucompi): Drop ShortForm from operand-less templates.
 357         * i386-tbl.h: Re-generate.
 358
 359 2020-02-11  Alan Modra  <amodra@gmail.com>
 360
 361         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 362         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 363         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 364         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 365         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 366
 367 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 368
 369         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 370         (cde_opcodes): Add VCX* instructions.
 371
 372 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 373             Matthew Malcomson  <matthew.malcomson@arm.com>
 374
 375         * arm-dis.c (struct cdeopcode32): New.
 376         (CDE_OPCODE): New macro.
 377         (cde_opcodes): New disassembly table.
 378         (regnames): New option to table.
 379         (cde_coprocs): New global variable.
 380         (print_insn_cde): New
 381         (print_insn_thumb32): Use print_insn_cde.
 382         (parse_arm_disassembler_options): Parse coprocN args.
 383
 384 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 385
 386         PR gas/25516
 387         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 388         with ISA64.
 389         * i386-opc.h (AMD64): Removed.
 390         (Intel64): Likewose.
 391         (AMD64): New.
 392         (INTEL64): Likewise.
 393         (INTEL64ONLY): Likewise.
 394         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 395         * i386-opc.tbl (Amd64): New.
 396         (Intel64): Likewise.
 397         (Intel64Only): Likewise.
 398         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 399         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 400         * i386-tbl.h: Regenerated.
 401
 402 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 403
 404         PR 25469
 405         * z80-dis.c: Add support for GBZ80 opcodes.
 406
 407 2020-02-04  Alan Modra  <amodra@gmail.com>
 408
 409         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 410
 411 2020-02-03  Alan Modra  <amodra@gmail.com>
 412
 413         * m32c-ibld.c: Regenerate.
 414
 415 2020-02-01  Alan Modra  <amodra@gmail.com>
 416
 417         * frv-ibld.c: Regenerate.
 418
 419 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 422         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 423         (OP_E_memory): Replace xmm_mdq_mode case label by
 424         vex_scalar_w_dq_mode one.
 425         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 426
 427 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 428
 429         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 430         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 431         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 432         (intel_operand_size): Drop vex_w_dq_mode case label.
 433
 434 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 435
 436         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 437         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 438
 439 2020-01-30  Alan Modra  <amodra@gmail.com>
 440
 441         * m32c-ibld.c: Regenerate.
 442
 443 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 444
 445         * bpf-opc.c: Regenerate.
 446
 447 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 450         (dis386): Use them to replace C2/C3 table entries.
 451         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 452         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 453         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 454         * i386-tbl.h: Re-generate.
 455
 456 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 457
 458         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 459         forms.
 460         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 461         DefaultSize.
 462         * i386-tbl.h: Re-generate.
 463
 464 2020-01-30  Alan Modra  <amodra@gmail.com>
 465
 466         * tic4x-dis.c (tic4x_dp): Make unsigned.
 467
 468 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 469             Jan Beulich  <jbeulich@suse.com>
 470
 471         PR binutils/25445
 472         * i386-dis.c (MOVSXD_Fixup): New function.
 473         (movsxd_mode): New enum.
 474         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 475         (intel_operand_size): Handle movsxd_mode.
 476         (OP_E_register): Likewise.
 477         (OP_G): Likewise.
 478         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 479         register on movsxd.  Add movsxd with 16-bit destination register
 480         for AMD64 and Intel64 ISAs.
 481         * i386-tbl.h: Regenerated.
 482
 483 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 484
 485         PR 25403
 486         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 487         * aarch64-asm-2.c: Regenerate
 488         * aarch64-dis-2.c: Likewise.
 489         * aarch64-opc-2.c: Likewise.
 490
 491 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl (sysret): Drop DefaultSize.
 494         * i386-tbl.h: Re-generate.
 495
 496 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 497
 498         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 499         Dword.
 500         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 501         * i386-tbl.h: Re-generate.
 502
 503 2020-01-20  Nick Clifton  <nickc@redhat.com>
 504
 505         * po/de.po: Updated German translation.
 506         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 507         * po/uk.po: Updated Ukranian translation.
 508
 509 2020-01-20  Alan Modra  <amodra@gmail.com>
 510
 511         * hppa-dis.c (fput_const): Remove useless cast.
 512
 513 2020-01-20  Alan Modra  <amodra@gmail.com>
 514
 515         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 516
 517 2020-01-18  Nick Clifton  <nickc@redhat.com>
 518
 519         * configure: Regenerate.
 520         * po/opcodes.pot: Regenerate.
 521
 522 2020-01-18  Nick Clifton  <nickc@redhat.com>
 523
 524         Binutils 2.34 branch created.
 525
 526 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 527
 528         * opintl.h: Fix spelling error (seperate).
 529
 530 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 531
 532         * i386-opc.tbl: Add {vex} pseudo prefix.
 533         * i386-tbl.h: Regenerated.
 534
 535 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 536
 537         PR 25376
 538         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 539         (neon_opcodes): Likewise.
 540         (select_arm_features): Make sure we enable MVE bits when selecting
 541         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 542         any architecture.
 543
 544 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 545
 546         * i386-opc.tbl: Drop stale comment from XOP section.
 547
 548 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 549
 550         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 551         (extractps): Add VexWIG to SSE2AVX forms.
 552         * i386-tbl.h: Re-generate.
 553
 554 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 555
 556         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 557         Size64 from and use VexW1 on SSE2AVX forms.
 558         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 559         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 560         * i386-tbl.h: Re-generate.
 561
 562 2020-01-15  Alan Modra  <amodra@gmail.com>
 563
 564         * tic4x-dis.c (tic4x_version): Make unsigned long.
 565         (optab, optab_special, registernames): New file scope vars.
 566         (tic4x_print_register): Set up registernames rather than
 567         malloc'd registertable.
 568         (tic4x_disassemble): Delete optable and optable_special.  Use
 569         optab and optab_special instead.  Throw away old optab,
 570         optab_special and registernames when info->mach changes.
 571
 572 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 573
 574         PR 25377
 575         * z80-dis.c (suffix): Use .db instruction to generate double
 576         prefix.
 577
 578 2020-01-14  Alan Modra  <amodra@gmail.com>
 579
 580         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 581         values to unsigned before shifting.
 582
 583 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 584
 585         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 586         flow instructions.
 587         (print_insn_thumb16, print_insn_thumb32): Likewise.
 588         (print_insn): Initialize the insn info.
 589         * i386-dis.c (print_insn): Initialize the insn info fields, and
 590         detect jumps.
 591
 592 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 593
 594         * arc-opc.c (C_NE): Make it required.
 595
 596 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 597
 598         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 599         reserved register name.
 600
 601 2020-01-13  Alan Modra  <amodra@gmail.com>
 602
 603         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 604         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 605
 606 2020-01-13  Alan Modra  <amodra@gmail.com>
 607
 608         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 609         result of wasm_read_leb128 in a uint64_t and check that bits
 610         are not lost when copying to other locals.  Use uint32_t for
 611         most locals.  Use PRId64 when printing int64_t.
 612
 613 2020-01-13  Alan Modra  <amodra@gmail.com>
 614
 615         * score-dis.c: Formatting.
 616         * score7-dis.c: Formatting.
 617
 618 2020-01-13  Alan Modra  <amodra@gmail.com>
 619
 620         * score-dis.c (print_insn_score48): Use unsigned variables for
 621         unsigned values.  Don't left shift negative values.
 622         (print_insn_score32): Likewise.
 623         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 624
 625 2020-01-13  Alan Modra  <amodra@gmail.com>
 626
 627         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 628
 629 2020-01-13  Alan Modra  <amodra@gmail.com>
 630
 631         * fr30-ibld.c: Regenerate.
 632
 633 2020-01-13  Alan Modra  <amodra@gmail.com>
 634
 635         * xgate-dis.c (print_insn): Don't left shift signed value.
 636         (ripBits): Formatting, use 1u.
 637
 638 2020-01-10  Alan Modra  <amodra@gmail.com>
 639
 640         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 641         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 642
 643 2020-01-10  Alan Modra  <amodra@gmail.com>
 644
 645         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 646         and XRREG value earlier to avoid a shift with negative exponent.
 647         * m10200-dis.c (disassemble): Similarly.
 648
 649 2020-01-09  Nick Clifton  <nickc@redhat.com>
 650
 651         PR 25224
 652         * z80-dis.c (ld_ii_ii): Use correct cast.
 653
 654 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 655
 656         PR 25224
 657         * z80-dis.c (ld_ii_ii): Use character constant when checking
 658         opcode byte value.
 659
 660 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-dis.c (SEP_Fixup): New.
 663         (SEP): Define.
 664         (dis386_twobyte): Use it for sysenter/sysexit.
 665         (enum x86_64_isa): Change amd64 enumerator to value 1.
 666         (OP_J): Compare isa64 against intel64 instead of amd64.
 667         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 668         forms.
 669         * i386-tbl.h: Re-generate.
 670
 671 2020-01-08  Alan Modra  <amodra@gmail.com>
 672
 673         * z8k-dis.c: Include libiberty.h
 674         (instr_data_s): Make max_fetched unsigned.
 675         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 676         Don't exceed byte_info bounds.
 677         (output_instr): Make num_bytes unsigned.
 678         (unpack_instr): Likewise for nibl_count and loop.
 679         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 680         idx unsigned.
 681         * z8k-opc.h: Regenerate.
 682
 683 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 684
 685         * arc-tbl.h (llock): Use 'LLOCK' as class.
 686         (llockd): Likewise.
 687         (scond): Use 'SCOND' as class.
 688         (scondd): Likewise.
 689         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 690         (scondd): Likewise.
 691
 692 2020-01-06  Alan Modra  <amodra@gmail.com>
 693
 694         * m32c-ibld.c: Regenerate.
 695
 696 2020-01-06  Alan Modra  <amodra@gmail.com>
 697
 698         PR 25344
 699         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 700         Peek at next byte to prevent recursion on repeated prefix bytes.
 701         Ensure uninitialised "mybuf" is not accessed.
 702         (print_insn_z80): Don't zero n_fetch and n_used here,..
 703         (print_insn_z80_buf): ..do it here instead.
 704
 705 2020-01-04  Alan Modra  <amodra@gmail.com>
 706
 707         * m32r-ibld.c: Regenerate.
 708
 709 2020-01-04  Alan Modra  <amodra@gmail.com>
 710
 711         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 712
 713 2020-01-04  Alan Modra  <amodra@gmail.com>
 714
 715         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 716
 717 2020-01-04  Alan Modra  <amodra@gmail.com>
 718
 719         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 720
 721 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 722
 723         * aarch64-tbl.h (aarch64_opcode_table): Use
 724         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 725
 726 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 727
 728         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 729         forms of SUDOT and USDOT.
 730
 731 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 732
 733         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 734         uzip{1,2}.
 735         * opcodes/aarch64-dis-2.c: Re-generate.
 736
 737 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 738
 739         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 740         FMMLA encoding.
 741         * opcodes/aarch64-dis-2.c: Re-generate.
 742
 743 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 744
 745         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 746
 747 2020-01-01  Alan Modra  <amodra@gmail.com>
 748
 749         Update year range in copyright notice of all files.
 750
 751 For older changes see ChangeLog-2019
 752 \f
 753 Copyright (C) 2020 Free Software Foundation, Inc.
 754
 755 Copying and distribution of this file, with or without modification,
 756 are permitted in any medium without royalty provided the copyright
 757 notice and this notice are preserved.
 758
 759 Local Variables:
 760 mode: change-log
 761 left-margin: 8
 762 fill-column: 74
 763 version-control: never
 764 End: