opcodes/ChangeLog

   1 2006-04-28  Thiemo Seufer  <ths@mips.com>
   2             David Ung  <davidu@mips.com>
   3             Nigel Stevens  <nigel@mips.com>
   4
   5         * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
   6         names.
   7
   8 2006-04-28  Thiemo Seufer  <ths@mips.com>
   9             Nigel Stevens  <nigel@mips.com>
  10             David Ung  <davidu@mips.com>
  11
  12         * mips-dis.c (print_insn_args): Add mips_opcode argument.
  13         (print_insn_mips):  Adjust print_insn_args call.
  14
  15 2006-04-28  Thiemo Seufer  <ths@mips.com>
  16             Nigel Stevens  <nigel@mips.com>
  17
  18         * mips-dis.c (print_insn_args): Print $fcc only for FP
  19         instructions, use $cc elsewise.
  20
  21 2006-04-28  Thiemo Seufer  <ths@mips.com>
  22             Nigel Stevens  <nigel@mips.com>
  23
  24         * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
  25         Map MIPS16 registers to O32 names.
  26         (print_mips16_insn_arg): Use mips16_reg_names.
  27
  28 2006-04-26  Julian Brown  <julian@codesourcery.com>
  29
  30         * arm-dis.c (print_insn_neon): Disassemble floating-point constant
  31         VMOV.
  32
  33 2006-04-26  Nathan Sidwell  <nathan@codesourcery.com>
  34             Julian Brown  <julian@codesourcery.com>
  35
  36         * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
  37         %<code>[zy] into %[zy]<code>.  Expand meaning of %<bitfield>['`?].
  38         Add unified load/store instruction names.
  39         (neon_opcode_table): New.
  40         (arm_opcodes): Expand meaning of %<bitfield>['`?].
  41         (arm_decode_bitfield): New.
  42         (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
  43         Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
  44         (print_insn_neon): New.
  45         (print_insn_arm): Adjust print_insn_coprocessor call. Call
  46         print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
  47         (print_insn_thumb32): Likewise.
  48
  49 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
  50
  51         * Makefile.am: Run "make dep-am".
  52         * Makefile.in: Regenerate.
  53
  54 2006-04-19  Alan Modra  <amodra@bigpond.net.au>
  55
  56         * avr-dis.c (avr_operand): Warning fix.
  57
  58         * configure: Regenerate.
  59
  60 2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
  61
  62         * po/POTFILES.in: Regenerated.
  63
  64 2006-04-12   Hochstein  <hochstein@algo.informatik.tu-darmstadt.de>
  65
  66         PR binutils/2454
  67         * avr-dis.c (avr_operand): Arrange for a comment to appear before
  68         the symolic form of an address, so that the output of objdump -d
  69         can be reassembled.
  70
  71 2006-04-10  DJ Delorie  <dj@redhat.com>
  72
  73         * m32c-asm.c: Regenerate.
  74
  75 2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
  76
  77         * Makefile.am: Add install-html target.
  78         * Makefile.in: Regenerate.
  79
  80 2006-04-06  Nick Clifton  <nickc@redhat.com>
  81
  82         * po/vi/po: Updated Vietnamese translation.
  83
  84 2006-03-31  Paul Koning  <ni1d@arrl.net>
  85
  86         * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
  87
  88 2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
  89
  90         * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
  91         logic to identify halfword shifts.
  92
  93 2006-03-16  Paul Brook  <paul@codesourcery.com>
  94
  95         * arm-dis.c (arm_opcodes): Rename swi to svc.
  96         (thumb_opcodes): Ditto.
  97
  98 2006-03-13  DJ Delorie  <dj@redhat.com>
  99
 100         * m32c-asm.c: Regenerate.
 101         * m32c-desc.c: Likewise.
 102         * m32c-desc.h: Likewise.
 103         * m32c-dis.c: Likewise.
 104         * m32c-ibld.c: Likewise.
 105         * m32c-opc.c: Likewise.
 106         * m32c-opc.h: Likewise.
 107
 108 2006-03-10  DJ Delorie  <dj@redhat.com>
 109
 110         * m32c-desc.c: Regenerate with mul.l, mulu.l.
 111         * m32c-opc.c: Likewise.
 112         * m32c-opc.h: Likewise.
 113
 114
 115 2006-03-09  Nick Clifton  <nickc@redhat.com>
 116
 117         * po/sv.po: Updated Swedish translation.
 118
 119 2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         PR binutils/2428
 122         * i386-dis.c (REP_Fixup): New function.
 123         (AL): Remove duplicate.
 124         (Xbr): New.
 125         (Xvr): Likewise.
 126         (Ybr): Likewise.
 127         (Yvr): Likewise.
 128         (indirDXr): Likewise.
 129         (ALr): Likewise.
 130         (eAXr): Likewise.
 131         (dis386): Updated entries of ins, outs, movs, lods and stos.
 132
 133 2006-03-05  Nick Clifton  <nickc@redhat.com>
 134
 135         * cgen-ibld.in (insert_normal): Cope with attempts to insert a
 136         signed 32-bit value into an unsigned 32-bit field when the host is
 137         a 64-bit machine.
 138         * fr30-ibld.c: Regenerate.
 139         * frv-ibld.c: Regenerate.
 140         * ip2k-ibld.c: Regenerate.
 141         * iq2000-asm.c: Regenerate.
 142         * iq2000-ibld.c: Regenerate.
 143         * m32c-ibld.c: Regenerate.
 144         * m32r-ibld.c: Regenerate.
 145         * openrisc-ibld.c: Regenerate.
 146         * xc16x-ibld.c: Regenerate.
 147         * xstormy16-ibld.c: Regenerate.
 148
 149 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
 150
 151         * xc16x-asm.c: Regenerate.
 152         * xc16x-dis.c: Regenerate.
 153
 154 2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 155
 156         * po/Make-in: Add html target.
 157
 158 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 159
 160         * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
 161         Intel Merom New Instructions.
 162         (THREE_BYTE_0): Likewise.
 163         (THREE_BYTE_1): Likewise.
 164         (three_byte_table): Likewise.
 165         (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
 166         THREE_BYTE_1 for entry 0x3a.
 167         (twobyte_has_modrm): Updated.
 168         (twobyte_uses_SSE_prefix): Likewise.
 169         (print_insn): Handle 3-byte opcodes used by Intel Merom New
 170         Instructions.
 171
 172 2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
 173
 174         * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
 175         (v9_hpriv_reg_names): New table.
 176         (print_insn_sparc): Allow values up to 16 for '?' and '!'.
 177         New cases '$' and '%' for read/write hyperprivileged register.
 178         * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
 179         window handling and rdhpr/wrhpr instructions.
 180
 181 2006-02-24  DJ Delorie  <dj@redhat.com>
 182
 183         * m32c-desc.c: Regenerate with linker relaxation attributes.
 184         * m32c-desc.h: Likewise.
 185         * m32c-dis.c: Likewise.
 186         * m32c-opc.c: Likewise.
 187
 188 2006-02-24  Paul Brook  <paul@codesourcery.com>
 189
 190         * arm-dis.c (arm_opcodes): Add V7 instructions.
 191         (thumb32_opcodes): Ditto.  Handle V7M MSR/MRS variants.
 192         (print_arm_address): New function.
 193         (print_insn_arm): Use it.  Add 'P' and 'U' cases.
 194         (psr_name): New function.
 195         (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
 196
 197 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 198
 199         * ia64-opc-i.c (bXc): New.
 200         (mXc): Likewise.
 201         (OpX2TaTbYaXcC): Likewise.
 202         (TF). Likewise.
 203         (TFCM). Likewise.
 204         (ia64_opcodes_i): Add instructions for tf.
 205
 206         * ia64-opc.h (IMMU5b): New.
 207
 208         * ia64-asmtab.c: Regenerated.
 209
 210 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         * ia64-gen.c: Update copyright years.
 213         * ia64-opc-b.c: Likewise.
 214
 215 2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         * ia64-gen.c (lookup_regindex): Handle ".vm".
 218         (print_dependency_table): Handle '\"'.
 219
 220         * ia64-ic.tbl: Updated from SDM 2.2.
 221         * ia64-raw.tbl: Likewise.
 222         * ia64-waw.tbl: Likewise.
 223         * ia64-asmtab.c: Regenerated.
 224
 225         * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
 226
 227 2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
 228             Anil Paranjape   <anilp1@kpitcummins.com>
 229             Shilin Shakti    <shilins@kpitcummins.com>
 230
 231         * xc16x-desc.h: New file
 232         * xc16x-desc.c: New file
 233         * xc16x-opc.h: New file
 234         * xc16x-opc.c: New file
 235         * xc16x-ibld.c: New file
 236         * xc16x-asm.c: New file
 237         * xc16x-dis.c: New file
 238         * Makefile.am: Entries for xc16x
 239         * Makefile.in: Regenerate
 240         * cofigure.in: Add xc16x target information.
 241         * configure: Regenerate.
 242         * disassemble.c: Add xc16x target information.
 243
 244 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
 247         moves.
 248
 249 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         * i386-dis.c ('Z'): Add a new macro.
 252         (dis386_twobyte): Use "movZ" for control register moves.
 253
 254 2006-02-10  Nick Clifton  <nickc@redhat.com>
 255
 256         * iq2000-asm.c: Regenerate.
 257
 258 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 259
 260         * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
 261
 262 2006-01-26  David Ung  <davidu@mips.com>
 263
 264         * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
 265         ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
 266         floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
 267         nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
 268         rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
 269
 270 2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
 271
 272         * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
 273         ld_d_r, pref_xd_cb): Use signed char to hold data to be
 274         disassembled.
 275         * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
 276         buffer overflows when disassembling instructions like
 277         ld (ix+123),0x23
 278         * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
 279         operand, if the offset is negative.
 280
 281 2006-01-17  Arnold Metselaar  <arnoldm@sourceware.org>
 282
 283         * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
 284         unsigned char to hold data to be disassembled.
 285
 286 2006-01-17  Andreas Schwab  <schwab@suse.de>
 287
 288         PR binutils/1486
 289         * disassemble.c (disassemble_init_for_target): Set
 290         disassembler_needs_relocs for bfd_arch_arm.
 291
 292 2006-01-16  Paul Brook  <paul@codesourcery.com>
 293
 294         * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
 295         f?add?, and f?sub? instructions.
 296
 297 2006-01-16  Nick Clifton  <nickc@redhat.com>
 298
 299         * po/zh_CN.po: New Chinese (simplified) translation.
 300         * configure.in (ALL_LINGUAS): Add "zh_CH".
 301         * configure: Regenerate.
 302
 303 2006-01-05  Paul Brook  <paul@codesourcery.com>
 304
 305         * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
 306
 307 2006-01-06  DJ Delorie  <dj@redhat.com>
 308
 309         * m32c-desc.c: Regenerate.
 310         * m32c-opc.c: Regenerate.
 311         * m32c-opc.h: Regenerate.
 312
 313 2006-01-03  DJ Delorie  <dj@redhat.com>
 314
 315         * cgen-ibld.in (extract_normal): Avoid memory range errors.
 316         * m32c-ibld.c: Regenerated.
 317
 318 For older changes see ChangeLog-2005
 319 \f
 320 Local Variables:
 321 mode: change-log
 322 left-margin: 8
 323 fill-column: 74
 324 version-control: never
 325 End: