1 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
4 * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
6 2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
9 * i386-dis.c (print_insn): Clear modrm if not needed.
10 (putop): Check need_modrm for modrm.mod != 3. Don't check
11 need_modrm for modrm.mod == 3.
13 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
15 * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
16 TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
17 TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
18 TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
19 TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
20 TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
21 TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
22 TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
23 WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
24 TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
25 TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
26 TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
27 TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
28 TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
30 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
32 * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
34 2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
36 * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
37 TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
39 2020-09-26 Alan Modra <amodra@gmail.com>
41 * csky-opc.h: Formatting.
42 (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
43 (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
45 (get_register_number): Likewise.
46 * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
48 2020-09-24 Lili Cui <lili.cui@intel.com>
51 * i386-dis.c (enum): Put MOD_VEX_0F38* together.
53 2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
55 * csky-dis.c (csky_output_operand): Enclose body of if in curly
58 2020-09-24 Lili Cui <lili.cui@intel.com>
60 * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
61 PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
62 X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
63 X86_64_0F01_REG_1_RM_7_P_2.
64 (prefix_table): Likewise.
65 (x86_64_table): Likewise.
67 * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
68 and CPU_ANY_TDX_FLAGS.
69 (cpu_flags): Add CpuTDX.
70 * i386-opc.h (enum): Add CpuTDX.
71 (i386_cpu_flags): Add cputdx.
72 * i386-opc.tbl: Add TDX insns.
73 * i386-init.h: Regenerate.
74 * i386-tbl.h: Likewise.
76 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
78 * csky-dis.c (using_abi): New.
79 (parse_csky_dis_options): New function.
80 (get_gr_name): New function.
81 (get_cr_name): New function.
82 (csky_output_operand): Use get_gr_name and get_cr_name to
83 disassemble and add handle of OPRND_TYPE_IMM5b_LS.
84 (print_insn_csky): Parse disassembler options.
85 * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
86 (GENARAL_REG_BANK): Define.
87 (REG_SUPPORT_ALL): Define.
88 (REG_SUPPORT_ALL): New.
90 (REG_SUPPORT_A): Define.
91 (REG_SUPPORT_B): Define.
92 (REG_SUPPORT_C): Define.
93 (REG_SUPPORT_D): Define.
94 (REG_SUPPORT_E): Define.
95 (csky_abiv1_general_regs): New.
96 (csky_abiv1_control_regs): New.
97 (csky_abiv2_general_regs): New.
98 (csky_abiv2_control_regs): New.
99 (get_register_name): New function.
100 (get_register_number): New function.
101 (csky_get_general_reg_name): New function.
102 (csky_get_general_regno): New function.
103 (csky_get_control_reg_name): New function.
104 (csky_get_control_regno): New function.
105 (csky_v2_opcodes): Prefer two oprerans format for bclri and
106 bseti, strengthen the operands legality check of addc, zext
109 2020-09-23 Lili Cui <lili.cui@intel.com>
111 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
112 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
113 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
114 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
115 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
116 (reg_table): New instructions (see prefixes above).
117 (prefix_table): Likewise.
118 (three_byte_table): Likewise.
119 (mod_table): Likewise
120 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
121 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
122 (cpu_flags): Likewise.
123 (operand_type_init): Likewise.
124 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
125 (i386_cpu_flags): Add cpukl and cpuwide_kl.
126 * i386-opc.tbl: Add KL and WIDE_KL insns.
127 * i386-init.h: Regenerate.
128 * i386-tbl.h: Likewise.
130 2020-09-21 Alan Modra <amodra@gmail.com>
132 * rx-dis.c (flag_names): Add missing comma.
133 (register_names, flag_names, double_register_names),
134 (double_register_high_names, double_register_low_names),
135 (double_control_register_names, double_condition_names): Remove
138 2020-09-18 David Faust <david.faust@oracle.com>
140 * bpf-desc.c: Regenerate.
141 * bpf-desc.h: Likewise.
142 * bpf-opc.c: Likewise.
143 * bpf-opc.h: Likewise.
145 2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
147 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
150 2020-09-16 Alan Modra <amodra@gmail.com>
152 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
154 2020-09-10 Nick Clifton <nickc@redhat.com>
156 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
157 for hidden, local, no-type symbols.
158 (disassemble_init_powerpc): Point the symbol_is_valid field in the
159 info structure at the new function.
161 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
163 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
164 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
167 2020-09-10 Nick Clifton <nickc@redhat.com>
169 * csky-dis.c (csky_output_operand): Coerce the immediate values to
170 long before printing.
172 2020-09-10 Alan Modra <amodra@gmail.com>
174 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
176 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
178 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
181 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
183 * csky-dis.c (csky_output_operand): Add handlers for
184 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
185 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
186 to support FPUV3 instructions.
187 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
188 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
189 OPRND_TYPE_DFLOAT_FMOVI.
190 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
191 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
192 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
193 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
194 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
195 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
196 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
197 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
198 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
199 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
200 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
201 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
202 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
203 (csky_v2_opcodes): Add FPUV3 instructions.
205 2020-09-08 Alex Coplan <alex.coplan@arm.com>
207 * aarch64-dis.c (print_operands): Pass CPU features to
208 aarch64_print_operand().
209 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
210 preferred disassembly of system registers.
211 (SR_RNG): Refactor to use new SR_FEAT2 macro.
217 (SR_EXPAND_ELx): New.
218 (SR_EXPAND_EL12): New.
219 (aarch64_sys_regs): Specify which registers are only on
220 A-profile, add R-profile system registers.
224 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
227 2020-09-08 Alex Coplan <alex.coplan@arm.com>
229 * aarch64-tbl.h (aarch64_feature_v8_r): New.
232 (aarch64_opcode_table): Add dfb.
233 * aarch64-opc-2.c: Regenerate.
234 * aarch64-asm-2.c: Regenerate.
235 * aarch64-dis-2.c: Regenerate.
237 2020-09-08 Alex Coplan <alex.coplan@arm.com>
239 * aarch64-dis.c (arch_variant): New.
240 (determine_disassembling_preference): Disassemble according to
242 (select_aarch64_variant): New.
243 (print_insn_aarch64): Set feature set.
245 2020-09-02 Alan Modra <amodra@gmail.com>
247 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
248 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
249 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
250 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
251 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
252 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
253 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
254 for value parameter and update code to suit.
255 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
256 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
258 2020-09-02 Alan Modra <amodra@gmail.com>
260 * i386-dis.c (OP_E_memory): Don't cast to signed type when
262 (get32, get32s): Use unsigned types in shift expressions.
264 2020-09-02 Alan Modra <amodra@gmail.com>
266 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
268 2020-09-02 Alan Modra <amodra@gmail.com>
270 * crx-dis.c: Whitespace.
271 (print_arg): Use unsigned type for longdisp and mask variables,
272 and for left shift constant.
274 2020-09-02 Alan Modra <amodra@gmail.com>
276 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
277 * bpf-ibld.c: Regenerate.
278 * epiphany-ibld.c: Regenerate.
279 * fr30-ibld.c: Regenerate.
280 * frv-ibld.c: Regenerate.
281 * ip2k-ibld.c: Regenerate.
282 * iq2000-ibld.c: Regenerate.
283 * lm32-ibld.c: Regenerate.
284 * m32c-ibld.c: Regenerate.
285 * m32r-ibld.c: Regenerate.
286 * mep-ibld.c: Regenerate.
287 * mt-ibld.c: Regenerate.
288 * or1k-ibld.c: Regenerate.
289 * xc16x-ibld.c: Regenerate.
290 * xstormy16-ibld.c: Regenerate.
292 2020-09-02 Alan Modra <amodra@gmail.com>
294 * bfin-dis.c (MASKBITS): Use SIGNBIT.
296 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
298 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
299 to CSKYV2_ISA_3E3R3 instruction set.
301 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
303 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
305 2020-09-01 Alan Modra <amodra@gmail.com>
307 * mep-ibld.c: Regenerate.
309 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
311 * csky-dis.c (csky_output_operand): Assign dis_info.value for
314 2020-08-30 Alan Modra <amodra@gmail.com>
316 * cr16-dis.c: Formatting.
317 (parameter): Delete struct typedef. Use dwordU instead
319 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
321 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
323 2020-08-29 Alan Modra <amodra@gmail.com>
326 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
327 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
329 2020-08-28 Alan Modra <amodra@gmail.com>
333 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
334 (extract_normal): Likewise.
335 (insert_normal): Likewise, and move past zero length test.
336 (put_insn_int_value): Handle mask for zero length, use 1UL.
337 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
338 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
339 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
340 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
342 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
344 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
345 (csky_dis_info): Add member isa.
346 (csky_find_inst_info): Skip instructions that do not belong to
348 (csky_get_disassembler): Get infomation from attribute section.
349 (print_insn_csky): Set defualt ISA flag.
350 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
351 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
352 isa_flag32'type to unsigned 64 bits.
354 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
356 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
358 2020-08-26 David Faust <david.faust@oracle.com>
360 * bpf-desc.c: Regenerate.
361 * bpf-desc.h: Likewise.
362 * bpf-opc.c: Likewise.
363 * bpf-opc.h: Likewise.
364 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
365 ISA when appropriate.
367 2020-08-25 Alan Modra <amodra@gmail.com>
370 * vax-dis.c (parse_disassembler_options): Always add at least one
371 to entry_addr_total_slots.
373 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
375 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
376 in other CPUs to speed up disassembling.
377 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
378 Change plsli.u16 to plsli.16, change sync's operand format.
380 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
382 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
384 2020-08-21 Nick Clifton <nickc@redhat.com>
386 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
389 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
391 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
393 2020-08-19 Alan Modra <amodra@gmail.com>
395 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
398 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
400 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
401 <xvcvbf16spn>: ...to this.
403 2020-08-12 Alex Coplan <alex.coplan@arm.com>
405 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
407 2020-08-12 Nick Clifton <nickc@redhat.com>
409 * po/sr.po: Updated Serbian translation.
411 2020-08-11 Alan Modra <amodra@gmail.com>
413 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
415 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
417 * aarch64-opc.c (aarch64_print_operand):
418 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
419 (aarch64_sys_reg_supported_p): Function removed.
420 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
421 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
424 2020-08-10 Alan Modra <amodra@gmail.com>
426 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
429 2020-08-10 Alan Modra <amodra@gmail.com>
431 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
432 Enable icbt for power5, miso for power8.
434 2020-08-10 Alan Modra <amodra@gmail.com>
436 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
437 mtvsrd, and similarly for mfvsrd.
439 2020-08-04 Christian Groessler <chris@groessler.org>
440 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
442 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
443 opcodes (special "out" to absolute address).
444 * z8k-opc.h: Regenerate.
446 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
449 * i386-opc.h (Prefix_Disp8): New.
450 (Prefix_Disp16): Likewise.
451 (Prefix_Disp32): Likewise.
452 (Prefix_Load): Likewise.
453 (Prefix_Store): Likewise.
454 (Prefix_VEX): Likewise.
455 (Prefix_VEX3): Likewise.
456 (Prefix_EVEX): Likewise.
457 (Prefix_REX): Likewise.
458 (Prefix_NoOptimize): Likewise.
459 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
460 * i386-tbl.h: Regenerated.
462 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
464 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
465 default case with abort() instead of printing an error message and
466 continuing, to avoid a maybe-uninitialized warning.
468 2020-07-24 Nick Clifton <nickc@redhat.com>
470 * po/de.po: Updated German translation.
472 2020-07-21 Jan Beulich <jbeulich@suse.com>
474 * i386-dis.c (OP_E_memory): Revert previous change.
476 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
479 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
480 without base nor index registers.
482 2020-07-15 Jan Beulich <jbeulich@suse.com>
484 * i386-dis.c (putop): Move 'V' and 'W' handling.
486 2020-07-15 Jan Beulich <jbeulich@suse.com>
488 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
489 construct for push/pop of register.
490 (putop): Honor cond when handling 'P'. Drop handling of plain
493 2020-07-15 Jan Beulich <jbeulich@suse.com>
495 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
496 description. Drop '&' description. Use P for push of immediate,
497 pushf/popf, enter, and leave. Use %LP for lret/retf.
498 (dis386_twobyte): Use P for push/pop of fs/gs.
499 (reg_table): Use P for push/pop. Use @ for near call/jmp.
500 (x86_64_table): Use P for far call/jmp.
501 (putop): Drop handling of 'U' and '&'. Move and adjust handling
502 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
504 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
505 and dqw_mode (unconditional).
507 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
510 * i386-dis.c (OP_E_memory): Without base nor index registers,
511 32-bit displacement to 64 bits.
513 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
515 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
516 faulty double register pair is detected.
518 2020-07-14 Jan Beulich <jbeulich@suse.com>
520 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
522 2020-07-14 Jan Beulich <jbeulich@suse.com>
524 * i386-dis.c (OP_R, Rm): Delete.
525 (MOD_0F24, MOD_0F26): Rename to ...
526 (X86_64_0F24, X86_64_0F26): ... respectively.
527 (dis386): Update 'L' and 'Z' comments.
528 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
530 (mod_table): Move opcode 0F24 and 0F26 entries ...
531 (x86_64_table): ... here.
532 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
535 2020-07-14 Jan Beulich <jbeulich@suse.com>
537 * i386-dis.c (Rd, Rdq, MaskR): Delete.
538 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
539 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
540 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
541 MOD_EVEX_0F387C): New enumerators.
542 (reg_table): Use Edq for rdssp.
543 (prefix_table): Use Edq for incssp.
544 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
545 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
546 ktest*, and kshift*. Use Edq / MaskE for kmov*.
547 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
548 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
549 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
550 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
551 0F3828_P_1 and 0F3838_P_1.
552 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
553 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
555 2020-07-14 Jan Beulich <jbeulich@suse.com>
557 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
558 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
559 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
560 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
561 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
562 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
563 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
564 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
565 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
566 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
567 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
568 (reg_table, prefix_table, three_byte_table, vex_table,
569 vex_len_table, mod_table, rm_table): Replace / remove respective
571 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
572 of PREFIX_DATA in used_prefixes.
574 2020-07-14 Jan Beulich <jbeulich@suse.com>
576 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
577 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
578 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
579 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
580 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
581 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
582 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
583 VEX_W_0F3A33_L_0): Delete.
584 (dis386): Adjust "BW" description.
585 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
586 0F3A31, 0F3A32, and 0F3A33.
587 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
589 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
592 2020-07-14 Jan Beulich <jbeulich@suse.com>
594 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
595 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
596 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
597 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
598 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
599 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
600 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
601 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
602 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
603 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
604 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
605 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
606 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
607 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
608 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
609 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
610 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
611 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
612 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
613 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
614 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
615 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
616 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
617 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
618 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
619 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
620 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
621 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
622 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
623 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
624 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
625 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
626 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
627 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
628 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
629 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
630 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
631 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
632 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
633 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
634 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
635 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
636 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
637 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
638 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
639 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
640 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
641 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
642 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
643 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
644 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
645 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
646 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
647 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
648 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
649 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
650 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
651 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
652 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
653 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
654 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
655 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
656 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
657 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
658 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
659 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
660 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
661 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
662 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
663 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
664 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
665 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
666 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
667 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
668 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
669 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
670 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
671 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
672 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
673 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
674 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
675 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
676 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
677 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
678 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
679 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
680 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
681 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
682 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
683 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
684 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
685 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
686 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
687 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
688 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
689 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
690 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
691 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
692 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
693 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
694 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
695 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
696 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
697 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
698 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
699 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
700 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
701 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
702 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
703 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
704 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
705 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
706 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
707 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
708 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
709 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
710 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
711 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
712 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
713 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
714 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
715 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
716 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
717 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
718 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
719 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
720 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
721 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
722 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
723 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
724 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
725 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
726 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
727 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
728 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
729 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
730 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
731 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
732 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
733 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
734 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
735 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
736 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
737 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
738 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
739 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
740 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
741 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
742 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
743 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
744 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
745 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
746 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
747 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
748 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
749 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
750 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
751 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
752 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
753 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
754 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
755 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
756 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
757 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
758 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
759 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
760 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
761 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
762 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
763 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
764 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
765 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
766 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
767 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
768 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
769 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
770 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
771 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
772 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
773 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
774 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
775 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
776 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
777 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
778 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
779 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
780 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
781 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
782 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
783 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
784 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
785 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
786 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
787 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
788 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
789 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
790 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
791 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
792 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
793 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
794 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
795 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
796 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
797 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
798 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
799 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
800 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
801 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
802 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
803 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
804 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
805 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
806 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
807 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
808 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
809 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
810 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
811 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
812 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
813 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
814 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
815 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
816 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
817 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
818 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
819 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
820 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
821 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
822 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
823 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
824 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
825 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
826 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
827 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
828 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
829 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
830 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
831 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
832 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
833 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
834 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
835 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
836 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
837 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
838 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
839 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
840 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
841 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
842 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
843 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
844 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
845 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
846 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
847 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
848 EVEX_W_0F3A72_P_2): Rename to ...
849 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
850 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
851 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
852 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
853 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
854 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
855 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
856 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
857 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
858 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
859 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
860 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
861 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
862 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
863 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
864 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
865 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
866 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
867 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
868 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
869 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
870 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
871 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
872 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
873 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
874 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
875 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
876 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
877 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
878 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
879 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
880 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
881 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
882 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
883 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
884 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
885 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
886 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
887 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
888 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
889 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
890 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
891 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
892 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
893 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
894 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
895 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
896 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
897 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
898 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
899 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
900 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
901 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
902 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
903 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
904 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
905 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
906 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
907 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
908 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
909 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
910 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
911 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
912 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
913 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
914 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
915 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
916 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
917 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
918 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
919 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
920 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
922 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
923 vex_w_table, mod_table): Replace / remove respective entries.
924 (print_insn): Move up dp->prefix_requirement handling. Handle
926 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
927 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
928 Replace / remove respective entries.
930 2020-07-14 Jan Beulich <jbeulich@suse.com>
932 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
933 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
934 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
935 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
936 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
938 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
939 0F2C, 0F2D, 0F2E, and 0F2F.
940 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
943 2020-07-14 Jan Beulich <jbeulich@suse.com>
945 * i386-dis.c (OP_VexR, VexScalarR): New.
946 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
947 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
948 need_vex_reg): Delete.
949 (prefix_table): Replace VexScalar by VexScalarR and
950 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
951 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
952 (vex_len_table): Replace EXqVexScalarS by EXqS.
953 (get_valid_dis386): Don't set need_vex_reg.
954 (print_insn): Don't initialize need_vex_reg.
955 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
956 q_scalar_swap_mode cases.
957 (OP_EX): Don't check for d_scalar_swap_mode and
959 (OP_VEX): Done check need_vex_reg.
960 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
961 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
962 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
964 2020-07-14 Jan Beulich <jbeulich@suse.com>
966 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
967 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
968 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
969 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
970 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
971 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
972 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
973 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
974 (vex_table): Replace Vex128 by Vex.
975 (vex_len_table): Likewise. Adjust referenced enum names.
976 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
977 referenced enum names.
978 (OP_VEX): Drop vex128_mode and vex256_mode cases.
979 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
981 2020-07-14 Jan Beulich <jbeulich@suse.com>
983 * i386-dis.c (dis386): "LW" description now applies to "DQ".
984 (putop): Handle "DQ". Don't handle "LW" anymore.
985 (prefix_table, mod_table): Replace %LW by %DQ.
986 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
988 2020-07-14 Jan Beulich <jbeulich@suse.com>
990 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
991 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
992 d_scalar_swap_mode case handling. Move shift adjsutment into
993 the case its applicable to.
995 2020-07-14 Jan Beulich <jbeulich@suse.com>
997 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
998 (EXbScalar, EXwScalar): Fold to ...
999 (EXbwUnit): ... this.
1000 (b_scalar_mode, w_scalar_mode): Fold to ...
1001 (bw_unit_mode): ... this.
1002 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
1003 w_scalar_mode handling by bw_unit_mode one.
1004 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
1006 * i386-dis-evex-prefix.h: ... here.
1008 2020-07-14 Jan Beulich <jbeulich@suse.com>
1010 * i386-dis.c (PCMPESTR_Fixup): Delete.
1011 (dis386): Adjust "LQ" description.
1012 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
1013 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
1014 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
1015 vpcmpestrm, and vpcmpestri.
1016 (putop): Honor "cond" when handling LQ.
1017 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
1018 vcvtsi2ss and vcvtusi2ss.
1019 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
1020 vcvtsi2sd and vcvtusi2sd.
1022 2020-07-14 Jan Beulich <jbeulich@suse.com>
1024 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
1025 (simd_cmp_op): Add const.
1026 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
1027 (CMP_Fixup): Handle VEX case.
1028 (prefix_table): Replace VCMP by CMP.
1029 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
1031 2020-07-14 Jan Beulich <jbeulich@suse.com>
1033 * i386-dis.c (MOVBE_Fixup): Delete.
1035 (prefix_table): Use Mv for movbe entries.
1037 2020-07-14 Jan Beulich <jbeulich@suse.com>
1039 * i386-dis.c (CRC32_Fixup): Delete.
1040 (prefix_table): Use Eb/Ev for crc32 entries.
1042 2020-07-14 Jan Beulich <jbeulich@suse.com>
1044 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
1045 Conditionalize invocations of "USED_REX (0)".
1047 2020-07-14 Jan Beulich <jbeulich@suse.com>
1049 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
1050 CH, DH, BH, AX, DX): Delete.
1051 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
1052 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
1053 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
1055 2020-07-10 Lili Cui <lili.cui@intel.com>
1057 * i386-dis.c (TMM): New.
1060 (MVexSIBMEM): Likewise.
1061 (tmm_mode): Likewise.
1062 (vex_sibmem_mode): Likewise.
1063 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
1064 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
1065 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
1066 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
1067 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
1068 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
1069 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
1070 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
1071 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
1072 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
1073 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
1074 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
1075 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
1076 (PREFIX_VEX_0F3849_X86_64): Likewise.
1077 (PREFIX_VEX_0F384B_X86_64): Likewise.
1078 (PREFIX_VEX_0F385C_X86_64): Likewise.
1079 (PREFIX_VEX_0F385E_X86_64): Likewise.
1080 (X86_64_VEX_0F3849): Likewise.
1081 (X86_64_VEX_0F384B): Likewise.
1082 (X86_64_VEX_0F385C): Likewise.
1083 (X86_64_VEX_0F385E): Likewise.
1084 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
1085 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
1086 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
1087 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
1088 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
1089 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
1090 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
1091 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
1092 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
1093 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
1094 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
1095 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
1096 (VEX_W_0F3849_X86_64_P_0): Likewise.
1097 (VEX_W_0F3849_X86_64_P_2): Likewise.
1098 (VEX_W_0F3849_X86_64_P_3): Likewise.
1099 (VEX_W_0F384B_X86_64_P_1): Likewise.
1100 (VEX_W_0F384B_X86_64_P_2): Likewise.
1101 (VEX_W_0F384B_X86_64_P_3): Likewise.
1102 (VEX_W_0F385C_X86_64_P_1): Likewise.
1103 (VEX_W_0F385E_X86_64_P_0): Likewise.
1104 (VEX_W_0F385E_X86_64_P_1): Likewise.
1105 (VEX_W_0F385E_X86_64_P_2): Likewise.
1106 (VEX_W_0F385E_X86_64_P_3): Likewise.
1107 (names_tmm): Likewise.
1108 (att_names_tmm): Likewise.
1109 (intel_operand_size): Handle void_mode.
1110 (OP_XMM): Handle tmm_mode.
1113 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1114 CpuAMX_BF16 and CpuAMX_TILE.
1115 (operand_type_shorthands): Add RegTMM.
1116 (operand_type_init): Likewise.
1117 (operand_types): Add Tmmword.
1118 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1119 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1120 * i386-opc.h (CpuAMX_INT8): New.
1121 (CpuAMX_BF16): Likewise.
1122 (CpuAMX_TILE): Likewise.
1124 (Tmmword): Likewise.
1125 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1126 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1127 (i386_operand_type): Add tmmword.
1128 * i386-opc.tbl: Add AMX instructions.
1129 * i386-reg.tbl: Add AMX registers.
1130 * i386-init.h: Regenerated.
1131 * i386-tbl.h: Likewise.
1133 2020-07-08 Jan Beulich <jbeulich@suse.com>
1135 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1136 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1138 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1139 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1141 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1142 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1143 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1144 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1145 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1146 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1147 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1148 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1149 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1150 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1151 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1152 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1153 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1154 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1155 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1156 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1157 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1158 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1159 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1160 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1161 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1162 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1163 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1164 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1165 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1166 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1167 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1168 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1169 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1170 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1171 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1172 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1173 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1174 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1175 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1176 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1177 (reg_table): Re-order XOP entries. Adjust their operands.
1178 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1179 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1180 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1181 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1182 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1183 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1184 entries by references ...
1185 (vex_len_table): ... to resepctive new entries here. For several
1186 new and existing entries reference ...
1187 (vex_w_table): ... new entries here.
1188 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1190 2020-07-08 Jan Beulich <jbeulich@suse.com>
1192 * i386-dis.c (XMVexScalarI4): Define.
1193 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1194 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1195 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1196 (vex_len_table): Move scalar FMA4 entries ...
1197 (prefix_table): ... here.
1198 (OP_REG_VexI4): Handle scalar_mode.
1199 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1200 * i386-tbl.h: Re-generate.
1202 2020-07-08 Jan Beulich <jbeulich@suse.com>
1204 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1205 Vex_2src_2): Delete.
1206 (OP_VexW, VexW): New.
1207 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1208 for shifts and rotates by register.
1210 2020-07-08 Jan Beulich <jbeulich@suse.com>
1212 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1213 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1214 OP_EX_VexReg): Delete.
1215 (OP_VexI4, VexI4): New.
1216 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1217 (prefix_table): ... here.
1218 (print_insn): Drop setting of vex_w_done.
1220 2020-07-08 Jan Beulich <jbeulich@suse.com>
1222 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1223 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1224 (xop_table): Replace operands of 4-operand insns.
1225 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1227 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1229 * arc-opc.c (insert_rbd): New function.
1232 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1235 2020-07-07 Jan Beulich <jbeulich@suse.com>
1237 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1238 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1239 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1240 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1242 (putop): Handle "BW".
1243 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1244 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1246 * i386-dis-evex-prefix.h: ... here.
1248 2020-07-06 Jan Beulich <jbeulich@suse.com>
1250 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1251 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1252 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1253 VEX_W_0FXOP_09_83): New enumerators.
1254 (xop_table): Reference the above.
1255 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1256 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1257 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1258 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1260 2020-07-06 Jan Beulich <jbeulich@suse.com>
1262 * i386-dis.c (EVEX_W_0F3838_P_1,
1263 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1264 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1265 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1266 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1267 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1268 (putop): Centralize management of last[]. Delete SAVE_LAST.
1269 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1270 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1271 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1272 * i386-dis-evex-prefix.h: here.
1274 2020-07-06 Jan Beulich <jbeulich@suse.com>
1276 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1277 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1278 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1279 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1281 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1282 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1283 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1284 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1285 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1286 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1287 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1288 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1289 these, respectively.
1290 * i386-dis-evex-len.h: Adjust comments.
1291 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1292 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1293 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1294 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1295 MOD_EVEX_0F385B_P_2_W_1 table entries.
1296 * i386-dis-evex-w.h: Reference mod_table[] for
1297 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1300 2020-07-06 Jan Beulich <jbeulich@suse.com>
1302 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1303 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1305 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1306 Likewise. Mark 256-bit entries invalid.
1308 2020-07-06 Jan Beulich <jbeulich@suse.com>
1310 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1311 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1312 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1313 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1314 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1315 PREFIX_EVEX_0F382B): Delete.
1316 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1317 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1318 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1319 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1320 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1322 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1323 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1324 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1325 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1327 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1328 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1329 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1330 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1331 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1332 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1333 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1334 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1335 PREFIX_EVEX_0F382B): Remove table entries.
1336 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1337 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1338 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1340 2020-07-06 Jan Beulich <jbeulich@suse.com>
1342 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1343 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1345 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1346 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1347 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1348 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1351 2020-07-06 Jan Beulich <jbeulich@suse.com>
1353 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1354 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1355 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1356 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1357 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1358 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1359 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1360 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1361 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1364 2020-07-06 Jan Beulich <jbeulich@suse.com>
1366 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1367 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1368 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1370 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1372 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1374 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1376 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1378 2020-07-06 Jan Beulich <jbeulich@suse.com>
1380 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1381 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1382 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1383 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1384 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1385 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1386 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1387 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1388 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1389 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1390 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1391 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1392 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1393 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1394 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1395 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1396 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1397 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1398 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1399 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1400 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1401 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1402 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1403 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1404 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1405 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1406 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1407 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1408 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1409 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1410 (prefix_table): Add EXxEVexR to FMA table entries.
1411 (OP_Rounding): Move abort() invocation.
1412 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1413 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1414 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1415 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1416 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1417 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1418 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1419 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1420 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1421 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1423 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1424 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1425 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1426 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1427 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1428 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1429 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1430 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1431 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1432 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1433 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1434 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1435 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1436 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1437 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1438 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1439 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1440 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1441 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1442 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1443 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1444 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1445 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1446 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1447 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1448 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1449 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1450 Delete table entries.
1451 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1452 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1453 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1456 2020-07-06 Jan Beulich <jbeulich@suse.com>
1458 * i386-dis.c (EXqScalarS): Delete.
1459 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1460 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1462 2020-07-06 Jan Beulich <jbeulich@suse.com>
1464 * i386-dis.c (safe-ctype.h): Include.
1465 (EXdScalar, EXqScalar): Delete.
1466 (d_scalar_mode, q_scalar_mode): Delete.
1467 (prefix_table, vex_len_table): Use EXxmm_md in place of
1468 EXdScalar and EXxmm_mq in place of EXqScalar.
1469 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1470 d_scalar_mode and q_scalar_mode.
1471 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1472 (vmovsd): Use EXxmm_mq.
1474 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1477 * arc-dis.c: Fix spelling mistake.
1478 * po/opcodes.pot: Regenerate.
1480 2020-07-06 Nick Clifton <nickc@redhat.com>
1482 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1483 * po/uk.po: Updated Ukranian translation.
1485 2020-07-04 Nick Clifton <nickc@redhat.com>
1487 * configure: Regenerate.
1488 * po/opcodes.pot: Regenerate.
1490 2020-07-04 Nick Clifton <nickc@redhat.com>
1492 Binutils 2.35 branch created.
1494 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1496 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1497 * i386-opc.h (VexSwapSources): New.
1498 (i386_opcode_modifier): Add vexswapsources.
1499 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1500 with two source operands swapped.
1501 * i386-tbl.h: Regenerated.
1503 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1505 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1506 unprivileged CSR can also be initialized.
1508 2020-06-29 Alan Modra <amodra@gmail.com>
1510 * arm-dis.c: Use C style comments.
1511 * cr16-opc.c: Likewise.
1512 * ft32-dis.c: Likewise.
1513 * moxie-opc.c: Likewise.
1514 * tic54x-dis.c: Likewise.
1515 * s12z-opc.c: Remove useless comment.
1516 * xgate-dis.c: Likewise.
1518 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1520 * i386-opc.tbl: Add a blank line.
1522 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1524 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1525 (VecSIB128): Renamed to ...
1527 (VecSIB256): Renamed to ...
1529 (VecSIB512): Renamed to ...
1531 (VecSIB): Renamed to ...
1533 (i386_opcode_modifier): Replace vecsib with sib.
1534 * i386-opc.tbl (VecSIB128): New.
1535 (VecSIB256): Likewise.
1536 (VecSIB512): Likewise.
1537 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1538 and VecSIB512, respectively.
1540 2020-06-26 Jan Beulich <jbeulich@suse.com>
1542 * i386-dis.c: Adjust description of I macro.
1543 (x86_64_table): Drop use of I.
1544 (float_mem): Replace use of I.
1545 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1547 2020-06-26 Jan Beulich <jbeulich@suse.com>
1549 * i386-dis.c: (print_insn): Avoid straight assignment to
1550 priv.orig_sizeflag when processing -M sub-options.
1552 2020-06-25 Jan Beulich <jbeulich@suse.com>
1554 * i386-dis.c: Adjust description of J macro.
1555 (dis386, x86_64_table, mod_table): Replace J.
1556 (putop): Remove handling of J.
1558 2020-06-25 Jan Beulich <jbeulich@suse.com>
1560 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1562 2020-06-25 Jan Beulich <jbeulich@suse.com>
1564 * i386-dis.c: Adjust description of "LQ" macro.
1565 (dis386_twobyte): Use LQ for sysret.
1566 (putop): Adjust handling of LQ.
1568 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1570 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1571 * riscv-dis.c: Include elfxx-riscv.h.
1573 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1575 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1577 2020-06-17 Lili Cui <lili.cui@intel.com>
1579 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1581 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1584 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1585 * i386-opc.tbl: Likewise.
1586 * i386-tbl.h: Regenerated.
1588 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1590 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1592 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1594 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1595 (SR_CORE): Likewise.
1596 (SR_FEAT): Likewise.
1598 (SR_V8_1): Likewise.
1599 (SR_V8_2): Likewise.
1600 (SR_V8_3): Likewise.
1601 (SR_V8_4): Likewise.
1604 (SR_SSBS): Likewise.
1606 (SR_ID_PFR2): Likewise.
1607 (SR_PROFILE): Likewise.
1608 (SR_MEMTAG): Likewise.
1609 (SR_SCXTNUM): Likewise.
1610 (aarch64_sys_regs): Refactor to store feature information in the table.
1611 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1612 that now describe their own features.
1613 (aarch64_pstatefield_supported_p): Likewise.
1615 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1617 * i386-dis.c (prefix_table): Fix a typo in comments.
1619 2020-06-09 Jan Beulich <jbeulich@suse.com>
1621 * i386-dis.c (rex_ignored): Delete.
1622 (ckprefix): Drop rex_ignored initialization.
1623 (get_valid_dis386): Drop setting of rex_ignored.
1624 (print_insn): Drop checking of rex_ignored. Don't record data
1625 size prefix as used with VEX-and-alike encodings.
1627 2020-06-09 Jan Beulich <jbeulich@suse.com>
1629 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1630 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1631 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1632 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1633 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1634 VEX_0F12, and VEX_0F16.
1635 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1636 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1637 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1638 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1639 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1640 MOD_VEX_0F16_PREFIX_2 entries.
1642 2020-06-09 Jan Beulich <jbeulich@suse.com>
1644 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1645 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1646 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1647 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1648 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1649 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1650 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1651 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1652 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1653 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1654 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1655 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1656 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1657 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1658 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1659 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1660 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1661 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1662 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1663 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1664 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1665 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1666 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1667 EVEX_W_0FC6_P_2): Delete.
1668 (print_insn): Add EVEX.W vs embedded prefix consistency check
1669 to prefix validation.
1670 * i386-dis-evex.h (evex_table): Don't further descend for
1671 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1672 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1674 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1675 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1676 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1677 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1678 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1679 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1680 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1681 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1682 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1683 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1684 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1685 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1686 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1687 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1688 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1689 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1690 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1691 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1692 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1693 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1694 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1695 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1696 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1697 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1698 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1699 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1700 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1702 2020-06-09 Jan Beulich <jbeulich@suse.com>
1704 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1705 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1706 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1708 (print_insn): Drop pointless check against bad_opcode. Split
1709 prefix validation into legacy and VEX-and-alike parts.
1710 (putop): Re-work 'X' macro handling.
1712 2020-06-09 Jan Beulich <jbeulich@suse.com>
1714 * i386-dis.c (MOD_0F51): Rename to ...
1715 (MOD_0F50): ... this.
1717 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1719 * arm-dis.c (arm_opcodes): Add dfb.
1720 (thumb32_opcodes): Add dfb.
1722 2020-06-08 Jan Beulich <jbeulich@suse.com>
1724 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1726 2020-06-06 Alan Modra <amodra@gmail.com>
1728 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1730 2020-06-05 Alan Modra <amodra@gmail.com>
1732 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1733 size is large enough.
1735 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1737 * disassemble.c (disassemble_init_for_target): Set endian_code for
1739 * bpf-desc.c: Regenerate.
1740 * bpf-opc.c: Likewise.
1741 * bpf-dis.c: Likewise.
1743 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1745 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1746 (cgen_put_insn_value): Likewise.
1747 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1748 * cgen-dis.in (print_insn): Likewise.
1749 * cgen-ibld.in (insert_1): Likewise.
1750 (insert_1): Likewise.
1751 (insert_insn_normal): Likewise.
1752 (extract_1): Likewise.
1753 * bpf-dis.c: Regenerate.
1754 * bpf-ibld.c: Likewise.
1755 * bpf-ibld.c: Likewise.
1756 * cgen-dis.in: Likewise.
1757 * cgen-ibld.in: Likewise.
1758 * cgen-opc.c: Likewise.
1759 * epiphany-dis.c: Likewise.
1760 * epiphany-ibld.c: Likewise.
1761 * fr30-dis.c: Likewise.
1762 * fr30-ibld.c: Likewise.
1763 * frv-dis.c: Likewise.
1764 * frv-ibld.c: Likewise.
1765 * ip2k-dis.c: Likewise.
1766 * ip2k-ibld.c: Likewise.
1767 * iq2000-dis.c: Likewise.
1768 * iq2000-ibld.c: Likewise.
1769 * lm32-dis.c: Likewise.
1770 * lm32-ibld.c: Likewise.
1771 * m32c-dis.c: Likewise.
1772 * m32c-ibld.c: Likewise.
1773 * m32r-dis.c: Likewise.
1774 * m32r-ibld.c: Likewise.
1775 * mep-dis.c: Likewise.
1776 * mep-ibld.c: Likewise.
1777 * mt-dis.c: Likewise.
1778 * mt-ibld.c: Likewise.
1779 * or1k-dis.c: Likewise.
1780 * or1k-ibld.c: Likewise.
1781 * xc16x-dis.c: Likewise.
1782 * xc16x-ibld.c: Likewise.
1783 * xstormy16-dis.c: Likewise.
1784 * xstormy16-ibld.c: Likewise.
1786 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1788 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1789 (print_insn_): Handle instruction endian.
1790 * bpf-dis.c: Regenerate.
1791 * bpf-desc.c: Regenerate.
1792 * epiphany-dis.c: Likewise.
1793 * epiphany-desc.c: Likewise.
1794 * fr30-dis.c: Likewise.
1795 * fr30-desc.c: Likewise.
1796 * frv-dis.c: Likewise.
1797 * frv-desc.c: Likewise.
1798 * ip2k-dis.c: Likewise.
1799 * ip2k-desc.c: Likewise.
1800 * iq2000-dis.c: Likewise.
1801 * iq2000-desc.c: Likewise.
1802 * lm32-dis.c: Likewise.
1803 * lm32-desc.c: Likewise.
1804 * m32c-dis.c: Likewise.
1805 * m32c-desc.c: Likewise.
1806 * m32r-dis.c: Likewise.
1807 * m32r-desc.c: Likewise.
1808 * mep-dis.c: Likewise.
1809 * mep-desc.c: Likewise.
1810 * mt-dis.c: Likewise.
1811 * mt-desc.c: Likewise.
1812 * or1k-dis.c: Likewise.
1813 * or1k-desc.c: Likewise.
1814 * xc16x-dis.c: Likewise.
1815 * xc16x-desc.c: Likewise.
1816 * xstormy16-dis.c: Likewise.
1817 * xstormy16-desc.c: Likewise.
1819 2020-06-03 Nick Clifton <nickc@redhat.com>
1821 * po/sr.po: Updated Serbian translation.
1823 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1825 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1826 (riscv_get_priv_spec_class): Likewise.
1828 2020-06-01 Alan Modra <amodra@gmail.com>
1830 * bpf-desc.c: Regenerate.
1832 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1833 David Faust <david.faust@oracle.com>
1835 * bpf-desc.c: Regenerate.
1836 * bpf-opc.h: Likewise.
1837 * bpf-opc.c: Likewise.
1838 * bpf-dis.c: Likewise.
1840 2020-05-28 Alan Modra <amodra@gmail.com>
1842 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1845 2020-05-28 Alan Modra <amodra@gmail.com>
1847 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1849 (print_insn_ns32k): Revert last change.
1851 2020-05-28 Nick Clifton <nickc@redhat.com>
1853 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1856 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1858 Fix extraction of signed constants in nios2 disassembler (again).
1860 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1861 extractions of signed fields.
1863 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1865 * s390-opc.txt: Relocate vector load/store instructions with
1866 additional alignment parameter and change architecture level
1867 constraint from z14 to z13.
1869 2020-05-21 Alan Modra <amodra@gmail.com>
1871 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1872 * sparc-dis.c: Likewise.
1873 * tic4x-dis.c: Likewise.
1874 * xtensa-dis.c: Likewise.
1875 * bpf-desc.c: Regenerate.
1876 * epiphany-desc.c: Regenerate.
1877 * fr30-desc.c: Regenerate.
1878 * frv-desc.c: Regenerate.
1879 * ip2k-desc.c: Regenerate.
1880 * iq2000-desc.c: Regenerate.
1881 * lm32-desc.c: Regenerate.
1882 * m32c-desc.c: Regenerate.
1883 * m32r-desc.c: Regenerate.
1884 * mep-asm.c: Regenerate.
1885 * mep-desc.c: Regenerate.
1886 * mt-desc.c: Regenerate.
1887 * or1k-desc.c: Regenerate.
1888 * xc16x-desc.c: Regenerate.
1889 * xstormy16-desc.c: Regenerate.
1891 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1893 * riscv-opc.c (riscv_ext_version_table): The table used to store
1894 all information about the supported spec and the corresponding ISA
1895 versions. Currently, only Zicsr is supported to verify the
1896 correctness of Z sub extension settings. Others will be supported
1897 in the future patches.
1898 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1899 classes and the corresponding strings.
1900 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1901 spec class by giving a ISA spec string.
1902 * riscv-opc.c (struct priv_spec_t): New structure.
1903 (struct priv_spec_t priv_specs): List for all supported privilege spec
1904 classes and the corresponding strings.
1905 (riscv_get_priv_spec_class): New function. Get the corresponding
1906 privilege spec class by giving a spec string.
1907 (riscv_get_priv_spec_name): New function. Get the corresponding
1908 privilege spec string by giving a CSR version class.
1909 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1910 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1911 according to the chosen version. Build a hash table riscv_csr_hash to
1912 store the valid CSR for the chosen pirv verison. Dump the direct
1913 CSR address rather than it's name if it is invalid.
1914 (parse_riscv_dis_option_without_args): New function. Parse the options
1916 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1917 parse the options without arguments first, and then handle the options
1918 with arguments. Add the new option -Mpriv-spec, which has argument.
1919 * riscv-dis.c (print_riscv_disassembler_options): Add description
1920 about the new OBJDUMP option.
1922 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1924 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1925 WC values on POWER10 sync, dcbf and wait instructions.
1926 (insert_pl, extract_pl): New functions.
1927 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1928 (LS3): New , 3-bit L for sync.
1929 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1930 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1931 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1932 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1933 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1934 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1935 <wait>: Enable PL operand on POWER10.
1936 <dcbf>: Enable L3OPT operand on POWER10.
1937 <sync>: Enable SC2 operand on POWER10.
1939 2020-05-19 Stafford Horne <shorne@gmail.com>
1942 * or1k-asm.c: Regenerate.
1943 * or1k-desc.c: Regenerate.
1944 * or1k-desc.h: Regenerate.
1945 * or1k-dis.c: Regenerate.
1946 * or1k-ibld.c: Regenerate.
1947 * or1k-opc.c: Regenerate.
1948 * or1k-opc.h: Regenerate.
1949 * or1k-opinst.c: Regenerate.
1951 2020-05-11 Alan Modra <amodra@gmail.com>
1953 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1956 2020-05-11 Alan Modra <amodra@gmail.com>
1958 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1959 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1961 2020-05-11 Alan Modra <amodra@gmail.com>
1963 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1965 2020-05-11 Alan Modra <amodra@gmail.com>
1967 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1968 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1970 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1972 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1975 2020-05-11 Alan Modra <amodra@gmail.com>
1977 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1978 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1979 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1980 (prefix_opcodes): Add xxeval.
1982 2020-05-11 Alan Modra <amodra@gmail.com>
1984 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1985 xxgenpcvwm, xxgenpcvdm.
1987 2020-05-11 Alan Modra <amodra@gmail.com>
1989 * ppc-opc.c (MP, VXVAM_MASK): Define.
1990 (VXVAPS_MASK): Use VXVA_MASK.
1991 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1992 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1993 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1994 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1996 2020-05-11 Alan Modra <amodra@gmail.com>
1997 Peter Bergner <bergner@linux.ibm.com>
1999 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
2001 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
2002 YMSK2, XA6a, XA6ap, XB6a entries.
2003 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
2004 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
2006 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
2007 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
2008 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
2009 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
2010 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
2011 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
2012 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
2013 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
2014 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
2015 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
2016 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
2017 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
2018 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
2019 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
2021 2020-05-11 Alan Modra <amodra@gmail.com>
2023 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
2024 (insert_xts, extract_xts): New functions.
2025 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
2026 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
2027 (VXRC_MASK, VXSH_MASK): Define.
2028 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
2029 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
2030 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
2031 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
2032 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
2033 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
2034 xxblendvh, xxblendvw, xxblendvd, xxpermx.
2036 2020-05-11 Alan Modra <amodra@gmail.com>
2038 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
2039 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
2040 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
2041 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
2042 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
2044 2020-05-11 Alan Modra <amodra@gmail.com>
2046 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
2047 (XTP, DQXP, DQXP_MASK): Define.
2048 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
2049 (prefix_opcodes): Add plxvp and pstxvp.
2051 2020-05-11 Alan Modra <amodra@gmail.com>
2053 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
2054 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
2055 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
2057 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2059 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
2061 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2063 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
2065 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
2067 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
2069 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
2071 2020-05-11 Alan Modra <amodra@gmail.com>
2073 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
2075 2020-05-11 Alan Modra <amodra@gmail.com>
2077 * ppc-dis.c (ppc_opts): Add "power10" entry.
2078 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
2079 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
2081 2020-05-11 Nick Clifton <nickc@redhat.com>
2083 * po/fr.po: Updated French translation.
2085 2020-04-30 Alex Coplan <alex.coplan@arm.com>
2087 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
2088 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
2089 (operand_general_constraint_met_p): validate
2090 AARCH64_OPND_UNDEFINED.
2091 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
2093 * aarch64-asm-2.c: Regenerated.
2094 * aarch64-dis-2.c: Regenerated.
2095 * aarch64-opc-2.c: Regenerated.
2097 2020-04-29 Nick Clifton <nickc@redhat.com>
2100 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
2103 2020-04-29 Nick Clifton <nickc@redhat.com>
2105 * po/sv.po: Updated Swedish translation.
2107 2020-04-29 Nick Clifton <nickc@redhat.com>
2110 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2111 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2112 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2115 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2118 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2119 cmpi only on m68020up and cpu32.
2121 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2123 * aarch64-asm.c (aarch64_ins_none): New.
2124 * aarch64-asm.h (ins_none): New declaration.
2125 * aarch64-dis.c (aarch64_ext_none): New.
2126 * aarch64-dis.h (ext_none): New declaration.
2127 * aarch64-opc.c (aarch64_print_operand): Update case for
2128 AARCH64_OPND_BARRIER_PSB.
2129 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2130 (AARCH64_OPERANDS): Update inserter/extracter for
2131 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2132 * aarch64-asm-2.c: Regenerated.
2133 * aarch64-dis-2.c: Regenerated.
2134 * aarch64-opc-2.c: Regenerated.
2136 2020-04-20 Sudakshina Das <sudi.das@arm.com>
2138 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2139 (aarch64_feature_ras, RAS): Likewise.
2140 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2141 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2142 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2143 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2144 * aarch64-asm-2.c: Regenerated.
2145 * aarch64-dis-2.c: Regenerated.
2146 * aarch64-opc-2.c: Regenerated.
2148 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
2150 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2151 (print_insn_neon): Support disassembly of conditional
2154 2020-02-16 David Faust <david.faust@oracle.com>
2156 * bpf-desc.c: Regenerate.
2157 * bpf-desc.h: Likewise.
2158 * bpf-opc.c: Regenerate.
2159 * bpf-opc.h: Likewise.
2161 2020-04-07 Lili Cui <lili.cui@intel.com>
2163 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2164 (prefix_table): New instructions (see prefixes above).
2165 (rm_table): Likewise
2166 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2167 CPU_ANY_TSXLDTRK_FLAGS.
2168 (cpu_flags): Add CpuTSXLDTRK.
2169 * i386-opc.h (enum): Add CpuTSXLDTRK.
2170 (i386_cpu_flags): Add cputsxldtrk.
2171 * i386-opc.tbl: Add XSUSPLDTRK insns.
2172 * i386-init.h: Regenerate.
2173 * i386-tbl.h: Likewise.
2175 2020-04-02 Lili Cui <lili.cui@intel.com>
2177 * i386-dis.c (prefix_table): New instructions serialize.
2178 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2179 CPU_ANY_SERIALIZE_FLAGS.
2180 (cpu_flags): Add CpuSERIALIZE.
2181 * i386-opc.h (enum): Add CpuSERIALIZE.
2182 (i386_cpu_flags): Add cpuserialize.
2183 * i386-opc.tbl: Add SERIALIZE insns.
2184 * i386-init.h: Regenerate.
2185 * i386-tbl.h: Likewise.
2187 2020-03-26 Alan Modra <amodra@gmail.com>
2189 * disassemble.h (opcodes_assert): Declare.
2190 (OPCODES_ASSERT): Define.
2191 * disassemble.c: Don't include assert.h. Include opintl.h.
2192 (opcodes_assert): New function.
2193 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2194 (bfd_h8_disassemble): Reduce size of data array. Correctly
2195 calculate maxlen. Omit insn decoding when insn length exceeds
2196 maxlen. Exit from nibble loop when looking for E, before
2197 accessing next data byte. Move processing of E outside loop.
2198 Replace tests of maxlen in loop with assertions.
2200 2020-03-26 Alan Modra <amodra@gmail.com>
2202 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2204 2020-03-25 Alan Modra <amodra@gmail.com>
2206 * z80-dis.c (suffix): Init mybuf.
2208 2020-03-22 Alan Modra <amodra@gmail.com>
2210 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2211 successflly read from section.
2213 2020-03-22 Alan Modra <amodra@gmail.com>
2215 * arc-dis.c (find_format): Use ISO C string concatenation rather
2216 than line continuation within a string. Don't access needs_limm
2217 before testing opcode != NULL.
2219 2020-03-22 Alan Modra <amodra@gmail.com>
2221 * ns32k-dis.c (print_insn_arg): Update comment.
2222 (print_insn_ns32k): Reduce size of index_offset array, and
2223 initialize, passing -1 to print_insn_arg for args that are not
2224 an index. Don't exit arg loop early. Abort on bad arg number.
2226 2020-03-22 Alan Modra <amodra@gmail.com>
2228 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2229 * s12z-opc.c: Formatting.
2230 (operands_f): Return an int.
2231 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2232 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2233 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2234 (exg_sex_discrim): Likewise.
2235 (create_immediate_operand, create_bitfield_operand),
2236 (create_register_operand_with_size, create_register_all_operand),
2237 (create_register_all16_operand, create_simple_memory_operand),
2238 (create_memory_operand, create_memory_auto_operand): Don't
2239 segfault on malloc failure.
2240 (z_ext24_decode): Return an int status, negative on fail, zero
2242 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2243 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2244 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2245 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2246 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2247 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2248 (loop_primitive_decode, shift_decode, psh_pul_decode),
2249 (bit_field_decode): Similarly.
2250 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2251 to return value, update callers.
2252 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2253 Don't segfault on NULL operand.
2254 (decode_operation): Return OP_INVALID on first fail.
2255 (decode_s12z): Check all reads, returning -1 on fail.
2257 2020-03-20 Alan Modra <amodra@gmail.com>
2259 * metag-dis.c (print_insn_metag): Don't ignore status from
2262 2020-03-20 Alan Modra <amodra@gmail.com>
2264 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2265 Initialize parts of buffer not written when handling a possible
2266 2-byte insn at end of section. Don't attempt decoding of such
2267 an insn by the 4-byte machinery.
2269 2020-03-20 Alan Modra <amodra@gmail.com>
2271 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2272 partially filled buffer. Prevent lookup of 4-byte insns when
2273 only VLE 2-byte insns are possible due to section size. Print
2274 ".word" rather than ".long" for 2-byte leftovers.
2276 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2279 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2281 2020-03-13 Jan Beulich <jbeulich@suse.com>
2283 * i386-dis.c (X86_64_0D): Rename to ...
2284 (X86_64_0E): ... this.
2286 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2288 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2289 * Makefile.in: Regenerated.
2291 2020-03-09 Jan Beulich <jbeulich@suse.com>
2293 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2295 * i386-tbl.h: Re-generate.
2297 2020-03-09 Jan Beulich <jbeulich@suse.com>
2299 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2300 vprot*, vpsha*, and vpshl*.
2301 * i386-tbl.h: Re-generate.
2303 2020-03-09 Jan Beulich <jbeulich@suse.com>
2305 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2306 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2307 * i386-tbl.h: Re-generate.
2309 2020-03-09 Jan Beulich <jbeulich@suse.com>
2311 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2312 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2313 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2314 * i386-tbl.h: Re-generate.
2316 2020-03-09 Jan Beulich <jbeulich@suse.com>
2318 * i386-gen.c (struct template_arg, struct template_instance,
2319 struct template_param, struct template, templates,
2320 parse_template, expand_templates): New.
2321 (process_i386_opcodes): Various local variables moved to
2322 expand_templates. Call parse_template and expand_templates.
2323 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2324 * i386-tbl.h: Re-generate.
2326 2020-03-06 Jan Beulich <jbeulich@suse.com>
2328 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2329 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2330 register and memory source templates. Replace VexW= by VexW*
2332 * i386-tbl.h: Re-generate.
2334 2020-03-06 Jan Beulich <jbeulich@suse.com>
2336 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2337 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2338 * i386-tbl.h: Re-generate.
2340 2020-03-06 Jan Beulich <jbeulich@suse.com>
2342 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2343 * i386-tbl.h: Re-generate.
2345 2020-03-06 Jan Beulich <jbeulich@suse.com>
2347 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2348 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2349 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2350 VexW0 on SSE2AVX variants.
2351 (vmovq): Drop NoRex64 from XMM/XMM variants.
2352 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2353 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2354 applicable use VexW0.
2355 * i386-tbl.h: Re-generate.
2357 2020-03-06 Jan Beulich <jbeulich@suse.com>
2359 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2360 * i386-opc.h (Rex64): Delete.
2361 (struct i386_opcode_modifier): Remove rex64 field.
2362 * i386-opc.tbl (crc32): Drop Rex64.
2363 Replace Rex64 with Size64 everywhere else.
2364 * i386-tbl.h: Re-generate.
2366 2020-03-06 Jan Beulich <jbeulich@suse.com>
2368 * i386-dis.c (OP_E_memory): Exclude recording of used address
2369 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2370 addressed memory operands for MPX insns.
2372 2020-03-06 Jan Beulich <jbeulich@suse.com>
2374 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2375 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2376 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2377 (ptwrite): Split into non-64-bit and 64-bit forms.
2378 * i386-tbl.h: Re-generate.
2380 2020-03-06 Jan Beulich <jbeulich@suse.com>
2382 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2384 * i386-tbl.h: Re-generate.
2386 2020-03-04 Jan Beulich <jbeulich@suse.com>
2388 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2389 (prefix_table): Move vmmcall here. Add vmgexit.
2390 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2391 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2392 (cpu_flags): Add CpuSEV_ES entry.
2393 * i386-opc.h (CpuSEV_ES): New.
2394 (union i386_cpu_flags): Add cpusev_es field.
2395 * i386-opc.tbl (vmgexit): New.
2396 * i386-init.h, i386-tbl.h: Re-generate.
2398 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2400 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2402 * i386-opc.h (IGNORESIZE): New.
2403 (DEFAULTSIZE): Likewise.
2404 (IgnoreSize): Removed.
2405 (DefaultSize): Likewise.
2406 (MnemonicSize): New.
2407 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2409 * i386-opc.tbl (IgnoreSize): New.
2410 (DefaultSize): Likewise.
2411 * i386-tbl.h: Regenerated.
2413 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2416 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2419 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2422 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2423 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2424 * i386-tbl.h: Regenerated.
2426 2020-02-26 Alan Modra <amodra@gmail.com>
2428 * aarch64-asm.c: Indent labels correctly.
2429 * aarch64-dis.c: Likewise.
2430 * aarch64-gen.c: Likewise.
2431 * aarch64-opc.c: Likewise.
2432 * alpha-dis.c: Likewise.
2433 * i386-dis.c: Likewise.
2434 * nds32-asm.c: Likewise.
2435 * nfp-dis.c: Likewise.
2436 * visium-dis.c: Likewise.
2438 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2440 * arc-regs.h (int_vector_base): Make it available for all ARC
2443 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2445 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2448 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2450 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2451 c.mv/c.li if rs1 is zero.
2453 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2455 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2456 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2458 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2459 * i386-opc.h (CpuABM): Removed.
2461 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2462 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2463 popcnt. Remove CpuABM from lzcnt.
2464 * i386-init.h: Regenerated.
2465 * i386-tbl.h: Likewise.
2467 2020-02-17 Jan Beulich <jbeulich@suse.com>
2469 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2470 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2471 VexW1 instead of open-coding them.
2472 * i386-tbl.h: Re-generate.
2474 2020-02-17 Jan Beulich <jbeulich@suse.com>
2476 * i386-opc.tbl (AddrPrefixOpReg): Define.
2477 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2478 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2479 templates. Drop NoRex64.
2480 * i386-tbl.h: Re-generate.
2482 2020-02-17 Jan Beulich <jbeulich@suse.com>
2485 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2486 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2487 into Intel syntax instance (with Unpsecified) and AT&T one
2489 (vcvtneps2bf16): Likewise, along with folding the two so far
2491 * i386-tbl.h: Re-generate.
2493 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2495 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2496 CPU_ANY_SSE4A_FLAGS.
2498 2020-02-17 Alan Modra <amodra@gmail.com>
2500 * i386-gen.c (cpu_flag_init): Correct last change.
2502 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2504 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2507 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2509 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2512 2020-02-14 Jan Beulich <jbeulich@suse.com>
2515 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2516 destination for Cpu64-only variant.
2517 (movzx): Fold patterns.
2518 * i386-tbl.h: Re-generate.
2520 2020-02-13 Jan Beulich <jbeulich@suse.com>
2522 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2523 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2524 CPU_ANY_SSE4_FLAGS entry.
2525 * i386-init.h: Re-generate.
2527 2020-02-12 Jan Beulich <jbeulich@suse.com>
2529 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2530 with Unspecified, making the present one AT&T syntax only.
2531 * i386-tbl.h: Re-generate.
2533 2020-02-12 Jan Beulich <jbeulich@suse.com>
2535 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2536 * i386-tbl.h: Re-generate.
2538 2020-02-12 Jan Beulich <jbeulich@suse.com>
2541 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2542 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2543 Amd64 and Intel64 templates.
2544 (call, jmp): Likewise for far indirect variants. Dro
2546 * i386-tbl.h: Re-generate.
2548 2020-02-11 Jan Beulich <jbeulich@suse.com>
2550 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2551 * i386-opc.h (ShortForm): Delete.
2552 (struct i386_opcode_modifier): Remove shortform field.
2553 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2554 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2555 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2556 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2558 * i386-tbl.h: Re-generate.
2560 2020-02-11 Jan Beulich <jbeulich@suse.com>
2562 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2563 fucompi): Drop ShortForm from operand-less templates.
2564 * i386-tbl.h: Re-generate.
2566 2020-02-11 Alan Modra <amodra@gmail.com>
2568 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2569 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2570 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2571 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2572 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2574 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2576 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2577 (cde_opcodes): Add VCX* instructions.
2579 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2580 Matthew Malcomson <matthew.malcomson@arm.com>
2582 * arm-dis.c (struct cdeopcode32): New.
2583 (CDE_OPCODE): New macro.
2584 (cde_opcodes): New disassembly table.
2585 (regnames): New option to table.
2586 (cde_coprocs): New global variable.
2587 (print_insn_cde): New
2588 (print_insn_thumb32): Use print_insn_cde.
2589 (parse_arm_disassembler_options): Parse coprocN args.
2591 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2594 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2596 * i386-opc.h (AMD64): Removed.
2597 (Intel64): Likewose.
2599 (INTEL64): Likewise.
2600 (INTEL64ONLY): Likewise.
2601 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2602 * i386-opc.tbl (Amd64): New.
2603 (Intel64): Likewise.
2604 (Intel64Only): Likewise.
2605 Replace AMD64 with Amd64. Update sysenter/sysenter with
2606 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2607 * i386-tbl.h: Regenerated.
2609 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2612 * z80-dis.c: Add support for GBZ80 opcodes.
2614 2020-02-04 Alan Modra <amodra@gmail.com>
2616 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2618 2020-02-03 Alan Modra <amodra@gmail.com>
2620 * m32c-ibld.c: Regenerate.
2622 2020-02-01 Alan Modra <amodra@gmail.com>
2624 * frv-ibld.c: Regenerate.
2626 2020-01-31 Jan Beulich <jbeulich@suse.com>
2628 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2629 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2630 (OP_E_memory): Replace xmm_mdq_mode case label by
2631 vex_scalar_w_dq_mode one.
2632 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2634 2020-01-31 Jan Beulich <jbeulich@suse.com>
2636 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2637 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2638 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2639 (intel_operand_size): Drop vex_w_dq_mode case label.
2641 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2643 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2644 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2646 2020-01-30 Alan Modra <amodra@gmail.com>
2648 * m32c-ibld.c: Regenerate.
2650 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2652 * bpf-opc.c: Regenerate.
2654 2020-01-30 Jan Beulich <jbeulich@suse.com>
2656 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2657 (dis386): Use them to replace C2/C3 table entries.
2658 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2659 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2660 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2661 * i386-tbl.h: Re-generate.
2663 2020-01-30 Jan Beulich <jbeulich@suse.com>
2665 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2667 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2669 * i386-tbl.h: Re-generate.
2671 2020-01-30 Alan Modra <amodra@gmail.com>
2673 * tic4x-dis.c (tic4x_dp): Make unsigned.
2675 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2676 Jan Beulich <jbeulich@suse.com>
2679 * i386-dis.c (MOVSXD_Fixup): New function.
2680 (movsxd_mode): New enum.
2681 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2682 (intel_operand_size): Handle movsxd_mode.
2683 (OP_E_register): Likewise.
2685 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2686 register on movsxd. Add movsxd with 16-bit destination register
2687 for AMD64 and Intel64 ISAs.
2688 * i386-tbl.h: Regenerated.
2690 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2693 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2694 * aarch64-asm-2.c: Regenerate
2695 * aarch64-dis-2.c: Likewise.
2696 * aarch64-opc-2.c: Likewise.
2698 2020-01-21 Jan Beulich <jbeulich@suse.com>
2700 * i386-opc.tbl (sysret): Drop DefaultSize.
2701 * i386-tbl.h: Re-generate.
2703 2020-01-21 Jan Beulich <jbeulich@suse.com>
2705 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2707 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2708 * i386-tbl.h: Re-generate.
2710 2020-01-20 Nick Clifton <nickc@redhat.com>
2712 * po/de.po: Updated German translation.
2713 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2714 * po/uk.po: Updated Ukranian translation.
2716 2020-01-20 Alan Modra <amodra@gmail.com>
2718 * hppa-dis.c (fput_const): Remove useless cast.
2720 2020-01-20 Alan Modra <amodra@gmail.com>
2722 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2724 2020-01-18 Nick Clifton <nickc@redhat.com>
2726 * configure: Regenerate.
2727 * po/opcodes.pot: Regenerate.
2729 2020-01-18 Nick Clifton <nickc@redhat.com>
2731 Binutils 2.34 branch created.
2733 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2735 * opintl.h: Fix spelling error (seperate).
2737 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2739 * i386-opc.tbl: Add {vex} pseudo prefix.
2740 * i386-tbl.h: Regenerated.
2742 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2745 * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2746 (neon_opcodes): Likewise.
2747 (select_arm_features): Make sure we enable MVE bits when selecting
2748 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2751 2020-01-16 Jan Beulich <jbeulich@suse.com>
2753 * i386-opc.tbl: Drop stale comment from XOP section.
2755 2020-01-16 Jan Beulich <jbeulich@suse.com>
2757 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2758 (extractps): Add VexWIG to SSE2AVX forms.
2759 * i386-tbl.h: Re-generate.
2761 2020-01-16 Jan Beulich <jbeulich@suse.com>
2763 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2764 Size64 from and use VexW1 on SSE2AVX forms.
2765 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2766 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2767 * i386-tbl.h: Re-generate.
2769 2020-01-15 Alan Modra <amodra@gmail.com>
2771 * tic4x-dis.c (tic4x_version): Make unsigned long.
2772 (optab, optab_special, registernames): New file scope vars.
2773 (tic4x_print_register): Set up registernames rather than
2774 malloc'd registertable.
2775 (tic4x_disassemble): Delete optable and optable_special. Use
2776 optab and optab_special instead. Throw away old optab,
2777 optab_special and registernames when info->mach changes.
2779 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2782 * z80-dis.c (suffix): Use .db instruction to generate double
2785 2020-01-14 Alan Modra <amodra@gmail.com>
2787 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2788 values to unsigned before shifting.
2790 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2792 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2794 (print_insn_thumb16, print_insn_thumb32): Likewise.
2795 (print_insn): Initialize the insn info.
2796 * i386-dis.c (print_insn): Initialize the insn info fields, and
2799 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2801 * arc-opc.c (C_NE): Make it required.
2803 2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
2805 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2806 reserved register name.
2808 2020-01-13 Alan Modra <amodra@gmail.com>
2810 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2811 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2813 2020-01-13 Alan Modra <amodra@gmail.com>
2815 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2816 result of wasm_read_leb128 in a uint64_t and check that bits
2817 are not lost when copying to other locals. Use uint32_t for
2818 most locals. Use PRId64 when printing int64_t.
2820 2020-01-13 Alan Modra <amodra@gmail.com>
2822 * score-dis.c: Formatting.
2823 * score7-dis.c: Formatting.
2825 2020-01-13 Alan Modra <amodra@gmail.com>
2827 * score-dis.c (print_insn_score48): Use unsigned variables for
2828 unsigned values. Don't left shift negative values.
2829 (print_insn_score32): Likewise.
2830 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2832 2020-01-13 Alan Modra <amodra@gmail.com>
2834 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2836 2020-01-13 Alan Modra <amodra@gmail.com>
2838 * fr30-ibld.c: Regenerate.
2840 2020-01-13 Alan Modra <amodra@gmail.com>
2842 * xgate-dis.c (print_insn): Don't left shift signed value.
2843 (ripBits): Formatting, use 1u.
2845 2020-01-10 Alan Modra <amodra@gmail.com>
2847 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2848 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2850 2020-01-10 Alan Modra <amodra@gmail.com>
2852 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2853 and XRREG value earlier to avoid a shift with negative exponent.
2854 * m10200-dis.c (disassemble): Similarly.
2856 2020-01-09 Nick Clifton <nickc@redhat.com>
2859 * z80-dis.c (ld_ii_ii): Use correct cast.
2861 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2864 * z80-dis.c (ld_ii_ii): Use character constant when checking
2867 2020-01-09 Jan Beulich <jbeulich@suse.com>
2869 * i386-dis.c (SEP_Fixup): New.
2871 (dis386_twobyte): Use it for sysenter/sysexit.
2872 (enum x86_64_isa): Change amd64 enumerator to value 1.
2873 (OP_J): Compare isa64 against intel64 instead of amd64.
2874 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2876 * i386-tbl.h: Re-generate.
2878 2020-01-08 Alan Modra <amodra@gmail.com>
2880 * z8k-dis.c: Include libiberty.h
2881 (instr_data_s): Make max_fetched unsigned.
2882 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2883 Don't exceed byte_info bounds.
2884 (output_instr): Make num_bytes unsigned.
2885 (unpack_instr): Likewise for nibl_count and loop.
2886 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2888 * z8k-opc.h: Regenerate.
2890 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2892 * arc-tbl.h (llock): Use 'LLOCK' as class.
2894 (scond): Use 'SCOND' as class.
2896 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2899 2020-01-06 Alan Modra <amodra@gmail.com>
2901 * m32c-ibld.c: Regenerate.
2903 2020-01-06 Alan Modra <amodra@gmail.com>
2906 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2907 Peek at next byte to prevent recursion on repeated prefix bytes.
2908 Ensure uninitialised "mybuf" is not accessed.
2909 (print_insn_z80): Don't zero n_fetch and n_used here,..
2910 (print_insn_z80_buf): ..do it here instead.
2912 2020-01-04 Alan Modra <amodra@gmail.com>
2914 * m32r-ibld.c: Regenerate.
2916 2020-01-04 Alan Modra <amodra@gmail.com>
2918 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2920 2020-01-04 Alan Modra <amodra@gmail.com>
2922 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2924 2020-01-04 Alan Modra <amodra@gmail.com>
2926 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2928 2020-01-03 Jan Beulich <jbeulich@suse.com>
2930 * aarch64-tbl.h (aarch64_opcode_table): Use
2931 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2933 2020-01-03 Jan Beulich <jbeulich@suse.com>
2935 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2936 forms of SUDOT and USDOT.
2938 2020-01-03 Jan Beulich <jbeulich@suse.com>
2940 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2942 * aarch64-dis-2.c: Re-generate.
2944 2020-01-03 Jan Beulich <jbeulich@suse.com>
2946 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2948 * aarch64-dis-2.c: Re-generate.
2950 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2952 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2954 2020-01-01 Alan Modra <amodra@gmail.com>
2956 Update year range in copyright notice of all files.
2958 For older changes see ChangeLog-2019
2960 Copyright (C) 2020 Free Software Foundation, Inc.
2962 Copying and distribution of this file, with or without modification,
2963 are permitted in any medium without royalty provided the copyright
2964 notice and this notice are preserved.
2970 version-control: never
projects / thirdparty / binutils-gdb.git / blob