opcodes/ChangeLog

   1 2018-07-19  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
   4         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
   5         IgnoreSize and [XYZ]MMword where applicable.
   6         * i386-tbl.h: Re-generate.
   7
   8 2018-07-19  Jan Beulich  <jbeulich@suse.com>
   9
  10         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
  11         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
  12         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
  13         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
  14         * i386-tbl.h: Re-generate.
  15
  16 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
  19         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
  20         VPCLMULQDQ templates into their respective AVX512VL counterparts
  21         where possible, using Disp8ShiftVL and CheckRegSize instead of
  22         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
  23         * i386-tbl.h: Re-generate.
  24
  25 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl: Fold AVX512DQ templates into their respective
  28         AVX512VL counterparts where possible, using Disp8ShiftVL and
  29         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  30         IgnoreSize) as appropriate.
  31         * i386-tbl.h: Re-generate.
  32
  33 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.tbl: Fold AVX512BW templates into their respective
  36         AVX512VL counterparts where possible, using Disp8ShiftVL and
  37         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  38         IgnoreSize) as appropriate.
  39         * i386-tbl.h: Re-generate.
  40
  41 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-opc.tbl: Fold AVX512CD templates into their respective
  44         AVX512VL counterparts where possible, using Disp8ShiftVL and
  45         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  46         IgnoreSize) as appropriate.
  47         * i386-tbl.h: Re-generate.
  48
  49 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.h (DISP8_SHIFT_VL): New.
  52         * i386-opc.tbl (Disp8ShiftVL):  Define.
  53         (various): Fold AVX512VL templates into their respective
  54         AVX512F counterparts where possible, using Disp8ShiftVL and
  55         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  56         IgnoreSize) as appropriate.
  57         * i386-tbl.h: Re-generate.
  58
  59 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  60
  61         * Makefile.am: Change dependencies and rule for
  62         $(srcdir)/i386-init.h.
  63         * Makefile.in: Re-generate.
  64         * i386-gen.c (process_i386_opcodes): New local variable
  65         "marker". Drop opening of input file. Recognize marker and line
  66         number directives.
  67         * i386-opc.tbl (OPCODE_I386_H): Define.
  68         (i386-opc.h): Include it.
  69         (None): Undefine.
  70
  71 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  72
  73         PR gas/23418
  74         * i386-opc.h (Byte): Update comments.
  75         (Word): Likewise.
  76         (Dword): Likewise.
  77         (Fword): Likewise.
  78         (Qword): Likewise.
  79         (Tbyte): Likewise.
  80         (Xmmword): Likewise.
  81         (Ymmword): Likewise.
  82         (Zmmword): Likewise.
  83         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
  84         vcvttps2uqq.
  85         * i386-tbl.h: Regenerated.
  86
  87 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
  88
  89         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
  90         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
  91         * aarch64-asm-2.c: Regenerate.
  92         * aarch64-dis-2.c: Regenerate.
  93         * aarch64-opc-2.c: Regenerate.
  94
  95 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
  96
  97         PR binutils/23192
  98         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
  99         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 100         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 101         sqdmulh, sqrdmulh): Use Em16.
 102
 103 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 104
 105         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 106         csdb together with them.
 107         (thumb32_opcodes): Likewise.
 108
 109 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 110
 111         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 112         requiring 32-bit registers as operands 2 and 3. Improve
 113         comments.
 114         (mwait, mwaitx): Fold templates. Improve comments.
 115         OPERAND_TYPE_INOUTPORTREG.
 116         * i386-tbl.h: Re-generate.
 117
 118 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-gen.c (operand_type_init): Remove
 121         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 122         OPERAND_TYPE_INOUTPORTREG.
 123         * i386-init.h: Re-generate.
 124
 125 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 128         (wrssq, wrussq): Add Qword.
 129         * i386-tbl.h: Re-generate.
 130
 131 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-opc.h: Rename OTMax to OTNum.
 134         (OTNumOfUints): Adjust calculation.
 135         (OTUnused): Directly alias to OTNum.
 136
 137 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 138
 139         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 140         `reg_xys'.
 141         (lea_reg_xys): Likewise.
 142         (print_insn_loop_primitive): Rename `reg' local variable to
 143         `reg_dxy'.
 144
 145 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 146
 147         PR binutils/23242
 148         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 149
 150 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 151
 152         PR binutils/23369
 153         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 154         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 155
 156 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 157
 158         PR tdep/8282
 159         * mips-dis.c (mips_option_arg_t): New enumeration.
 160         (mips_options): New variable.
 161         (disassembler_options_mips): New function.
 162         (print_mips_disassembler_options): Reimplement in terms of
 163         `disassembler_options_mips'.
 164         * arm-dis.c (disassembler_options_arm): Adapt to using the
 165         `disasm_options_and_args_t' structure.
 166         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 167         * s390-dis.c (disassembler_options_s390): Likewise.
 168
 169 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 170
 171         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 172         expected result.
 173         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 174         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 175         * testsuite/ld-arm/tls-longplt.d: Likewise.
 176
 177 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 178
 179         PR binutils/23192
 180         * aarch64-asm-2.c: Regenerate.
 181         * aarch64-dis-2.c: Likewise.
 182         * aarch64-opc-2.c: Likewise.
 183         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 184         * aarch64-opc.c (operand_general_constraint_met_p,
 185         aarch64_print_operand): Likewise.
 186         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 187         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 188         fmlal2, fmlsl2.
 189         (AARCH64_OPERANDS): Add Em2.
 190
 191 2018-06-26  Nick Clifton  <nickc@redhat.com>
 192
 193         * po/uk.po: Updated Ukranian translation.
 194         * po/de.po: Updated German translation.
 195         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 196
 197 2018-06-26  Nick Clifton  <nickc@redhat.com>
 198
 199         * nfp-dis.c: Fix spelling mistake.
 200
 201 2018-06-24  Nick Clifton  <nickc@redhat.com>
 202
 203         * configure: Regenerate.
 204         * po/opcodes.pot: Regenerate.
 205
 206 2018-06-24  Nick Clifton  <nickc@redhat.com>
 207
 208         2.31 branch created.
 209
 210 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 211
 212         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 213         * aarch64-asm-2.c: Regenerate.
 214         * aarch64-dis-2.c: Likewise.
 215
 216 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 217
 218         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 219         `-M ginv' option description.
 220
 221 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 222
 223         PR gas/23305
 224         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 225         la and lla.
 226
 227 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 228
 229         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 230         * configure.ac: Remove AC_PREREQ.
 231         * Makefile.in: Re-generate.
 232         * aclocal.m4: Re-generate.
 233         * configure: Re-generate.
 234
 235 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 236
 237         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 238         mips64r6 descriptors.
 239         (parse_mips_ase_option): Handle -Mginv option.
 240         (print_mips_disassembler_options): Document -Mginv.
 241         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 242         (GINV): New macro.
 243         (mips_opcodes): Define ginvi and ginvt.
 244
 245 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 246             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 247
 248         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 249         * mips-opc.c (CRC, CRC64): New macros.
 250         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 251         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 252         crc32cd for CRC64.
 253
 254 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 255
 256         PR 20319
 257         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 258         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 259
 260 2018-06-06  Alan Modra  <amodra@gmail.com>
 261
 262         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 263         setjmp.  Move init for some other vars later too.
 264
 265 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 266
 267         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 268         (dis_private): Add new fields for property section tracking.
 269         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 270         (xtensa_instruction_fits): New functions.
 271         (fetch_data): Bump minimal fetch size to 4.
 272         (print_insn_xtensa): Make struct dis_private static.
 273         Load and prepare property table on section change.
 274         Don't disassemble literals. Don't disassemble instructions that
 275         cross property table boundaries.
 276
 277 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 278
 279         * configure: Regenerated.
 280
 281 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 282
 283         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 284         * i386-tbl.h: Re-generate.
 285
 286 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 287
 288         * i386-opc.tbl (sldt, str): Add NoRex64.
 289         * i386-tbl.h: Re-generate.
 290
 291 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-opc.tbl (invpcid): Add Oword.
 294         * i386-tbl.h: Re-generate.
 295
 296 2018-06-01  Alan Modra  <amodra@gmail.com>
 297
 298         * sysdep.h (_bfd_error_handler): Don't declare.
 299         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 300         * rl78-decode.opc: Likewise.
 301         * msp430-decode.c: Regenerate.
 302         * rl78-decode.c: Regenerate.
 303
 304 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 305
 306         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 307         * i386-init.h : Regenerated.
 308
 309 2018-05-25  Alan Modra  <amodra@gmail.com>
 310
 311         * Makefile.in: Regenerate.
 312         * po/POTFILES.in: Regenerate.
 313
 314 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 315
 316         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 317         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 318         (insert_bab, extract_bab, insert_btab, extract_btab,
 319         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 320         (BAT, BBA VBA RBS XB6S): Delete macros.
 321         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 322         (BB, BD, RBX, XC6): Update for new macros.
 323         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 324         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 325         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 326         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 327
 328 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 329
 330         * Makefile.am: Add support for s12z architecture.
 331         * configure.ac: Likewise.
 332         * disassemble.c: Likewise.
 333         * disassemble.h: Likewise.
 334         * Makefile.in: Regenerate.
 335         * configure: Regenerate.
 336         * s12z-dis.c: New file.
 337         * s12z.h: New file.
 338
 339 2018-05-18  Alan Modra  <amodra@gmail.com>
 340
 341         * nfp-dis.c: Don't #include libbfd.h.
 342         (init_nfp3200_priv): Use bfd_get_section_contents.
 343         (nit_nfp6000_mecsr_sec): Likewise.
 344
 345 2018-05-17  Nick Clifton  <nickc@redhat.com>
 346
 347         * po/zh_CN.po: Updated simplified Chinese translation.
 348
 349 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 350
 351         PR binutils/23109
 352         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 353         * aarch64-dis-2.c: Regenerate.
 354
 355 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 356
 357         PR binutils/21446
 358         * aarch64-asm.c (opintl.h): Include.
 359         (aarch64_ins_sysreg): Enforce read/write constraints.
 360         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 361         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 362         (F_REG_READ, F_REG_WRITE): New.
 363         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 364         AARCH64_OPND_SYSREG.
 365         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 366         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 367         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 368         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 369         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 370         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 371         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 372         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 373         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 374         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 375         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 376         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 377         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 378         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 379         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 380         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 381         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 382
 383 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 384
 385         PR binutils/21446
 386         * aarch64-dis.c (no_notes: New.
 387         (parse_aarch64_dis_option): Support notes.
 388         (aarch64_decode_insn, print_operands): Likewise.
 389         (print_aarch64_disassembler_options): Document notes.
 390         * aarch64-opc.c (aarch64_print_operand): Support notes.
 391
 392 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 393
 394         PR binutils/21446
 395         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 396         and take error struct.
 397         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 398         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 399         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 400         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 401         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 402         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 403         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 404         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 405         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 406         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 407         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 408         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 409         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 410         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 411         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 412         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 413         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 414         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 415         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 416         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 417         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 418         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 419         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 420         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 421         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 422         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 423         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 424         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 425         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 426         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 427         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 428         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 429         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 430         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 431         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 432         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 433         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 434         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 435         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 436         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 437         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 438         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 439         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 440         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 441         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 442         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 443         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 444         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 445         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 446         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 447         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 448         (determine_disassembling_preference, aarch64_decode_insn,
 449         print_insn_aarch64_word, print_insn_data): Take errors struct.
 450         (print_insn_aarch64): Use errors.
 451         * aarch64-asm-2.c: Regenerate.
 452         * aarch64-dis-2.c: Regenerate.
 453         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 454         boolean in aarch64_insert_operan.
 455         (print_operand_extractor): Likewise.
 456         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 457
 458 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 459
 460         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 461
 462 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 463
 464         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 465
 466 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 467
 468         * cr16-opc.c (cr16_instruction): Comment typo fix.
 469         * hppa-dis.c (print_insn_hppa): Likewise.
 470
 471 2018-05-08  Jim Wilson  <jimw@sifive.com>
 472
 473         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 474         (match_c_slli64, match_srxi_as_c_srxi): New.
 475         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 476         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 477         <c.slli, c.srli, c.srai>: Use match_s_slli.
 478         <c.slli64, c.srli64, c.srai64>: New.
 479
 480 2018-05-08  Alan Modra  <amodra@gmail.com>
 481
 482         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 483         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 484         partition opcode space for index lookup.
 485
 486 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 487
 488         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 489         <insn_length>: ...with this.  Update usage.
 490         Remove duplicate call to *info->memory_error_func.
 491
 492 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 493             H.J. Lu  <hongjiu.lu@intel.com>
 494
 495         * i386-dis.c (Gva): New.
 496         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 497         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 498         (prefix_table): New instructions (see prefix above).
 499         (mod_table): New instructions (see prefix above).
 500         (OP_G): Handle va_mode.
 501         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 502         CPU_MOVDIR64B_FLAGS.
 503         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 504         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 505         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 506         * i386-opc.tbl: Add movidir{i,64b}.
 507         * i386-init.h: Regenerated.
 508         * i386-tbl.h: Likewise.
 509
 510 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 511
 512         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 513         AddrPrefixOpReg.
 514         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 515         (AddrPrefixOpReg): This.
 516         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 517         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 518
 519 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 520
 521         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 522         (vle_num_opcodes): Likewise.
 523         (spe2_num_opcodes): Likewise.
 524         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 525         initialization loop.
 526         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 527         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 528         only once.
 529
 530 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 531
 532         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 533
 534 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 535
 536         Makefile.am: Added nfp-dis.c.
 537         configure.ac: Added bfd_nfp_arch.
 538         disassemble.h: Added print_insn_nfp prototype.
 539         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 540         nfp-dis.c: New, for NFP support.
 541         po/POTFILES.in: Added nfp-dis.c to the list.
 542         Makefile.in: Regenerate.
 543         configure: Regenerate.
 544
 545 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 546
 547         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 548         templates into their base ones.
 549         * i386-tlb.h: Re-generate.
 550
 551 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 552
 553         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 554         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 555         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 556         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 557         * i386-init.h: Re-generate.
 558
 559 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 560
 561         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 562         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 563         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 564         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 565         comment.
 566         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 567         and CpuRegMask.
 568         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 569         CpuRegMask: Delete.
 570         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 571         cpuregzmm, and cpuregmask.
 572         * i386-init.h: Re-generate.
 573         * i386-tbl.h: Re-generate.
 574
 575 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 576
 577         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 578         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 579         * i386-init.h: Re-generate.
 580
 581 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 582
 583         * i386-gen.c (VexImmExt): Delete.
 584         * i386-opc.h (VexImmExt, veximmext): Delete.
 585         * i386-opc.tbl: Drop all VexImmExt uses.
 586         * i386-tlb.h: Re-generate.
 587
 588 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 591         register-only forms.
 592         * i386-tlb.h: Re-generate.
 593
 594 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 595
 596         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 597
 598 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 599
 600         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 601         PREFIX_0F1C.
 602         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 603         (cpu_flags): Add CpuCLDEMOTE.
 604         * i386-init.h: Regenerate.
 605         * i386-opc.h (enum): Add CpuCLDEMOTE,
 606         (i386_cpu_flags): Add cpucldemote.
 607         * i386-opc.tbl: Add cldemote.
 608         * i386-tbl.h: Regenerate.
 609
 610 2018-04-16  Alan Modra  <amodra@gmail.com>
 611
 612         * Makefile.am: Remove sh5 and sh64 support.
 613         * configure.ac: Likewise.
 614         * disassemble.c: Likewise.
 615         * disassemble.h: Likewise.
 616         * sh-dis.c: Likewise.
 617         * sh64-dis.c: Delete.
 618         * sh64-opc.c: Delete.
 619         * sh64-opc.h: Delete.
 620         * Makefile.in: Regenerate.
 621         * configure: Regenerate.
 622         * po/POTFILES.in: Regenerate.
 623
 624 2018-04-16  Alan Modra  <amodra@gmail.com>
 625
 626         * Makefile.am: Remove w65 support.
 627         * configure.ac: Likewise.
 628         * disassemble.c: Likewise.
 629         * disassemble.h: Likewise.
 630         * w65-dis.c: Delete.
 631         * w65-opc.h: Delete.
 632         * Makefile.in: Regenerate.
 633         * configure: Regenerate.
 634         * po/POTFILES.in: Regenerate.
 635
 636 2018-04-16  Alan Modra  <amodra@gmail.com>
 637
 638         * configure.ac: Remove we32k support.
 639         * configure: Regenerate.
 640
 641 2018-04-16  Alan Modra  <amodra@gmail.com>
 642
 643         * Makefile.am: Remove m88k support.
 644         * configure.ac: Likewise.
 645         * disassemble.c: Likewise.
 646         * disassemble.h: Likewise.
 647         * m88k-dis.c: Delete.
 648         * Makefile.in: Regenerate.
 649         * configure: Regenerate.
 650         * po/POTFILES.in: Regenerate.
 651
 652 2018-04-16  Alan Modra  <amodra@gmail.com>
 653
 654         * Makefile.am: Remove i370 support.
 655         * configure.ac: Likewise.
 656         * disassemble.c: Likewise.
 657         * disassemble.h: Likewise.
 658         * i370-dis.c: Delete.
 659         * i370-opc.c: Delete.
 660         * Makefile.in: Regenerate.
 661         * configure: Regenerate.
 662         * po/POTFILES.in: Regenerate.
 663
 664 2018-04-16  Alan Modra  <amodra@gmail.com>
 665
 666         * Makefile.am: Remove h8500 support.
 667         * configure.ac: Likewise.
 668         * disassemble.c: Likewise.
 669         * disassemble.h: Likewise.
 670         * h8500-dis.c: Delete.
 671         * h8500-opc.h: Delete.
 672         * Makefile.in: Regenerate.
 673         * configure: Regenerate.
 674         * po/POTFILES.in: Regenerate.
 675
 676 2018-04-16  Alan Modra  <amodra@gmail.com>
 677
 678         * configure.ac: Remove tahoe support.
 679         * configure: Regenerate.
 680
 681 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 684         umwait.
 685         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 686         64-bit mode.
 687         * i386-tbl.h: Regenerated.
 688
 689 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 690
 691         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 692         PREFIX_MOD_1_0FAE_REG_6.
 693         (va_mode): New.
 694         (OP_E_register): Use va_mode.
 695         * i386-dis-evex.h (prefix_table):
 696         New instructions (see prefixes above).
 697         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 698         (cpu_flags): Likewise.
 699         * i386-opc.h (enum): Likewise.
 700         (i386_cpu_flags): Likewise.
 701         * i386-opc.tbl: Add umonitor, umwait, tpause.
 702         * i386-init.h: Regenerate.
 703         * i386-tbl.h: Likewise.
 704
 705 2018-04-11  Alan Modra  <amodra@gmail.com>
 706
 707         * opcodes/i860-dis.c: Delete.
 708         * opcodes/i960-dis.c: Delete.
 709         * Makefile.am: Remove i860 and i960 support.
 710         * configure.ac: Likewise.
 711         * disassemble.c: Likewise.
 712         * disassemble.h: Likewise.
 713         * Makefile.in: Regenerate.
 714         * configure: Regenerate.
 715         * po/POTFILES.in: Regenerate.
 716
 717 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 718
 719         PR binutils/23025
 720         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 721         to 0.
 722         (print_insn): Clear vex instead of vex.evex.
 723
 724 2018-04-04  Nick Clifton  <nickc@redhat.com>
 725
 726         * po/es.po: Updated Spanish translation.
 727
 728 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-gen.c (opcode_modifiers): Delete VecESize.
 731         * i386-opc.h (VecESize): Delete.
 732         (struct i386_opcode_modifier): Delete vecesize.
 733         * i386-opc.tbl: Drop VecESize.
 734         * i386-tlb.h: Re-generate.
 735
 736 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 739         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 740         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 741         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 742         * i386-tlb.h: Re-generate.
 743
 744 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 745
 746         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 747         Fold AVX512 forms
 748         * i386-tlb.h: Re-generate.
 749
 750 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 753         (vex_len_table): Drop Y for vcvt*2si.
 754         (putop): Replace plain 'Y' handling by abort().
 755
 756 2018-03-28  Nick Clifton  <nickc@redhat.com>
 757
 758         PR 22988
 759         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 760         instructions with only a base address register.
 761         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 762         handle AARHC64_OPND_SVE_ADDR_R.
 763         (aarch64_print_operand): Likewise.
 764         * aarch64-asm-2.c: Regenerate.
 765         * aarch64_dis-2.c: Regenerate.
 766         * aarch64-opc-2.c: Regenerate.
 767
 768 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-opc.tbl: Drop VecESize from register only insn forms and
 771         memory forms not allowing broadcast.
 772         * i386-tlb.h: Re-generate.
 773
 774 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 775
 776         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 777         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 778         sha256*): Drop Disp<N>.
 779
 780 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 781
 782         * i386-dis.c (EbndS, bnd_swap_mode): New.
 783         (prefix_table): Use EbndS.
 784         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 785         * i386-opc.tbl (bndmov): Move misplaced Load.
 786         * i386-tlb.h: Re-generate.
 787
 788 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 789
 790         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 791         templates allowing memory operands and folded ones for register
 792         only flavors.
 793         * i386-tlb.h: Re-generate.
 794
 795 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 798         256-bit templates. Drop redundant leftover Disp<N>.
 799         * i386-tlb.h: Re-generate.
 800
 801 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 802
 803         * riscv-opc.c (riscv_insn_types): New.
 804
 805 2018-03-13  Nick Clifton  <nickc@redhat.com>
 806
 807         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 808
 809 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 810
 811         * i386-opc.tbl: Add Optimize to clr.
 812         * i386-tbl.h: Regenerated.
 813
 814 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 815
 816         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 817         * i386-opc.h (OldGcc): Removed.
 818         (i386_opcode_modifier): Remove oldgcc.
 819         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 820         instructions for old (<= 2.8.1) versions of gcc.
 821         * i386-tbl.h: Regenerated.
 822
 823 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-opc.h (EVEXDYN): New.
 826         * i386-opc.tbl: Fold various AVX512VL templates.
 827         * i386-tlb.h: Re-generate.
 828
 829 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 830
 831         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 832         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 833         vpexpandd, vpexpandq): Fold AFX512VF templates.
 834         * i386-tlb.h: Re-generate.
 835
 836 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 839         Fold 128- and 256-bit VEX-encoded templates.
 840         * i386-tlb.h: Re-generate.
 841
 842 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 843
 844         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 845         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 846         vpexpandd, vpexpandq): Fold AVX512F templates.
 847         * i386-tlb.h: Re-generate.
 848
 849 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 850
 851         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 852         64-bit templates. Drop Disp<N>.
 853         * i386-tlb.h: Re-generate.
 854
 855 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 856
 857         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 858         and 256-bit templates.
 859         * i386-tlb.h: Re-generate.
 860
 861 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 864         * i386-tlb.h: Re-generate.
 865
 866 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 869         Drop NoAVX.
 870         * i386-tlb.h: Re-generate.
 871
 872 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 875         * i386-tlb.h: Re-generate.
 876
 877 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-gen.c (opcode_modifiers): Delete FloatD.
 880         * i386-opc.h (FloatD): Delete.
 881         (struct i386_opcode_modifier): Delete floatd.
 882         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 883         FloatD by D.
 884         * i386-tlb.h: Re-generate.
 885
 886 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 887
 888         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 889
 890 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 891
 892         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 893         * i386-tlb.h: Re-generate.
 894
 895 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 896
 897         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 898         forms.
 899         * i386-tlb.h: Re-generate.
 900
 901 2018-03-07  Alan Modra  <amodra@gmail.com>
 902
 903         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 904         bfd_arch_rs6000.
 905         * disassemble.h (print_insn_rs6000): Delete.
 906         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 907         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 908         (print_insn_rs6000): Delete.
 909
 910 2018-03-03  Alan Modra  <amodra@gmail.com>
 911
 912         * sysdep.h (opcodes_error_handler): Define.
 913         (_bfd_error_handler): Declare.
 914         * Makefile.am: Remove stray #.
 915         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 916         EDIT" comment.
 917         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 918         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 919         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 920         opcodes_error_handler to print errors.  Standardize error messages.
 921         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 922         and include opintl.h.
 923         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 924         * i386-gen.c: Standardize error messages.
 925         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 926         * Makefile.in: Regenerate.
 927         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 928         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 929         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 930         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 931         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 932         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 933         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 934         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 935         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 936         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 937         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 938         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 939         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 940
 941 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 942
 943         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 944         vpsub[bwdq] instructions.
 945         * i386-tbl.h: Regenerated.
 946
 947 2018-03-01  Alan Modra  <amodra@gmail.com>
 948
 949         * configure.ac (ALL_LINGUAS): Sort.
 950         * configure: Regenerate.
 951
 952 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 953
 954         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 955         macro by assignements.
 956
 957 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 958
 959         PR gas/22871
 960         * i386-gen.c (opcode_modifiers): Add Optimize.
 961         * i386-opc.h (Optimize): New enum.
 962         (i386_opcode_modifier): Add optimize.
 963         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 964         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 965         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 966         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 967         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 968         vpxord and vpxorq.
 969         * i386-tbl.h: Regenerated.
 970
 971 2018-02-26  Alan Modra  <amodra@gmail.com>
 972
 973         * crx-dis.c (getregliststring): Allocate a large enough buffer
 974         to silence false positive gcc8 warning.
 975
 976 2018-02-22  Shea Levy <shea@shealevy.com>
 977
 978         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 979
 980 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 981
 982         * i386-opc.tbl: Add {rex},
 983         * i386-tbl.h: Regenerated.
 984
 985 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 986
 987         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 988         (mips16_opcodes): Replace `M' with `m' for "restore".
 989
 990 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 991
 992         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 993
 994 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 995
 996         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 997         variable to `function_index'.
 998
 999 2018-02-13  Nick Clifton  <nickc@redhat.com>
1000
1001         PR 22823
1002         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1003         about truncation of printing.
1004
1005 2018-02-12  Henry Wong <henry@stuffedcow.net>
1006
1007         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1008
1009 2018-02-05  Nick Clifton  <nickc@redhat.com>
1010
1011         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1012
1013 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1014
1015         * i386-dis.c (enum): Add pconfig.
1016         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1017         (cpu_flags): Add CpuPCONFIG.
1018         * i386-opc.h (enum): Add CpuPCONFIG.
1019         (i386_cpu_flags): Add cpupconfig.
1020         * i386-opc.tbl: Add PCONFIG instruction.
1021         * i386-init.h: Regenerate.
1022         * i386-tbl.h: Likewise.
1023
1024 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1025
1026         * i386-dis.c (enum): Add PREFIX_0F09.
1027         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1028         (cpu_flags): Add CpuWBNOINVD.
1029         * i386-opc.h (enum): Add CpuWBNOINVD.
1030         (i386_cpu_flags): Add cpuwbnoinvd.
1031         * i386-opc.tbl: Add WBNOINVD instruction.
1032         * i386-init.h: Regenerate.
1033         * i386-tbl.h: Likewise.
1034
1035 2018-01-17  Jim Wilson  <jimw@sifive.com>
1036
1037         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1038
1039 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1040
1041         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1042         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1043         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1044         (cpu_flags): Add CpuIBT, CpuSHSTK.
1045         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1046         (i386_cpu_flags): Add cpuibt, cpushstk.
1047         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1048         * i386-init.h: Regenerate.
1049         * i386-tbl.h: Likewise.
1050
1051 2018-01-16  Nick Clifton  <nickc@redhat.com>
1052
1053         * po/pt_BR.po: Updated Brazilian Portugese translation.
1054         * po/de.po: Updated German translation.
1055
1056 2018-01-15  Jim Wilson  <jimw@sifive.com>
1057
1058         * riscv-opc.c (match_c_nop): New.
1059         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1060
1061 2018-01-15  Nick Clifton  <nickc@redhat.com>
1062
1063         * po/uk.po: Updated Ukranian translation.
1064
1065 2018-01-13  Nick Clifton  <nickc@redhat.com>
1066
1067         * po/opcodes.pot: Regenerated.
1068
1069 2018-01-13  Nick Clifton  <nickc@redhat.com>
1070
1071         * configure: Regenerate.
1072
1073 2018-01-13  Nick Clifton  <nickc@redhat.com>
1074
1075         2.30 branch created.
1076
1077 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1078
1079         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1080         * i386-tbl.h: Regenerate.
1081
1082 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1083
1084         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1085         * i386-tbl.h: Re-generate.
1086
1087 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1090         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1091         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1092         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1093         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1094         Disp8MemShift of AVX512VL forms.
1095         * i386-tbl.h: Re-generate.
1096
1097 2018-01-09  Jim Wilson  <jimw@sifive.com>
1098
1099         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1100         then the hi_addr value is zero.
1101
1102 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1103
1104         * arm-dis.c (arm_opcodes): Add csdb.
1105         (thumb32_opcodes): Add csdb.
1106
1107 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1108
1109         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1110         * aarch64-asm-2.c: Regenerate.
1111         * aarch64-dis-2.c: Regenerate.
1112         * aarch64-opc-2.c: Regenerate.
1113
1114 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1115
1116         PR gas/22681
1117         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1118         Remove AVX512 vmovd with 64-bit operands.
1119         * i386-tbl.h: Regenerated.
1120
1121 2018-01-05  Jim Wilson  <jimw@sifive.com>
1122
1123         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1124         jalr.
1125
1126 2018-01-03  Alan Modra  <amodra@gmail.com>
1127
1128         Update year range in copyright notice of all files.
1129
1130 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1131
1132         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1133         and OPERAND_TYPE_REGZMM entries.
1134
1135 For older changes see ChangeLog-2017
1136 \f
1137 Copyright (C) 2018 Free Software Foundation, Inc.
1138
1139 Copying and distribution of this file, with or without modification,
1140 are permitted in any medium without royalty provided the copyright
1141 notice and this notice are preserved.
1142
1143 Local Variables:
1144 mode: change-log
1145 left-margin: 8
1146 fill-column: 74
1147 version-control: never
1148 End: