PR23430, Indices misspelled

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

2018-07-24  Alan Modra  <amodra@gmail.com>

        PR 23430
        * or1k-desc.h: Regenerate.

2018-07-24  Jan Beulich  <jbeulich@suse.com>

        * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
        vcvtusi2ss, and vcvtusi2sd.
        * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
        Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
        * i386-tbl.h: Re-generate.

2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>

        * arc-opc.c (extract_w6): Fix extending the sign.

2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>

        * arc-tbl.h (vewt): Allow it for ARC EM family.

2018-07-23  Alan Modra  <amodra@gmail.com>

        PR 23419
        * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
        opcode variants for mtspr/mfspr encodings.

2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
            Maciej W. Rozycki  <macro@mips.com>

        * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
        loongson3a descriptors.
        (parse_mips_ase_option): Handle -M loongson-mmi option.
        (print_mips_disassembler_options): Document -M loongson-mmi.
        * mips-opc.c (LMMI): New macro.
        (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
        instructions.

2018-07-19  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
        vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
        IgnoreSize and [XYZ]MMword where applicable.
        * i386-tbl.h: Re-generate.

2018-07-19  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
        (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
        (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
        (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
        * i386-tbl.h: Re-generate.

2018-07-19  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
        AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
        VPCLMULQDQ templates into their respective AVX512VL counterparts
        where possible, using Disp8ShiftVL and CheckRegSize instead of
        Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
        * i386-tbl.h: Re-generate.

2018-07-19  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl: Fold AVX512DQ templates into their respective
        AVX512VL counterparts where possible, using Disp8ShiftVL and
        CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
        IgnoreSize) as appropriate.
        * i386-tbl.h: Re-generate.

2018-07-19  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl: Fold AVX512BW templates into their respective
        AVX512VL counterparts where possible, using Disp8ShiftVL and
        CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
        IgnoreSize) as appropriate.
        * i386-tbl.h: Re-generate.

2018-07-19  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl: Fold AVX512CD templates into their respective
        AVX512VL counterparts where possible, using Disp8ShiftVL and
        CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
        IgnoreSize) as appropriate.
        * i386-tbl.h: Re-generate.

2018-07-19  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.h (DISP8_SHIFT_VL): New.
        * i386-opc.tbl (Disp8ShiftVL):  Define.
        (various): Fold AVX512VL templates into their respective
        AVX512F counterparts where possible, using Disp8ShiftVL and
        CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
        IgnoreSize) as appropriate.
        * i386-tbl.h: Re-generate.

2018-07-19  Jan Beulich  <jbeulich@suse.com>

        * Makefile.am: Change dependencies and rule for
        $(srcdir)/i386-init.h.
        * Makefile.in: Re-generate.
        * i386-gen.c (process_i386_opcodes): New local variable
        "marker". Drop opening of input file. Recognize marker and line
        number directives.
        * i386-opc.tbl (OPCODE_I386_H): Define.
        (i386-opc.h): Include it.
        (None): Undefine.

2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>

        PR gas/23418
        * i386-opc.h (Byte): Update comments.
        (Word): Likewise.
        (Dword): Likewise.
        (Fword): Likewise.
        (Qword): Likewise.
        (Tbyte): Likewise.
        (Xmmword): Likewise.
        (Ymmword): Likewise.
        (Zmmword): Likewise.
        * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
        vcvttps2uqq.
        * i386-tbl.h: Regenerated.

2018-07-12  Sudakshina Das  <sudi.das@arm.com>

        * aarch64-tbl.h (aarch64_opcode_table): Add entry for
        ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.

2018-07-12  Tamar Christina  <tamar.christina@arm.com>

        PR binutils/23192
        * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
        mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
        umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
        sqdmulh, sqrdmulh): Use Em16.

2018-07-11  Sudakshina Das  <sudi.das@arm.com>

        * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
        csdb together with them.
        (thumb32_opcodes): Likewise.

2018-07-11  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (monitor, monitorx): Add 64-bit template
        requiring 32-bit registers as operands 2 and 3. Improve
        comments.
        (mwait, mwaitx): Fold templates. Improve comments.
        OPERAND_TYPE_INOUTPORTREG.
        * i386-tbl.h: Re-generate.

2018-07-11  Jan Beulich  <jbeulich@suse.com>

        * i386-gen.c (operand_type_init): Remove
        OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
        OPERAND_TYPE_INOUTPORTREG.
        * i386-init.h: Re-generate.

2018-07-11  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (wrssd, wrussd): Add Dword.
        (wrssq, wrussq): Add Qword.
        * i386-tbl.h: Re-generate.

2018-07-11  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.h: Rename OTMax to OTNum.
        (OTNumOfUints): Adjust calculation.
        (OTUnused): Directly alias to OTNum.

2018-07-09  Maciej W. Rozycki  <macro@mips.com>

        * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
        `reg_xys'.
        (lea_reg_xys): Likewise.
        (print_insn_loop_primitive): Rename `reg' local variable to
        `reg_dxy'.

2018-07-06  Tamar Christina  <tamar.christina@arm.com>

        PR binutils/23242
        * aarch64-tbl.h (ldarh): Fix disassembly mask.

2018-07-06  Tamar Christina  <tamar.christina@arm.com>

        PR binutils/23369
        * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
        vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.

2018-07-02  Maciej W. Rozycki  <macro@mips.com>

        PR tdep/8282
        * mips-dis.c (mips_option_arg_t): New enumeration.
        (mips_options): New variable.
        (disassembler_options_mips): New function.
        (print_mips_disassembler_options): Reimplement in terms of
        `disassembler_options_mips'.
        * arm-dis.c (disassembler_options_arm): Adapt to using the
        `disasm_options_and_args_t' structure.
        * ppc-dis.c (disassembler_options_powerpc): Likewise.
        * s390-dis.c (disassembler_options_s390): Likewise.

2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>

        * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
        expected result.
        * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
        * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
        * testsuite/ld-arm/tls-longplt.d: Likewise.

2018-06-29  Tamar Christina  <tamar.christina@arm.com>

        PR binutils/23192
        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Likewise.
        * aarch64-opc-2.c: Likewise.
        * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
        * aarch64-opc.c (operand_general_constraint_met_p,
        aarch64_print_operand): Likewise.
        * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
        smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
        fmlal2, fmlsl2.
        (AARCH64_OPERANDS): Add Em2.

2018-06-26  Nick Clifton  <nickc@redhat.com>

        * po/uk.po: Updated Ukranian translation.
        * po/de.po: Updated German translation.
        * po/pt_BR.po: Updated Brazilian Portuguese translation.

2018-06-26  Nick Clifton  <nickc@redhat.com>

        * nfp-dis.c: Fix spelling mistake.

2018-06-24  Nick Clifton  <nickc@redhat.com>

        * configure: Regenerate.
        * po/opcodes.pot: Regenerate.

2018-06-24  Nick Clifton  <nickc@redhat.com>

        2.31 branch created.

2018-06-19  Tamar Christina  <tamar.christina@arm.com>

        * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Likewise.

2018-06-21  Maciej W. Rozycki  <macro@mips.com>

        * mips-dis.c (print_mips_disassembler_options): Fix a typo in
        `-M ginv' option description.

2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>

        PR gas/23305
        * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
        la and lla.

2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>

        * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
        * configure.ac: Remove AC_PREREQ.
        * Makefile.in: Re-generate.
        * aclocal.m4: Re-generate.
        * configure: Re-generate.

2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

        * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
        mips64r6 descriptors.
        (parse_mips_ase_option): Handle -Mginv option.
        (print_mips_disassembler_options): Document -Mginv.
        * mips-opc.c (decode_mips_operand) <+\>: New operand format.
        (GINV): New macro.
        (mips_opcodes): Define ginvi and ginvt.

2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

        * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
        * mips-opc.c (CRC, CRC64): New macros.
        (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
        crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
        crc32cd for CRC64.

2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>

        PR 20319
        * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
        (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.

2018-06-06  Alan Modra  <amodra@gmail.com>

        * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
        setjmp.  Move init for some other vars later too.

2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>

        * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
        (dis_private): Add new fields for property section tracking.
        (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
        (xtensa_instruction_fits): New functions.
        (fetch_data): Bump minimal fetch size to 4.
        (print_insn_xtensa): Make struct dis_private static.
        Load and prepare property table on section change.
        Don't disassemble literals. Don't disassemble instructions that
        cross property table boundaries.

2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>

        * configure: Regenerated.

2018-06-01  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
        * i386-tbl.h: Re-generate.

2018-06-01  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (sldt, str): Add NoRex64.
        * i386-tbl.h: Re-generate.

2018-06-01  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (invpcid): Add Oword.
        * i386-tbl.h: Re-generate.

2018-06-01  Alan Modra  <amodra@gmail.com>

        * sysdep.h (_bfd_error_handler): Don't declare.
        * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
        * rl78-decode.opc: Likewise.
        * msp430-decode.c: Regenerate.
        * rl78-decode.c: Regenerate.

2018-05-30  Amit Pawar <Amit.Pawar@amd.com>

        * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
        * i386-init.h : Regenerated.

2018-05-25  Alan Modra  <amodra@gmail.com>

        * Makefile.in: Regenerate.
        * po/POTFILES.in: Regenerate.

2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>

        * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
        insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
        (insert_bab, extract_bab, insert_btab, extract_btab,
        insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
        (BAT, BBA VBA RBS XB6S): Delete macros.
        (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
        (BB, BD, RBX, XC6): Update for new macros.
        (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
        crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
        e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
        * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.

2018-05-18  John Darrington  <john@darrington.wattle.id.au>

        * Makefile.am: Add support for s12z architecture.
        * configure.ac: Likewise.
        * disassemble.c: Likewise.
        * disassemble.h: Likewise.
        * Makefile.in: Regenerate.
        * configure: Regenerate.
        * s12z-dis.c: New file.
        * s12z.h: New file.

2018-05-18  Alan Modra  <amodra@gmail.com>

        * nfp-dis.c: Don't #include libbfd.h.
        (init_nfp3200_priv): Use bfd_get_section_contents.
        (nit_nfp6000_mecsr_sec): Likewise.

2018-05-17  Nick Clifton  <nickc@redhat.com>

        * po/zh_CN.po: Updated simplified Chinese translation.

2018-05-16  Tamar Christina  <tamar.christina@arm.com>

        PR binutils/23109
        * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
        * aarch64-dis-2.c: Regenerate.

2018-05-15  Tamar Christina  <tamar.christina@arm.com>

        PR binutils/21446
        * aarch64-asm.c (opintl.h): Include.
        (aarch64_ins_sysreg): Enforce read/write constraints.
        * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
        * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
        (F_REG_READ, F_REG_WRITE): New.
        * aarch64-opc.c (aarch64_print_operand): Generate notes for
        AARCH64_OPND_SYSREG.
        (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
        (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
        mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
        id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
        id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
        id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
        mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
        id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
        id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
        id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
        csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
        rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
        mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
        mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
        pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
        * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
        msr (F_SYS_WRITE), mrs (F_SYS_READ).

2018-05-15  Tamar Christina  <tamar.christina@arm.com>

        PR binutils/21446
        * aarch64-dis.c (no_notes: New.
        (parse_aarch64_dis_option): Support notes.
        (aarch64_decode_insn, print_operands): Likewise.
        (print_aarch64_disassembler_options): Document notes.
        * aarch64-opc.c (aarch64_print_operand): Support notes.

2018-05-15  Tamar Christina  <tamar.christina@arm.com>

        PR binutils/21446
        * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
        and take error struct.
        * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
        aarch64_ins_reglist, aarch64_ins_ldst_reglist,
        aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
        aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
        aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
        aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
        aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
        aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
        aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
        aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
        aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
        aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
        aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
        aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
        aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
        aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
        aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
        aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
        aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
        aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
        aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
        aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
        aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
        aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
        aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
        * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
        * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
        aarch64_ext_reglist, aarch64_ext_ldst_reglist,
        aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
        aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
        aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
        aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
        aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
        aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
        aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
        aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
        aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
        aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
        aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
        aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
        aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
        aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
        aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
        aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
        aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
        aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
        aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
        aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
        aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
        aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
        aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
        (determine_disassembling_preference, aarch64_decode_insn,
        print_insn_aarch64_word, print_insn_data): Take errors struct.
        (print_insn_aarch64): Use errors.
        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-gen.c (print_operand_inserter): Use errors and change type to
        boolean in aarch64_insert_operan.
        (print_operand_extractor): Likewise.
        * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.

2018-05-15  Francois H. Theron  <francois.theron@netronome.com>

        * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.

2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>

        * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.

2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>

        * cr16-opc.c (cr16_instruction): Comment typo fix.
        * hppa-dis.c (print_insn_hppa): Likewise.

2018-05-08  Jim Wilson  <jimw@sifive.com>

        * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
        (match_c_slli64, match_srxi_as_c_srxi): New.
        (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
        <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
        <c.slli, c.srli, c.srai>: Use match_s_slli.
        <c.slli64, c.srli64, c.srai64>: New.

2018-05-08  Alan Modra  <amodra@gmail.com>

        * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
        (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
        partition opcode space for index lookup.

2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>

        * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
        <insn_length>: ...with this.  Update usage.
        Remove duplicate call to *info->memory_error_func.

2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
            H.J. Lu  <hongjiu.lu@intel.com>

        * i386-dis.c (Gva): New.
        (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
        MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
        (prefix_table): New instructions (see prefix above).
        (mod_table): New instructions (see prefix above).
        (OP_G): Handle va_mode.
        * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
        CPU_MOVDIR64B_FLAGS.
        (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
        * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
        (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
        * i386-opc.tbl: Add movidir{i,64b}.
        * i386-init.h: Regenerated.
        * i386-tbl.h: Likewise.

2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>

        * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
        AddrPrefixOpReg.
        * i386-opc.h (AddrPrefixOp0): Renamed to ...
        (AddrPrefixOpReg): This.
        (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
        * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.

2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>

        * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
        (vle_num_opcodes): Likewise.
        (spe2_num_opcodes): Likewise.
        * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
        initialization loop.
        (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
        (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
        only once.

2018-05-01  Tamar Christina  <tamar.christina@arm.com>

        * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.

2018-04-30  Francois H. Theron <francois.theron@netronome.com>

        Makefile.am: Added nfp-dis.c.
        configure.ac: Added bfd_nfp_arch.
        disassemble.h: Added print_insn_nfp prototype.
        disassemble.c: Added ARCH_nfp and call to print_insn_nfp
        nfp-dis.c: New, for NFP support.
        po/POTFILES.in: Added nfp-dis.c to the list.
        Makefile.in: Regenerate.
        configure: Regenerate.

2018-04-26  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl: Fold various non-memory operand AVX512VL
        templates into their base ones.
        * i386-tlb.h: Re-generate.

2018-04-26  Jan Beulich  <jbeulich@suse.com>

        * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
        CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
        CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
        CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
        * i386-init.h: Re-generate.

2018-04-26  Jan Beulich  <jbeulich@suse.com>

        * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
        CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
        CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
        Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
        comment.
        (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
        and CpuRegMask.
        * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
        CpuRegMask: Delete.
        (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
        cpuregzmm, and cpuregmask.
        * i386-init.h: Re-generate.
        * i386-tbl.h: Re-generate.

2018-04-26  Jan Beulich  <jbeulich@suse.com>

        * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
        CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
        * i386-init.h: Re-generate.

2018-04-26  Jan Beulich  <jbeulich@suse.com>

        * i386-gen.c (VexImmExt): Delete.
        * i386-opc.h (VexImmExt, veximmext): Delete.
        * i386-opc.tbl: Drop all VexImmExt uses.
        * i386-tlb.h: Re-generate.

2018-04-25  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
        register-only forms.
        * i386-tlb.h: Re-generate.

2018-04-25  Tamar Christina  <tamar.christina@arm.com>

        * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.

2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

        * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
        PREFIX_0F1C.
        * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
        (cpu_flags): Add CpuCLDEMOTE.
        * i386-init.h: Regenerate.
        * i386-opc.h (enum): Add CpuCLDEMOTE,
        (i386_cpu_flags): Add cpucldemote.
        * i386-opc.tbl: Add cldemote.
        * i386-tbl.h: Regenerate.

2018-04-16  Alan Modra  <amodra@gmail.com>

        * Makefile.am: Remove sh5 and sh64 support.
        * configure.ac: Likewise.
        * disassemble.c: Likewise.
        * disassemble.h: Likewise.
        * sh-dis.c: Likewise.
        * sh64-dis.c: Delete.
        * sh64-opc.c: Delete.
        * sh64-opc.h: Delete.
        * Makefile.in: Regenerate.
        * configure: Regenerate.
        * po/POTFILES.in: Regenerate.

2018-04-16  Alan Modra  <amodra@gmail.com>

        * Makefile.am: Remove w65 support.
        * configure.ac: Likewise.
        * disassemble.c: Likewise.
        * disassemble.h: Likewise.
        * w65-dis.c: Delete.
        * w65-opc.h: Delete.
        * Makefile.in: Regenerate.
        * configure: Regenerate.
        * po/POTFILES.in: Regenerate.

2018-04-16  Alan Modra  <amodra@gmail.com>

        * configure.ac: Remove we32k support.
        * configure: Regenerate.

2018-04-16  Alan Modra  <amodra@gmail.com>

        * Makefile.am: Remove m88k support.
        * configure.ac: Likewise.
        * disassemble.c: Likewise.
        * disassemble.h: Likewise.
        * m88k-dis.c: Delete.
        * Makefile.in: Regenerate.
        * configure: Regenerate.
        * po/POTFILES.in: Regenerate.

2018-04-16  Alan Modra  <amodra@gmail.com>

        * Makefile.am: Remove i370 support.
        * configure.ac: Likewise.
        * disassemble.c: Likewise.
        * disassemble.h: Likewise.
        * i370-dis.c: Delete.
        * i370-opc.c: Delete.
        * Makefile.in: Regenerate.
        * configure: Regenerate.
        * po/POTFILES.in: Regenerate.

2018-04-16  Alan Modra  <amodra@gmail.com>

        * Makefile.am: Remove h8500 support.
        * configure.ac: Likewise.
        * disassemble.c: Likewise.
        * disassemble.h: Likewise.
        * h8500-dis.c: Delete.
        * h8500-opc.h: Delete.
        * Makefile.in: Regenerate.
        * configure: Regenerate.
        * po/POTFILES.in: Regenerate.

2018-04-16  Alan Modra  <amodra@gmail.com>

        * configure.ac: Remove tahoe support.
        * configure: Regenerate.

2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>

        * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
        umwait.
        * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
        64-bit mode.
        * i386-tbl.h: Regenerated.

2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

        * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
        PREFIX_MOD_1_0FAE_REG_6.
        (va_mode): New.
        (OP_E_register): Use va_mode.
        * i386-dis-evex.h (prefix_table):
        New instructions (see prefixes above).
        * i386-gen.c (cpu_flag_init): Add WAITPKG.
        (cpu_flags): Likewise.
        * i386-opc.h (enum): Likewise.
        (i386_cpu_flags): Likewise.
        * i386-opc.tbl: Add umonitor, umwait, tpause.
        * i386-init.h: Regenerate.
        * i386-tbl.h: Likewise.

2018-04-11  Alan Modra  <amodra@gmail.com>

        * opcodes/i860-dis.c: Delete.
        * opcodes/i960-dis.c: Delete.
        * Makefile.am: Remove i860 and i960 support.
        * configure.ac: Likewise.
        * disassemble.c: Likewise.
        * disassemble.h: Likewise.
        * Makefile.in: Regenerate.
        * configure: Regenerate.
        * po/POTFILES.in: Regenerate.

2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>

        PR binutils/23025
        * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
        to 0.
        (print_insn): Clear vex instead of vex.evex.

2018-04-04  Nick Clifton  <nickc@redhat.com>

        * po/es.po: Updated Spanish translation.

2018-03-28  Jan Beulich  <jbeulich@suse.com>

        * i386-gen.c (opcode_modifiers): Delete VecESize.
        * i386-opc.h (VecESize): Delete.
        (struct i386_opcode_modifier): Delete vecesize.
        * i386-opc.tbl: Drop VecESize.
        * i386-tlb.h: Re-generate.

2018-03-28  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
        BROADCAST_1TO4, BROADCAST_1TO2): Delete.
        (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
        * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
        * i386-tlb.h: Re-generate.

2018-03-28  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
        Fold AVX512 forms
        * i386-tlb.h: Re-generate.

2018-03-28  Jan Beulich  <jbeulich@suse.com>

        * i386-dis.c (prefix_table): Drop Y for cvt*2si.
        (vex_len_table): Drop Y for vcvt*2si.
        (putop): Replace plain 'Y' handling by abort().

2018-03-28  Nick Clifton  <nickc@redhat.com>

        PR 22988
        * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
        instructions with only a base address register.
        * aarch64-opc.c (operand_general_constraint_met_p): Add code to
        handle AARHC64_OPND_SVE_ADDR_R.
        (aarch64_print_operand): Likewise.
        * aarch64-asm-2.c: Regenerate.
        * aarch64_dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.

2018-03-22  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl: Drop VecESize from register only insn forms and
        memory forms not allowing broadcast.
        * i386-tlb.h: Re-generate.

2018-03-22  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
        vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
        sha256*): Drop Disp<N>.

2018-03-22  Jan Beulich  <jbeulich@suse.com>

        * i386-dis.c (EbndS, bnd_swap_mode): New.
        (prefix_table): Use EbndS.
        (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
        * i386-opc.tbl (bndmov): Move misplaced Load.
        * i386-tlb.h: Re-generate.

2018-03-22  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
        templates allowing memory operands and folded ones for register
        only flavors.
        * i386-tlb.h: Re-generate.

2018-03-22  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
        256-bit templates. Drop redundant leftover Disp<N>.
        * i386-tlb.h: Re-generate.

2018-03-14  Kito Cheng  <kito.cheng@gmail.com>

        * riscv-opc.c (riscv_insn_types): New.

2018-03-13  Nick Clifton  <nickc@redhat.com>

        * po/pt_BR.po: Updated Brazilian Portuguese translation.

2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>

        * i386-opc.tbl: Add Optimize to clr.
        * i386-tbl.h: Regenerated.

2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>

        * i386-gen.c (opcode_modifiers): Remove OldGcc.
        * i386-opc.h (OldGcc): Removed.
        (i386_opcode_modifier): Remove oldgcc.
        * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
        instructions for old (<= 2.8.1) versions of gcc.
        * i386-tbl.h: Regenerated.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.h (EVEXDYN): New.
        * i386-opc.tbl: Fold various AVX512VL templates.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
        vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
        vpexpandd, vpexpandq): Fold AFX512VF templates.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
        Fold 128- and 256-bit VEX-encoded templates.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
        vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
        vpexpandd, vpexpandq): Fold AVX512F templates.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
        64-bit templates. Drop Disp<N>.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
        and 256-bit templates.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (cmpxchg8b): Add NoRex64.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
        Drop NoAVX.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-gen.c (opcode_modifiers): Delete FloatD.
        * i386-opc.h (FloatD): Delete.
        (struct i386_opcode_modifier): Delete floatd.
        * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
        FloatD by D.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vmovd): Disallow Qword memory operands.
        * i386-tlb.h: Re-generate.

2018-03-08  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
        forms.
        * i386-tlb.h: Re-generate.

2018-03-07  Alan Modra  <amodra@gmail.com>

        * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
        bfd_arch_rs6000.
        * disassemble.h (print_insn_rs6000): Delete.
        * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
        (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
        (print_insn_rs6000): Delete.

2018-03-03  Alan Modra  <amodra@gmail.com>

        * sysdep.h (opcodes_error_handler): Define.
        (_bfd_error_handler): Declare.
        * Makefile.am: Remove stray #.
        * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
        EDIT" comment.
        * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
        * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
        * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
        opcodes_error_handler to print errors.  Standardize error messages.
        * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
        and include opintl.h.
        * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
        * i386-gen.c: Standardize error messages.
        * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
        * Makefile.in: Regenerate.
        * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
        * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
        * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
        * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
        * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
        * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
        * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
        * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
        * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
        * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
        * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
        * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
        * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.

2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>

        * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
        vpsub[bwdq] instructions.
        * i386-tbl.h: Regenerated.

2018-03-01  Alan Modra  <amodra@gmail.com>

        * configure.ac (ALL_LINGUAS): Sort.
        * configure: Regenerate.

2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

        * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
        macro by assignements.

2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>

        PR gas/22871
        * i386-gen.c (opcode_modifiers): Add Optimize.
        * i386-opc.h (Optimize): New enum.
        (i386_opcode_modifier): Add optimize.
        * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
        "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
        "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
        "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
        vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
        vpxord and vpxorq.
        * i386-tbl.h: Regenerated.

2018-02-26  Alan Modra  <amodra@gmail.com>

        * crx-dis.c (getregliststring): Allocate a large enough buffer
        to silence false positive gcc8 warning.

2018-02-22  Shea Levy <shea@shealevy.com>

        * disassemble.c (ARCH_riscv): Define if ARCH_all.

2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>

        * i386-opc.tbl: Add {rex},
        * i386-tbl.h: Regenerated.

2018-02-20  Maciej W. Rozycki  <macro@mips.com>

        * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
        (mips16_opcodes): Replace `M' with `m' for "restore".

2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>

        * arm-dis.c (thumb_opcodes): Fix BXNS mask.

2018-02-13  Maciej W. Rozycki  <macro@mips.com>

        * wasm32-dis.c (print_insn_wasm32): Rename `index' local
        variable to `function_index'.

2018-02-13  Nick Clifton  <nickc@redhat.com>

        PR 22823
        * metag-dis.c (print_fmmov): Double buffer size to avoid warning
        about truncation of printing.

2018-02-12  Henry Wong <henry@stuffedcow.net>

        * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.

2018-02-05  Nick Clifton  <nickc@redhat.com>

        * po/pt_BR.po: Updated Brazilian Portuguese translation.

2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

        * i386-dis.c (enum): Add pconfig.
        * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
        (cpu_flags): Add CpuPCONFIG.
        * i386-opc.h (enum): Add CpuPCONFIG.
        (i386_cpu_flags): Add cpupconfig.
        * i386-opc.tbl: Add PCONFIG instruction.
        * i386-init.h: Regenerate.
        * i386-tbl.h: Likewise.

2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

        * i386-dis.c (enum): Add PREFIX_0F09.
        * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
        (cpu_flags): Add CpuWBNOINVD.
        * i386-opc.h (enum): Add CpuWBNOINVD.
        (i386_cpu_flags): Add cpuwbnoinvd.
        * i386-opc.tbl: Add WBNOINVD instruction.
        * i386-init.h: Regenerate.
        * i386-tbl.h: Likewise.

2018-01-17  Jim Wilson  <jimw@sifive.com>

        * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.

2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

        * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
        Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
        CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
        (cpu_flags): Add CpuIBT, CpuSHSTK.
        * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
        (i386_cpu_flags): Add cpuibt, cpushstk.
        * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
        * i386-init.h: Regenerate.
        * i386-tbl.h: Likewise.

2018-01-16  Nick Clifton  <nickc@redhat.com>

        * po/pt_BR.po: Updated Brazilian Portugese translation.
        * po/de.po: Updated German translation.

2018-01-15  Jim Wilson  <jimw@sifive.com>

        * riscv-opc.c (match_c_nop): New.
        (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.

2018-01-15  Nick Clifton  <nickc@redhat.com>

        * po/uk.po: Updated Ukranian translation.

2018-01-13  Nick Clifton  <nickc@redhat.com>

        * po/opcodes.pot: Regenerated.

2018-01-13  Nick Clifton  <nickc@redhat.com>

        * configure: Regenerate.

2018-01-13  Nick Clifton  <nickc@redhat.com>

        2.30 branch created.

2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

        * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
        * i386-tbl.h: Regenerate.

2018-01-10  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
        * i386-tbl.h: Re-generate.

2018-01-10  Jan Beulich  <jbeulich@suse.com>

        * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
        vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
        vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
        vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
        vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
        Disp8MemShift of AVX512VL forms.
        * i386-tbl.h: Re-generate.

2018-01-09  Jim Wilson  <jimw@sifive.com>

        * riscv-dis.c (maybe_print_address): If base_reg is zero,
        then the hi_addr value is zero.

2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>

        * arm-dis.c (arm_opcodes): Add csdb.
        (thumb32_opcodes): Add csdb.

2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>

        * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.

2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>

        PR gas/22681
        * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
        Remove AVX512 vmovd with 64-bit operands.
        * i386-tbl.h: Regenerated.

2018-01-05  Jim Wilson  <jimw@sifive.com>

        * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
        jalr.

2018-01-03  Alan Modra  <amodra@gmail.com>

        Update year range in copyright notice of all files.

2018-01-02  Jan Beulich  <jbeulich@suse.com>

        * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
        and OPERAND_TYPE_REGZMM entries.

For older changes see ChangeLog-2017
\f
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