opcodes/ChangeLog

   1 2018-07-31  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Use element rather than vector size for AVX512*
   4         scatter/gather insns.
   5         * i386-tbl.h: Re-generate.
   6
   7 2018-07-31  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
  10         (cpu_flags): Drop CpuVREX.
  11         * i386-opc.h (CpuVREX): Delete.
  12         (union i386_cpu_flags): Remove cpuvrex.
  13         * i386-init.h, i386-tbl.h: Re-generate.
  14
  15 2018-07-30  Jim Wilson  <jimw@sifive.com>
  16
  17         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
  18         fields.
  19         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
  20
  21 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
  22
  23         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
  24         * Makefile.in: Regenerated.
  25         * configure.ac: Add C-SKY.
  26         * configure: Regenerated.
  27         * csky-dis.c: New file.
  28         * csky-opc.h: New file.
  29         * disassemble.c (ARCH_csky): Define.
  30         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
  31         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
  32
  33 2018-07-27  Alan Modra  <amodra@gmail.com>
  34
  35         * ppc-opc.c (insert_sprbat): Correct function parameter and
  36         return type.
  37         (extract_sprbat): Likewise, variable too.
  38
  39 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
  40             Alan Modra  <amodra@gmail.com>
  41
  42         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
  43         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
  44         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
  45         support disjointed BAT.
  46         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
  47         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
  48         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
  49
  50 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
  51             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  52
  53         * i386-gen.c (adjust_broadcast_modifier): New function.
  54         (process_i386_opcode_modifier): Add an argument for operands.
  55         Adjust the Broadcast value based on operands.
  56         (output_i386_opcode): Pass operand_types to
  57         process_i386_opcode_modifier.
  58         (process_i386_opcodes): Pass NULL as operands to
  59         process_i386_opcode_modifier.
  60         * i386-opc.h (BYTE_BROADCAST): New.
  61         (WORD_BROADCAST): Likewise.
  62         (DWORD_BROADCAST): Likewise.
  63         (QWORD_BROADCAST): Likewise.
  64         (i386_opcode_modifier): Expand broadcast to 3 bits.
  65         * i386-tbl.h: Regenerated.
  66
  67 2018-07-24  Alan Modra  <amodra@gmail.com>
  68
  69         PR 23430
  70         * or1k-desc.h: Regenerate.
  71
  72 2018-07-24  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
  75         vcvtusi2ss, and vcvtusi2sd.
  76         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
  77         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
  78         * i386-tbl.h: Re-generate.
  79
  80 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
  81
  82         * arc-opc.c (extract_w6): Fix extending the sign.
  83
  84 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
  85
  86         * arc-tbl.h (vewt): Allow it for ARC EM family.
  87
  88 2018-07-23  Alan Modra  <amodra@gmail.com>
  89
  90         PR 23419
  91         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
  92         opcode variants for mtspr/mfspr encodings.
  93
  94 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
  95             Maciej W. Rozycki  <macro@mips.com>
  96
  97         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
  98         loongson3a descriptors.
  99         (parse_mips_ase_option): Handle -M loongson-mmi option.
 100         (print_mips_disassembler_options): Document -M loongson-mmi.
 101         * mips-opc.c (LMMI): New macro.
 102         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 103         instructions.
 104
 105 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 108         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 109         IgnoreSize and [XYZ]MMword where applicable.
 110         * i386-tbl.h: Re-generate.
 111
 112 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 113
 114         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 115         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 116         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 117         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 118         * i386-tbl.h: Re-generate.
 119
 120 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 123         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 124         VPCLMULQDQ templates into their respective AVX512VL counterparts
 125         where possible, using Disp8ShiftVL and CheckRegSize instead of
 126         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 127         * i386-tbl.h: Re-generate.
 128
 129 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 130
 131         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 132         AVX512VL counterparts where possible, using Disp8ShiftVL and
 133         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 134         IgnoreSize) as appropriate.
 135         * i386-tbl.h: Re-generate.
 136
 137 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-opc.tbl: Fold AVX512BW templates into their respective
 140         AVX512VL counterparts where possible, using Disp8ShiftVL and
 141         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 142         IgnoreSize) as appropriate.
 143         * i386-tbl.h: Re-generate.
 144
 145 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-opc.tbl: Fold AVX512CD templates into their respective
 148         AVX512VL counterparts where possible, using Disp8ShiftVL and
 149         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 150         IgnoreSize) as appropriate.
 151         * i386-tbl.h: Re-generate.
 152
 153 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-opc.h (DISP8_SHIFT_VL): New.
 156         * i386-opc.tbl (Disp8ShiftVL):  Define.
 157         (various): Fold AVX512VL templates into their respective
 158         AVX512F counterparts where possible, using Disp8ShiftVL and
 159         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 160         IgnoreSize) as appropriate.
 161         * i386-tbl.h: Re-generate.
 162
 163 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 164
 165         * Makefile.am: Change dependencies and rule for
 166         $(srcdir)/i386-init.h.
 167         * Makefile.in: Re-generate.
 168         * i386-gen.c (process_i386_opcodes): New local variable
 169         "marker". Drop opening of input file. Recognize marker and line
 170         number directives.
 171         * i386-opc.tbl (OPCODE_I386_H): Define.
 172         (i386-opc.h): Include it.
 173         (None): Undefine.
 174
 175 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 176
 177         PR gas/23418
 178         * i386-opc.h (Byte): Update comments.
 179         (Word): Likewise.
 180         (Dword): Likewise.
 181         (Fword): Likewise.
 182         (Qword): Likewise.
 183         (Tbyte): Likewise.
 184         (Xmmword): Likewise.
 185         (Ymmword): Likewise.
 186         (Zmmword): Likewise.
 187         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 188         vcvttps2uqq.
 189         * i386-tbl.h: Regenerated.
 190
 191 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 192
 193         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 194         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 195         * aarch64-asm-2.c: Regenerate.
 196         * aarch64-dis-2.c: Regenerate.
 197         * aarch64-opc-2.c: Regenerate.
 198
 199 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 200
 201         PR binutils/23192
 202         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 203         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 204         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 205         sqdmulh, sqrdmulh): Use Em16.
 206
 207 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 208
 209         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 210         csdb together with them.
 211         (thumb32_opcodes): Likewise.
 212
 213 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 216         requiring 32-bit registers as operands 2 and 3. Improve
 217         comments.
 218         (mwait, mwaitx): Fold templates. Improve comments.
 219         OPERAND_TYPE_INOUTPORTREG.
 220         * i386-tbl.h: Re-generate.
 221
 222 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 223
 224         * i386-gen.c (operand_type_init): Remove
 225         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 226         OPERAND_TYPE_INOUTPORTREG.
 227         * i386-init.h: Re-generate.
 228
 229 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 232         (wrssq, wrussq): Add Qword.
 233         * i386-tbl.h: Re-generate.
 234
 235 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 236
 237         * i386-opc.h: Rename OTMax to OTNum.
 238         (OTNumOfUints): Adjust calculation.
 239         (OTUnused): Directly alias to OTNum.
 240
 241 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 242
 243         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 244         `reg_xys'.
 245         (lea_reg_xys): Likewise.
 246         (print_insn_loop_primitive): Rename `reg' local variable to
 247         `reg_dxy'.
 248
 249 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 250
 251         PR binutils/23242
 252         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 253
 254 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 255
 256         PR binutils/23369
 257         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 258         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 259
 260 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 261
 262         PR tdep/8282
 263         * mips-dis.c (mips_option_arg_t): New enumeration.
 264         (mips_options): New variable.
 265         (disassembler_options_mips): New function.
 266         (print_mips_disassembler_options): Reimplement in terms of
 267         `disassembler_options_mips'.
 268         * arm-dis.c (disassembler_options_arm): Adapt to using the
 269         `disasm_options_and_args_t' structure.
 270         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 271         * s390-dis.c (disassembler_options_s390): Likewise.
 272
 273 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 274
 275         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 276         expected result.
 277         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 278         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 279         * testsuite/ld-arm/tls-longplt.d: Likewise.
 280
 281 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 282
 283         PR binutils/23192
 284         * aarch64-asm-2.c: Regenerate.
 285         * aarch64-dis-2.c: Likewise.
 286         * aarch64-opc-2.c: Likewise.
 287         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 288         * aarch64-opc.c (operand_general_constraint_met_p,
 289         aarch64_print_operand): Likewise.
 290         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 291         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 292         fmlal2, fmlsl2.
 293         (AARCH64_OPERANDS): Add Em2.
 294
 295 2018-06-26  Nick Clifton  <nickc@redhat.com>
 296
 297         * po/uk.po: Updated Ukranian translation.
 298         * po/de.po: Updated German translation.
 299         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 300
 301 2018-06-26  Nick Clifton  <nickc@redhat.com>
 302
 303         * nfp-dis.c: Fix spelling mistake.
 304
 305 2018-06-24  Nick Clifton  <nickc@redhat.com>
 306
 307         * configure: Regenerate.
 308         * po/opcodes.pot: Regenerate.
 309
 310 2018-06-24  Nick Clifton  <nickc@redhat.com>
 311
 312         2.31 branch created.
 313
 314 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 315
 316         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 317         * aarch64-asm-2.c: Regenerate.
 318         * aarch64-dis-2.c: Likewise.
 319
 320 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 321
 322         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 323         `-M ginv' option description.
 324
 325 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 326
 327         PR gas/23305
 328         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 329         la and lla.
 330
 331 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 332
 333         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 334         * configure.ac: Remove AC_PREREQ.
 335         * Makefile.in: Re-generate.
 336         * aclocal.m4: Re-generate.
 337         * configure: Re-generate.
 338
 339 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 340
 341         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 342         mips64r6 descriptors.
 343         (parse_mips_ase_option): Handle -Mginv option.
 344         (print_mips_disassembler_options): Document -Mginv.
 345         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 346         (GINV): New macro.
 347         (mips_opcodes): Define ginvi and ginvt.
 348
 349 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 350             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 351
 352         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 353         * mips-opc.c (CRC, CRC64): New macros.
 354         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 355         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 356         crc32cd for CRC64.
 357
 358 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 359
 360         PR 20319
 361         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 362         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 363
 364 2018-06-06  Alan Modra  <amodra@gmail.com>
 365
 366         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 367         setjmp.  Move init for some other vars later too.
 368
 369 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 370
 371         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 372         (dis_private): Add new fields for property section tracking.
 373         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 374         (xtensa_instruction_fits): New functions.
 375         (fetch_data): Bump minimal fetch size to 4.
 376         (print_insn_xtensa): Make struct dis_private static.
 377         Load and prepare property table on section change.
 378         Don't disassemble literals. Don't disassemble instructions that
 379         cross property table boundaries.
 380
 381 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 382
 383         * configure: Regenerated.
 384
 385 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 388         * i386-tbl.h: Re-generate.
 389
 390 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.tbl (sldt, str): Add NoRex64.
 393         * i386-tbl.h: Re-generate.
 394
 395 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-opc.tbl (invpcid): Add Oword.
 398         * i386-tbl.h: Re-generate.
 399
 400 2018-06-01  Alan Modra  <amodra@gmail.com>
 401
 402         * sysdep.h (_bfd_error_handler): Don't declare.
 403         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 404         * rl78-decode.opc: Likewise.
 405         * msp430-decode.c: Regenerate.
 406         * rl78-decode.c: Regenerate.
 407
 408 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 409
 410         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 411         * i386-init.h : Regenerated.
 412
 413 2018-05-25  Alan Modra  <amodra@gmail.com>
 414
 415         * Makefile.in: Regenerate.
 416         * po/POTFILES.in: Regenerate.
 417
 418 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 419
 420         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 421         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 422         (insert_bab, extract_bab, insert_btab, extract_btab,
 423         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 424         (BAT, BBA VBA RBS XB6S): Delete macros.
 425         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 426         (BB, BD, RBX, XC6): Update for new macros.
 427         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 428         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 429         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 430         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 431
 432 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 433
 434         * Makefile.am: Add support for s12z architecture.
 435         * configure.ac: Likewise.
 436         * disassemble.c: Likewise.
 437         * disassemble.h: Likewise.
 438         * Makefile.in: Regenerate.
 439         * configure: Regenerate.
 440         * s12z-dis.c: New file.
 441         * s12z.h: New file.
 442
 443 2018-05-18  Alan Modra  <amodra@gmail.com>
 444
 445         * nfp-dis.c: Don't #include libbfd.h.
 446         (init_nfp3200_priv): Use bfd_get_section_contents.
 447         (nit_nfp6000_mecsr_sec): Likewise.
 448
 449 2018-05-17  Nick Clifton  <nickc@redhat.com>
 450
 451         * po/zh_CN.po: Updated simplified Chinese translation.
 452
 453 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 454
 455         PR binutils/23109
 456         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 457         * aarch64-dis-2.c: Regenerate.
 458
 459 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 460
 461         PR binutils/21446
 462         * aarch64-asm.c (opintl.h): Include.
 463         (aarch64_ins_sysreg): Enforce read/write constraints.
 464         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 465         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 466         (F_REG_READ, F_REG_WRITE): New.
 467         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 468         AARCH64_OPND_SYSREG.
 469         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 470         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 471         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 472         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 473         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 474         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 475         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 476         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 477         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 478         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 479         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 480         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 481         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 482         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 483         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 484         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 485         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 486
 487 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 488
 489         PR binutils/21446
 490         * aarch64-dis.c (no_notes: New.
 491         (parse_aarch64_dis_option): Support notes.
 492         (aarch64_decode_insn, print_operands): Likewise.
 493         (print_aarch64_disassembler_options): Document notes.
 494         * aarch64-opc.c (aarch64_print_operand): Support notes.
 495
 496 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 497
 498         PR binutils/21446
 499         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 500         and take error struct.
 501         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 502         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 503         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 504         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 505         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 506         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 507         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 508         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 509         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 510         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 511         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 512         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 513         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 514         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 515         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 516         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 517         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 518         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 519         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 520         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 521         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 522         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 523         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 524         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 525         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 526         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 527         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 528         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 529         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 530         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 531         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 532         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 533         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 534         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 535         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 536         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 537         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 538         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 539         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 540         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 541         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 542         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 543         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 544         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 545         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 546         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 547         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 548         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 549         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 550         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 551         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 552         (determine_disassembling_preference, aarch64_decode_insn,
 553         print_insn_aarch64_word, print_insn_data): Take errors struct.
 554         (print_insn_aarch64): Use errors.
 555         * aarch64-asm-2.c: Regenerate.
 556         * aarch64-dis-2.c: Regenerate.
 557         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 558         boolean in aarch64_insert_operan.
 559         (print_operand_extractor): Likewise.
 560         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 561
 562 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 563
 564         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 565
 566 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 567
 568         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 569
 570 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 571
 572         * cr16-opc.c (cr16_instruction): Comment typo fix.
 573         * hppa-dis.c (print_insn_hppa): Likewise.
 574
 575 2018-05-08  Jim Wilson  <jimw@sifive.com>
 576
 577         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 578         (match_c_slli64, match_srxi_as_c_srxi): New.
 579         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 580         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 581         <c.slli, c.srli, c.srai>: Use match_s_slli.
 582         <c.slli64, c.srli64, c.srai64>: New.
 583
 584 2018-05-08  Alan Modra  <amodra@gmail.com>
 585
 586         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 587         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 588         partition opcode space for index lookup.
 589
 590 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 591
 592         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 593         <insn_length>: ...with this.  Update usage.
 594         Remove duplicate call to *info->memory_error_func.
 595
 596 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 597             H.J. Lu  <hongjiu.lu@intel.com>
 598
 599         * i386-dis.c (Gva): New.
 600         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 601         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 602         (prefix_table): New instructions (see prefix above).
 603         (mod_table): New instructions (see prefix above).
 604         (OP_G): Handle va_mode.
 605         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 606         CPU_MOVDIR64B_FLAGS.
 607         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 608         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 609         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 610         * i386-opc.tbl: Add movidir{i,64b}.
 611         * i386-init.h: Regenerated.
 612         * i386-tbl.h: Likewise.
 613
 614 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 617         AddrPrefixOpReg.
 618         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 619         (AddrPrefixOpReg): This.
 620         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 621         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 622
 623 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 624
 625         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 626         (vle_num_opcodes): Likewise.
 627         (spe2_num_opcodes): Likewise.
 628         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 629         initialization loop.
 630         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 631         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 632         only once.
 633
 634 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 635
 636         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 637
 638 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 639
 640         Makefile.am: Added nfp-dis.c.
 641         configure.ac: Added bfd_nfp_arch.
 642         disassemble.h: Added print_insn_nfp prototype.
 643         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 644         nfp-dis.c: New, for NFP support.
 645         po/POTFILES.in: Added nfp-dis.c to the list.
 646         Makefile.in: Regenerate.
 647         configure: Regenerate.
 648
 649 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 650
 651         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 652         templates into their base ones.
 653         * i386-tlb.h: Re-generate.
 654
 655 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 656
 657         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 658         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 659         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 660         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 661         * i386-init.h: Re-generate.
 662
 663 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 664
 665         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 666         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 667         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 668         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 669         comment.
 670         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 671         and CpuRegMask.
 672         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 673         CpuRegMask: Delete.
 674         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 675         cpuregzmm, and cpuregmask.
 676         * i386-init.h: Re-generate.
 677         * i386-tbl.h: Re-generate.
 678
 679 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 680
 681         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 682         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 683         * i386-init.h: Re-generate.
 684
 685 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-gen.c (VexImmExt): Delete.
 688         * i386-opc.h (VexImmExt, veximmext): Delete.
 689         * i386-opc.tbl: Drop all VexImmExt uses.
 690         * i386-tlb.h: Re-generate.
 691
 692 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 695         register-only forms.
 696         * i386-tlb.h: Re-generate.
 697
 698 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 699
 700         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 701
 702 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 703
 704         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 705         PREFIX_0F1C.
 706         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 707         (cpu_flags): Add CpuCLDEMOTE.
 708         * i386-init.h: Regenerate.
 709         * i386-opc.h (enum): Add CpuCLDEMOTE,
 710         (i386_cpu_flags): Add cpucldemote.
 711         * i386-opc.tbl: Add cldemote.
 712         * i386-tbl.h: Regenerate.
 713
 714 2018-04-16  Alan Modra  <amodra@gmail.com>
 715
 716         * Makefile.am: Remove sh5 and sh64 support.
 717         * configure.ac: Likewise.
 718         * disassemble.c: Likewise.
 719         * disassemble.h: Likewise.
 720         * sh-dis.c: Likewise.
 721         * sh64-dis.c: Delete.
 722         * sh64-opc.c: Delete.
 723         * sh64-opc.h: Delete.
 724         * Makefile.in: Regenerate.
 725         * configure: Regenerate.
 726         * po/POTFILES.in: Regenerate.
 727
 728 2018-04-16  Alan Modra  <amodra@gmail.com>
 729
 730         * Makefile.am: Remove w65 support.
 731         * configure.ac: Likewise.
 732         * disassemble.c: Likewise.
 733         * disassemble.h: Likewise.
 734         * w65-dis.c: Delete.
 735         * w65-opc.h: Delete.
 736         * Makefile.in: Regenerate.
 737         * configure: Regenerate.
 738         * po/POTFILES.in: Regenerate.
 739
 740 2018-04-16  Alan Modra  <amodra@gmail.com>
 741
 742         * configure.ac: Remove we32k support.
 743         * configure: Regenerate.
 744
 745 2018-04-16  Alan Modra  <amodra@gmail.com>
 746
 747         * Makefile.am: Remove m88k support.
 748         * configure.ac: Likewise.
 749         * disassemble.c: Likewise.
 750         * disassemble.h: Likewise.
 751         * m88k-dis.c: Delete.
 752         * Makefile.in: Regenerate.
 753         * configure: Regenerate.
 754         * po/POTFILES.in: Regenerate.
 755
 756 2018-04-16  Alan Modra  <amodra@gmail.com>
 757
 758         * Makefile.am: Remove i370 support.
 759         * configure.ac: Likewise.
 760         * disassemble.c: Likewise.
 761         * disassemble.h: Likewise.
 762         * i370-dis.c: Delete.
 763         * i370-opc.c: Delete.
 764         * Makefile.in: Regenerate.
 765         * configure: Regenerate.
 766         * po/POTFILES.in: Regenerate.
 767
 768 2018-04-16  Alan Modra  <amodra@gmail.com>
 769
 770         * Makefile.am: Remove h8500 support.
 771         * configure.ac: Likewise.
 772         * disassemble.c: Likewise.
 773         * disassemble.h: Likewise.
 774         * h8500-dis.c: Delete.
 775         * h8500-opc.h: Delete.
 776         * Makefile.in: Regenerate.
 777         * configure: Regenerate.
 778         * po/POTFILES.in: Regenerate.
 779
 780 2018-04-16  Alan Modra  <amodra@gmail.com>
 781
 782         * configure.ac: Remove tahoe support.
 783         * configure: Regenerate.
 784
 785 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 786
 787         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 788         umwait.
 789         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 790         64-bit mode.
 791         * i386-tbl.h: Regenerated.
 792
 793 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 794
 795         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 796         PREFIX_MOD_1_0FAE_REG_6.
 797         (va_mode): New.
 798         (OP_E_register): Use va_mode.
 799         * i386-dis-evex.h (prefix_table):
 800         New instructions (see prefixes above).
 801         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 802         (cpu_flags): Likewise.
 803         * i386-opc.h (enum): Likewise.
 804         (i386_cpu_flags): Likewise.
 805         * i386-opc.tbl: Add umonitor, umwait, tpause.
 806         * i386-init.h: Regenerate.
 807         * i386-tbl.h: Likewise.
 808
 809 2018-04-11  Alan Modra  <amodra@gmail.com>
 810
 811         * opcodes/i860-dis.c: Delete.
 812         * opcodes/i960-dis.c: Delete.
 813         * Makefile.am: Remove i860 and i960 support.
 814         * configure.ac: Likewise.
 815         * disassemble.c: Likewise.
 816         * disassemble.h: Likewise.
 817         * Makefile.in: Regenerate.
 818         * configure: Regenerate.
 819         * po/POTFILES.in: Regenerate.
 820
 821 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 822
 823         PR binutils/23025
 824         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 825         to 0.
 826         (print_insn): Clear vex instead of vex.evex.
 827
 828 2018-04-04  Nick Clifton  <nickc@redhat.com>
 829
 830         * po/es.po: Updated Spanish translation.
 831
 832 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-gen.c (opcode_modifiers): Delete VecESize.
 835         * i386-opc.h (VecESize): Delete.
 836         (struct i386_opcode_modifier): Delete vecesize.
 837         * i386-opc.tbl: Drop VecESize.
 838         * i386-tlb.h: Re-generate.
 839
 840 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 841
 842         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 843         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 844         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 845         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 846         * i386-tlb.h: Re-generate.
 847
 848 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 851         Fold AVX512 forms
 852         * i386-tlb.h: Re-generate.
 853
 854 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 857         (vex_len_table): Drop Y for vcvt*2si.
 858         (putop): Replace plain 'Y' handling by abort().
 859
 860 2018-03-28  Nick Clifton  <nickc@redhat.com>
 861
 862         PR 22988
 863         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 864         instructions with only a base address register.
 865         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 866         handle AARHC64_OPND_SVE_ADDR_R.
 867         (aarch64_print_operand): Likewise.
 868         * aarch64-asm-2.c: Regenerate.
 869         * aarch64_dis-2.c: Regenerate.
 870         * aarch64-opc-2.c: Regenerate.
 871
 872 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl: Drop VecESize from register only insn forms and
 875         memory forms not allowing broadcast.
 876         * i386-tlb.h: Re-generate.
 877
 878 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 881         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 882         sha256*): Drop Disp<N>.
 883
 884 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 885
 886         * i386-dis.c (EbndS, bnd_swap_mode): New.
 887         (prefix_table): Use EbndS.
 888         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 889         * i386-opc.tbl (bndmov): Move misplaced Load.
 890         * i386-tlb.h: Re-generate.
 891
 892 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 893
 894         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 895         templates allowing memory operands and folded ones for register
 896         only flavors.
 897         * i386-tlb.h: Re-generate.
 898
 899 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 900
 901         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 902         256-bit templates. Drop redundant leftover Disp<N>.
 903         * i386-tlb.h: Re-generate.
 904
 905 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 906
 907         * riscv-opc.c (riscv_insn_types): New.
 908
 909 2018-03-13  Nick Clifton  <nickc@redhat.com>
 910
 911         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 912
 913 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 914
 915         * i386-opc.tbl: Add Optimize to clr.
 916         * i386-tbl.h: Regenerated.
 917
 918 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 919
 920         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 921         * i386-opc.h (OldGcc): Removed.
 922         (i386_opcode_modifier): Remove oldgcc.
 923         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 924         instructions for old (<= 2.8.1) versions of gcc.
 925         * i386-tbl.h: Regenerated.
 926
 927 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 928
 929         * i386-opc.h (EVEXDYN): New.
 930         * i386-opc.tbl: Fold various AVX512VL templates.
 931         * i386-tlb.h: Re-generate.
 932
 933 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 934
 935         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 936         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 937         vpexpandd, vpexpandq): Fold AFX512VF templates.
 938         * i386-tlb.h: Re-generate.
 939
 940 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 941
 942         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 943         Fold 128- and 256-bit VEX-encoded templates.
 944         * i386-tlb.h: Re-generate.
 945
 946 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 949         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 950         vpexpandd, vpexpandq): Fold AVX512F templates.
 951         * i386-tlb.h: Re-generate.
 952
 953 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 954
 955         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 956         64-bit templates. Drop Disp<N>.
 957         * i386-tlb.h: Re-generate.
 958
 959 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 960
 961         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 962         and 256-bit templates.
 963         * i386-tlb.h: Re-generate.
 964
 965 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 966
 967         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 968         * i386-tlb.h: Re-generate.
 969
 970 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 973         Drop NoAVX.
 974         * i386-tlb.h: Re-generate.
 975
 976 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 979         * i386-tlb.h: Re-generate.
 980
 981 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 982
 983         * i386-gen.c (opcode_modifiers): Delete FloatD.
 984         * i386-opc.h (FloatD): Delete.
 985         (struct i386_opcode_modifier): Delete floatd.
 986         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 987         FloatD by D.
 988         * i386-tlb.h: Re-generate.
 989
 990 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 991
 992         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 993
 994 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 997         * i386-tlb.h: Re-generate.
 998
 999 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1002         forms.
1003         * i386-tlb.h: Re-generate.
1004
1005 2018-03-07  Alan Modra  <amodra@gmail.com>
1006
1007         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1008         bfd_arch_rs6000.
1009         * disassemble.h (print_insn_rs6000): Delete.
1010         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1011         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1012         (print_insn_rs6000): Delete.
1013
1014 2018-03-03  Alan Modra  <amodra@gmail.com>
1015
1016         * sysdep.h (opcodes_error_handler): Define.
1017         (_bfd_error_handler): Declare.
1018         * Makefile.am: Remove stray #.
1019         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1020         EDIT" comment.
1021         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1022         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1023         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1024         opcodes_error_handler to print errors.  Standardize error messages.
1025         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1026         and include opintl.h.
1027         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1028         * i386-gen.c: Standardize error messages.
1029         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1030         * Makefile.in: Regenerate.
1031         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1032         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1033         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1034         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1035         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1036         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1037         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1038         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1039         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1040         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1041         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1042         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1043         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1044
1045 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1046
1047         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1048         vpsub[bwdq] instructions.
1049         * i386-tbl.h: Regenerated.
1050
1051 2018-03-01  Alan Modra  <amodra@gmail.com>
1052
1053         * configure.ac (ALL_LINGUAS): Sort.
1054         * configure: Regenerate.
1055
1056 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1057
1058         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1059         macro by assignements.
1060
1061 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1062
1063         PR gas/22871
1064         * i386-gen.c (opcode_modifiers): Add Optimize.
1065         * i386-opc.h (Optimize): New enum.
1066         (i386_opcode_modifier): Add optimize.
1067         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1068         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1069         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1070         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1071         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1072         vpxord and vpxorq.
1073         * i386-tbl.h: Regenerated.
1074
1075 2018-02-26  Alan Modra  <amodra@gmail.com>
1076
1077         * crx-dis.c (getregliststring): Allocate a large enough buffer
1078         to silence false positive gcc8 warning.
1079
1080 2018-02-22  Shea Levy <shea@shealevy.com>
1081
1082         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1083
1084 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1085
1086         * i386-opc.tbl: Add {rex},
1087         * i386-tbl.h: Regenerated.
1088
1089 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1090
1091         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1092         (mips16_opcodes): Replace `M' with `m' for "restore".
1093
1094 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1095
1096         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1097
1098 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1099
1100         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1101         variable to `function_index'.
1102
1103 2018-02-13  Nick Clifton  <nickc@redhat.com>
1104
1105         PR 22823
1106         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1107         about truncation of printing.
1108
1109 2018-02-12  Henry Wong <henry@stuffedcow.net>
1110
1111         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1112
1113 2018-02-05  Nick Clifton  <nickc@redhat.com>
1114
1115         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1116
1117 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1118
1119         * i386-dis.c (enum): Add pconfig.
1120         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1121         (cpu_flags): Add CpuPCONFIG.
1122         * i386-opc.h (enum): Add CpuPCONFIG.
1123         (i386_cpu_flags): Add cpupconfig.
1124         * i386-opc.tbl: Add PCONFIG instruction.
1125         * i386-init.h: Regenerate.
1126         * i386-tbl.h: Likewise.
1127
1128 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1129
1130         * i386-dis.c (enum): Add PREFIX_0F09.
1131         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1132         (cpu_flags): Add CpuWBNOINVD.
1133         * i386-opc.h (enum): Add CpuWBNOINVD.
1134         (i386_cpu_flags): Add cpuwbnoinvd.
1135         * i386-opc.tbl: Add WBNOINVD instruction.
1136         * i386-init.h: Regenerate.
1137         * i386-tbl.h: Likewise.
1138
1139 2018-01-17  Jim Wilson  <jimw@sifive.com>
1140
1141         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1142
1143 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1144
1145         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1146         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1147         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1148         (cpu_flags): Add CpuIBT, CpuSHSTK.
1149         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1150         (i386_cpu_flags): Add cpuibt, cpushstk.
1151         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1152         * i386-init.h: Regenerate.
1153         * i386-tbl.h: Likewise.
1154
1155 2018-01-16  Nick Clifton  <nickc@redhat.com>
1156
1157         * po/pt_BR.po: Updated Brazilian Portugese translation.
1158         * po/de.po: Updated German translation.
1159
1160 2018-01-15  Jim Wilson  <jimw@sifive.com>
1161
1162         * riscv-opc.c (match_c_nop): New.
1163         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1164
1165 2018-01-15  Nick Clifton  <nickc@redhat.com>
1166
1167         * po/uk.po: Updated Ukranian translation.
1168
1169 2018-01-13  Nick Clifton  <nickc@redhat.com>
1170
1171         * po/opcodes.pot: Regenerated.
1172
1173 2018-01-13  Nick Clifton  <nickc@redhat.com>
1174
1175         * configure: Regenerate.
1176
1177 2018-01-13  Nick Clifton  <nickc@redhat.com>
1178
1179         2.30 branch created.
1180
1181 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1182
1183         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1184         * i386-tbl.h: Regenerate.
1185
1186 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1187
1188         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1189         * i386-tbl.h: Re-generate.
1190
1191 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1192
1193         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1194         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1195         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1196         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1197         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1198         Disp8MemShift of AVX512VL forms.
1199         * i386-tbl.h: Re-generate.
1200
1201 2018-01-09  Jim Wilson  <jimw@sifive.com>
1202
1203         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1204         then the hi_addr value is zero.
1205
1206 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1207
1208         * arm-dis.c (arm_opcodes): Add csdb.
1209         (thumb32_opcodes): Add csdb.
1210
1211 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1212
1213         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1214         * aarch64-asm-2.c: Regenerate.
1215         * aarch64-dis-2.c: Regenerate.
1216         * aarch64-opc-2.c: Regenerate.
1217
1218 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1219
1220         PR gas/22681
1221         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1222         Remove AVX512 vmovd with 64-bit operands.
1223         * i386-tbl.h: Regenerated.
1224
1225 2018-01-05  Jim Wilson  <jimw@sifive.com>
1226
1227         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1228         jalr.
1229
1230 2018-01-03  Alan Modra  <amodra@gmail.com>
1231
1232         Update year range in copyright notice of all files.
1233
1234 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1235
1236         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1237         and OPERAND_TYPE_REGZMM entries.
1238
1239 For older changes see ChangeLog-2017
1240 \f
1241 Copyright (C) 2018 Free Software Foundation, Inc.
1242
1243 Copying and distribution of this file, with or without modification,
1244 are permitted in any medium without royalty provided the copyright
1245 notice and this notice are preserved.
1246
1247 Local Variables:
1248 mode: change-log
1249 left-margin: 8
1250 fill-column: 74
1251 version-control: never
1252 End: