opcodes/ChangeLog

   1 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
   2
   3         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
   4         descriptors.
   5         (parse_mips_ase_option): Handle -M loongson-cam option.
   6         (print_mips_disassembler_options): Document -M loongson-cam.
   7         * mips-opc.c (LCAM): New macro.
   8         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
   9         instructions.
  10
  11 2018-08-21  Alan Modra  <amodra@gmail.com>
  12
  13         * ppc-dis.c (operand_value_powerpc): Init "invalid".
  14         (skip_optional_operands): Count optional operands, and update
  15         ppc_optional_operand_value call.
  16         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
  17         (extract_vlensi): Likewise.
  18         (extract_fxm): Return default value for missing optional operand.
  19         (extract_ls, extract_raq, extract_tbr): Likewise.
  20         (insert_sxl, extract_sxl): New functions.
  21         (insert_esync, extract_esync): Remove Power9 handling and simplify.
  22         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
  23         flag and extra entry.
  24         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
  25         extract_sxl.
  26
  27 2018-08-20  Alan Modra  <amodra@gmail.com>
  28
  29         * sh-opc.h (MASK): Simplify.
  30
  31 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
  32
  33         * s12z-dis.c (bm_decode): Deal with cases where the mode is
  34         BM_RESERVED0 or BM_RESERVED1
  35         (bm_rel_decode, bm_n_bytes): Ditto.
  36
  37 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
  38
  39         * s12z.h: Delete.
  40
  41 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
  42
  43         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
  44         address with the addr32 prefix and without base nor index
  45         registers.
  46
  47 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
  50         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
  51         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
  52         (cpu_flags): Add CpuCMOV and CpuFXSR.
  53         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
  54         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
  55         * i386-init.h: Regenerated.
  56         * i386-tbl.h: Likewise.
  57
  58 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
  59
  60         * arc-regs.h: Update auxiliary registers.
  61
  62 2018-08-06  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
  65         (RegIP, RegIZ): Define.
  66         * i386-reg.tbl: Adjust comments.
  67         (rip): Use Qword instead of BaseIndex. Use RegIP.
  68         (eip): Use Dword instead of BaseIndex. Use RegIP.
  69         (riz): Add Qword. Use RegIZ.
  70         (eiz): Add Dword. Use RegIZ.
  71         * i386-tbl.h: Re-generate.
  72
  73 2018-08-03  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
  76         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
  77         vpmovzxdq, vpmovzxwd): Remove NoRex64.
  78         * i386-tbl.h: Re-generate.
  79
  80 2018-08-03  Jan Beulich  <jbeulich@suse.com>
  81
  82         * i386-gen.c (operand_types): Remove Mem field.
  83         * i386-opc.h (union i386_operand_type): Remove mem field.
  84         * i386-init.h, i386-tbl.h: Re-generate.
  85
  86 2018-08-01  Alan Modra  <amodra@gmail.com>
  87
  88         * po/POTFILES.in: Regenerate.
  89
  90 2018-07-31  Nick Clifton  <nickc@redhat.com>
  91
  92         * po/sv.po: Updated Swedish translation.
  93
  94 2018-07-31  Jan Beulich  <jbeulich@suse.com>
  95
  96         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
  97         * i386-init.h, i386-tbl.h: Re-generate.
  98
  99 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-opc.h (ZEROING_MASKING) Rename to ...
 102         (DYNAMIC_MASKING): ... this. Adjust comment.
 103         * i386-opc.tbl (MaskingMorZ): Define.
 104         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 105         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 106         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 107         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 108         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 109         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 110         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 111         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 112         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 113
 114 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 115
 116         * i386-opc.tbl: Use element rather than vector size for AVX512*
 117         scatter/gather insns.
 118         * i386-tbl.h: Re-generate.
 119
 120 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 123         (cpu_flags): Drop CpuVREX.
 124         * i386-opc.h (CpuVREX): Delete.
 125         (union i386_cpu_flags): Remove cpuvrex.
 126         * i386-init.h, i386-tbl.h: Re-generate.
 127
 128 2018-07-30  Jim Wilson  <jimw@sifive.com>
 129
 130         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 131         fields.
 132         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 133
 134 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 135
 136         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 137         * Makefile.in: Regenerated.
 138         * configure.ac: Add C-SKY.
 139         * configure: Regenerated.
 140         * csky-dis.c: New file.
 141         * csky-opc.h: New file.
 142         * disassemble.c (ARCH_csky): Define.
 143         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 144         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 145
 146 2018-07-27  Alan Modra  <amodra@gmail.com>
 147
 148         * ppc-opc.c (insert_sprbat): Correct function parameter and
 149         return type.
 150         (extract_sprbat): Likewise, variable too.
 151
 152 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 153             Alan Modra  <amodra@gmail.com>
 154
 155         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 156         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 157         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 158         support disjointed BAT.
 159         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 160         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 161         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 162
 163 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 164             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 165
 166         * i386-gen.c (adjust_broadcast_modifier): New function.
 167         (process_i386_opcode_modifier): Add an argument for operands.
 168         Adjust the Broadcast value based on operands.
 169         (output_i386_opcode): Pass operand_types to
 170         process_i386_opcode_modifier.
 171         (process_i386_opcodes): Pass NULL as operands to
 172         process_i386_opcode_modifier.
 173         * i386-opc.h (BYTE_BROADCAST): New.
 174         (WORD_BROADCAST): Likewise.
 175         (DWORD_BROADCAST): Likewise.
 176         (QWORD_BROADCAST): Likewise.
 177         (i386_opcode_modifier): Expand broadcast to 3 bits.
 178         * i386-tbl.h: Regenerated.
 179
 180 2018-07-24  Alan Modra  <amodra@gmail.com>
 181
 182         PR 23430
 183         * or1k-desc.h: Regenerate.
 184
 185 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 188         vcvtusi2ss, and vcvtusi2sd.
 189         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 190         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 191         * i386-tbl.h: Re-generate.
 192
 193 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 194
 195         * arc-opc.c (extract_w6): Fix extending the sign.
 196
 197 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 198
 199         * arc-tbl.h (vewt): Allow it for ARC EM family.
 200
 201 2018-07-23  Alan Modra  <amodra@gmail.com>
 202
 203         PR 23419
 204         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 205         opcode variants for mtspr/mfspr encodings.
 206
 207 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 208             Maciej W. Rozycki  <macro@mips.com>
 209
 210         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
 211         loongson3a descriptors.
 212         (parse_mips_ase_option): Handle -M loongson-mmi option.
 213         (print_mips_disassembler_options): Document -M loongson-mmi.
 214         * mips-opc.c (LMMI): New macro.
 215         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
 216         instructions.
 217
 218 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 219
 220         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 221         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
 222         IgnoreSize and [XYZ]MMword where applicable.
 223         * i386-tbl.h: Re-generate.
 224
 225 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
 228         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
 229         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
 230         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
 231         * i386-tbl.h: Re-generate.
 232
 233 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 236         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 237         VPCLMULQDQ templates into their respective AVX512VL counterparts
 238         where possible, using Disp8ShiftVL and CheckRegSize instead of
 239         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 240         * i386-tbl.h: Re-generate.
 241
 242 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 245         AVX512VL counterparts where possible, using Disp8ShiftVL and
 246         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 247         IgnoreSize) as appropriate.
 248         * i386-tbl.h: Re-generate.
 249
 250 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 251
 252         * i386-opc.tbl: Fold AVX512BW templates into their respective
 253         AVX512VL counterparts where possible, using Disp8ShiftVL and
 254         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 255         IgnoreSize) as appropriate.
 256         * i386-tbl.h: Re-generate.
 257
 258 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl: Fold AVX512CD templates into their respective
 261         AVX512VL counterparts where possible, using Disp8ShiftVL and
 262         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 263         IgnoreSize) as appropriate.
 264         * i386-tbl.h: Re-generate.
 265
 266 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-opc.h (DISP8_SHIFT_VL): New.
 269         * i386-opc.tbl (Disp8ShiftVL):  Define.
 270         (various): Fold AVX512VL templates into their respective
 271         AVX512F counterparts where possible, using Disp8ShiftVL and
 272         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 273         IgnoreSize) as appropriate.
 274         * i386-tbl.h: Re-generate.
 275
 276 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 277
 278         * Makefile.am: Change dependencies and rule for
 279         $(srcdir)/i386-init.h.
 280         * Makefile.in: Re-generate.
 281         * i386-gen.c (process_i386_opcodes): New local variable
 282         "marker". Drop opening of input file. Recognize marker and line
 283         number directives.
 284         * i386-opc.tbl (OPCODE_I386_H): Define.
 285         (i386-opc.h): Include it.
 286         (None): Undefine.
 287
 288 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 289
 290         PR gas/23418
 291         * i386-opc.h (Byte): Update comments.
 292         (Word): Likewise.
 293         (Dword): Likewise.
 294         (Fword): Likewise.
 295         (Qword): Likewise.
 296         (Tbyte): Likewise.
 297         (Xmmword): Likewise.
 298         (Ymmword): Likewise.
 299         (Zmmword): Likewise.
 300         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 301         vcvttps2uqq.
 302         * i386-tbl.h: Regenerated.
 303
 304 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 305
 306         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 307         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 308         * aarch64-asm-2.c: Regenerate.
 309         * aarch64-dis-2.c: Regenerate.
 310         * aarch64-opc-2.c: Regenerate.
 311
 312 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 313
 314         PR binutils/23192
 315         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 316         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 317         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 318         sqdmulh, sqrdmulh): Use Em16.
 319
 320 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 321
 322         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 323         csdb together with them.
 324         (thumb32_opcodes): Likewise.
 325
 326 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 329         requiring 32-bit registers as operands 2 and 3. Improve
 330         comments.
 331         (mwait, mwaitx): Fold templates. Improve comments.
 332         OPERAND_TYPE_INOUTPORTREG.
 333         * i386-tbl.h: Re-generate.
 334
 335 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 336
 337         * i386-gen.c (operand_type_init): Remove
 338         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 339         OPERAND_TYPE_INOUTPORTREG.
 340         * i386-init.h: Re-generate.
 341
 342 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 345         (wrssq, wrussq): Add Qword.
 346         * i386-tbl.h: Re-generate.
 347
 348 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-opc.h: Rename OTMax to OTNum.
 351         (OTNumOfUints): Adjust calculation.
 352         (OTUnused): Directly alias to OTNum.
 353
 354 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 355
 356         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 357         `reg_xys'.
 358         (lea_reg_xys): Likewise.
 359         (print_insn_loop_primitive): Rename `reg' local variable to
 360         `reg_dxy'.
 361
 362 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 363
 364         PR binutils/23242
 365         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 366
 367 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 368
 369         PR binutils/23369
 370         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 371         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 372
 373 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 374
 375         PR tdep/8282
 376         * mips-dis.c (mips_option_arg_t): New enumeration.
 377         (mips_options): New variable.
 378         (disassembler_options_mips): New function.
 379         (print_mips_disassembler_options): Reimplement in terms of
 380         `disassembler_options_mips'.
 381         * arm-dis.c (disassembler_options_arm): Adapt to using the
 382         `disasm_options_and_args_t' structure.
 383         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 384         * s390-dis.c (disassembler_options_s390): Likewise.
 385
 386 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 387
 388         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 389         expected result.
 390         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 391         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 392         * testsuite/ld-arm/tls-longplt.d: Likewise.
 393
 394 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 395
 396         PR binutils/23192
 397         * aarch64-asm-2.c: Regenerate.
 398         * aarch64-dis-2.c: Likewise.
 399         * aarch64-opc-2.c: Likewise.
 400         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 401         * aarch64-opc.c (operand_general_constraint_met_p,
 402         aarch64_print_operand): Likewise.
 403         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 404         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 405         fmlal2, fmlsl2.
 406         (AARCH64_OPERANDS): Add Em2.
 407
 408 2018-06-26  Nick Clifton  <nickc@redhat.com>
 409
 410         * po/uk.po: Updated Ukranian translation.
 411         * po/de.po: Updated German translation.
 412         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 413
 414 2018-06-26  Nick Clifton  <nickc@redhat.com>
 415
 416         * nfp-dis.c: Fix spelling mistake.
 417
 418 2018-06-24  Nick Clifton  <nickc@redhat.com>
 419
 420         * configure: Regenerate.
 421         * po/opcodes.pot: Regenerate.
 422
 423 2018-06-24  Nick Clifton  <nickc@redhat.com>
 424
 425         2.31 branch created.
 426
 427 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 428
 429         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 430         * aarch64-asm-2.c: Regenerate.
 431         * aarch64-dis-2.c: Likewise.
 432
 433 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 434
 435         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 436         `-M ginv' option description.
 437
 438 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 439
 440         PR gas/23305
 441         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 442         la and lla.
 443
 444 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 445
 446         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 447         * configure.ac: Remove AC_PREREQ.
 448         * Makefile.in: Re-generate.
 449         * aclocal.m4: Re-generate.
 450         * configure: Re-generate.
 451
 452 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 453
 454         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 455         mips64r6 descriptors.
 456         (parse_mips_ase_option): Handle -Mginv option.
 457         (print_mips_disassembler_options): Document -Mginv.
 458         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 459         (GINV): New macro.
 460         (mips_opcodes): Define ginvi and ginvt.
 461
 462 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 463             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 464
 465         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 466         * mips-opc.c (CRC, CRC64): New macros.
 467         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 468         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 469         crc32cd for CRC64.
 470
 471 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 472
 473         PR 20319
 474         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 475         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 476
 477 2018-06-06  Alan Modra  <amodra@gmail.com>
 478
 479         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 480         setjmp.  Move init for some other vars later too.
 481
 482 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 483
 484         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 485         (dis_private): Add new fields for property section tracking.
 486         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 487         (xtensa_instruction_fits): New functions.
 488         (fetch_data): Bump minimal fetch size to 4.
 489         (print_insn_xtensa): Make struct dis_private static.
 490         Load and prepare property table on section change.
 491         Don't disassemble literals. Don't disassemble instructions that
 492         cross property table boundaries.
 493
 494 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 495
 496         * configure: Regenerated.
 497
 498 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 501         * i386-tbl.h: Re-generate.
 502
 503 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 504
 505         * i386-opc.tbl (sldt, str): Add NoRex64.
 506         * i386-tbl.h: Re-generate.
 507
 508 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 509
 510         * i386-opc.tbl (invpcid): Add Oword.
 511         * i386-tbl.h: Re-generate.
 512
 513 2018-06-01  Alan Modra  <amodra@gmail.com>
 514
 515         * sysdep.h (_bfd_error_handler): Don't declare.
 516         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 517         * rl78-decode.opc: Likewise.
 518         * msp430-decode.c: Regenerate.
 519         * rl78-decode.c: Regenerate.
 520
 521 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 522
 523         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 524         * i386-init.h : Regenerated.
 525
 526 2018-05-25  Alan Modra  <amodra@gmail.com>
 527
 528         * Makefile.in: Regenerate.
 529         * po/POTFILES.in: Regenerate.
 530
 531 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 532
 533         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 534         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 535         (insert_bab, extract_bab, insert_btab, extract_btab,
 536         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 537         (BAT, BBA VBA RBS XB6S): Delete macros.
 538         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 539         (BB, BD, RBX, XC6): Update for new macros.
 540         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 541         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 542         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 543         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 544
 545 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 546
 547         * Makefile.am: Add support for s12z architecture.
 548         * configure.ac: Likewise.
 549         * disassemble.c: Likewise.
 550         * disassemble.h: Likewise.
 551         * Makefile.in: Regenerate.
 552         * configure: Regenerate.
 553         * s12z-dis.c: New file.
 554         * s12z.h: New file.
 555
 556 2018-05-18  Alan Modra  <amodra@gmail.com>
 557
 558         * nfp-dis.c: Don't #include libbfd.h.
 559         (init_nfp3200_priv): Use bfd_get_section_contents.
 560         (nit_nfp6000_mecsr_sec): Likewise.
 561
 562 2018-05-17  Nick Clifton  <nickc@redhat.com>
 563
 564         * po/zh_CN.po: Updated simplified Chinese translation.
 565
 566 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 567
 568         PR binutils/23109
 569         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 570         * aarch64-dis-2.c: Regenerate.
 571
 572 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 573
 574         PR binutils/21446
 575         * aarch64-asm.c (opintl.h): Include.
 576         (aarch64_ins_sysreg): Enforce read/write constraints.
 577         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 578         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 579         (F_REG_READ, F_REG_WRITE): New.
 580         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 581         AARCH64_OPND_SYSREG.
 582         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 583         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 584         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 585         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 586         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 587         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 588         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 589         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 590         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 591         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 592         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 593         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 594         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 595         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 596         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 597         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 598         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 599
 600 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 601
 602         PR binutils/21446
 603         * aarch64-dis.c (no_notes: New.
 604         (parse_aarch64_dis_option): Support notes.
 605         (aarch64_decode_insn, print_operands): Likewise.
 606         (print_aarch64_disassembler_options): Document notes.
 607         * aarch64-opc.c (aarch64_print_operand): Support notes.
 608
 609 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 610
 611         PR binutils/21446
 612         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 613         and take error struct.
 614         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 615         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 616         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 617         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 618         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 619         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 620         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 621         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 622         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 623         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 624         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 625         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 626         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 627         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 628         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 629         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 630         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 631         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 632         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 633         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 634         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 635         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 636         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 637         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 638         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 639         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 640         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 641         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 642         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 643         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 644         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 645         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 646         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 647         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 648         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 649         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 650         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 651         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 652         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 653         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 654         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 655         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 656         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 657         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 658         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 659         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 660         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 661         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 662         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 663         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 664         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 665         (determine_disassembling_preference, aarch64_decode_insn,
 666         print_insn_aarch64_word, print_insn_data): Take errors struct.
 667         (print_insn_aarch64): Use errors.
 668         * aarch64-asm-2.c: Regenerate.
 669         * aarch64-dis-2.c: Regenerate.
 670         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 671         boolean in aarch64_insert_operan.
 672         (print_operand_extractor): Likewise.
 673         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 674
 675 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 676
 677         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 678
 679 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 682
 683 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 684
 685         * cr16-opc.c (cr16_instruction): Comment typo fix.
 686         * hppa-dis.c (print_insn_hppa): Likewise.
 687
 688 2018-05-08  Jim Wilson  <jimw@sifive.com>
 689
 690         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 691         (match_c_slli64, match_srxi_as_c_srxi): New.
 692         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 693         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 694         <c.slli, c.srli, c.srai>: Use match_s_slli.
 695         <c.slli64, c.srli64, c.srai64>: New.
 696
 697 2018-05-08  Alan Modra  <amodra@gmail.com>
 698
 699         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 700         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 701         partition opcode space for index lookup.
 702
 703 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 704
 705         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 706         <insn_length>: ...with this.  Update usage.
 707         Remove duplicate call to *info->memory_error_func.
 708
 709 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 710             H.J. Lu  <hongjiu.lu@intel.com>
 711
 712         * i386-dis.c (Gva): New.
 713         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 714         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 715         (prefix_table): New instructions (see prefix above).
 716         (mod_table): New instructions (see prefix above).
 717         (OP_G): Handle va_mode.
 718         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 719         CPU_MOVDIR64B_FLAGS.
 720         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 721         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 722         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 723         * i386-opc.tbl: Add movidir{i,64b}.
 724         * i386-init.h: Regenerated.
 725         * i386-tbl.h: Likewise.
 726
 727 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 728
 729         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 730         AddrPrefixOpReg.
 731         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 732         (AddrPrefixOpReg): This.
 733         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 734         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 735
 736 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 737
 738         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 739         (vle_num_opcodes): Likewise.
 740         (spe2_num_opcodes): Likewise.
 741         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 742         initialization loop.
 743         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 744         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 745         only once.
 746
 747 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 748
 749         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 750
 751 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 752
 753         Makefile.am: Added nfp-dis.c.
 754         configure.ac: Added bfd_nfp_arch.
 755         disassemble.h: Added print_insn_nfp prototype.
 756         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 757         nfp-dis.c: New, for NFP support.
 758         po/POTFILES.in: Added nfp-dis.c to the list.
 759         Makefile.in: Regenerate.
 760         configure: Regenerate.
 761
 762 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 763
 764         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 765         templates into their base ones.
 766         * i386-tlb.h: Re-generate.
 767
 768 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 769
 770         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 771         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 772         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 773         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 774         * i386-init.h: Re-generate.
 775
 776 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 779         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 780         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 781         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 782         comment.
 783         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 784         and CpuRegMask.
 785         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 786         CpuRegMask: Delete.
 787         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 788         cpuregzmm, and cpuregmask.
 789         * i386-init.h: Re-generate.
 790         * i386-tbl.h: Re-generate.
 791
 792 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 793
 794         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 795         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 796         * i386-init.h: Re-generate.
 797
 798 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 799
 800         * i386-gen.c (VexImmExt): Delete.
 801         * i386-opc.h (VexImmExt, veximmext): Delete.
 802         * i386-opc.tbl: Drop all VexImmExt uses.
 803         * i386-tlb.h: Re-generate.
 804
 805 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 808         register-only forms.
 809         * i386-tlb.h: Re-generate.
 810
 811 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 812
 813         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 814
 815 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 816
 817         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 818         PREFIX_0F1C.
 819         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 820         (cpu_flags): Add CpuCLDEMOTE.
 821         * i386-init.h: Regenerate.
 822         * i386-opc.h (enum): Add CpuCLDEMOTE,
 823         (i386_cpu_flags): Add cpucldemote.
 824         * i386-opc.tbl: Add cldemote.
 825         * i386-tbl.h: Regenerate.
 826
 827 2018-04-16  Alan Modra  <amodra@gmail.com>
 828
 829         * Makefile.am: Remove sh5 and sh64 support.
 830         * configure.ac: Likewise.
 831         * disassemble.c: Likewise.
 832         * disassemble.h: Likewise.
 833         * sh-dis.c: Likewise.
 834         * sh64-dis.c: Delete.
 835         * sh64-opc.c: Delete.
 836         * sh64-opc.h: Delete.
 837         * Makefile.in: Regenerate.
 838         * configure: Regenerate.
 839         * po/POTFILES.in: Regenerate.
 840
 841 2018-04-16  Alan Modra  <amodra@gmail.com>
 842
 843         * Makefile.am: Remove w65 support.
 844         * configure.ac: Likewise.
 845         * disassemble.c: Likewise.
 846         * disassemble.h: Likewise.
 847         * w65-dis.c: Delete.
 848         * w65-opc.h: Delete.
 849         * Makefile.in: Regenerate.
 850         * configure: Regenerate.
 851         * po/POTFILES.in: Regenerate.
 852
 853 2018-04-16  Alan Modra  <amodra@gmail.com>
 854
 855         * configure.ac: Remove we32k support.
 856         * configure: Regenerate.
 857
 858 2018-04-16  Alan Modra  <amodra@gmail.com>
 859
 860         * Makefile.am: Remove m88k support.
 861         * configure.ac: Likewise.
 862         * disassemble.c: Likewise.
 863         * disassemble.h: Likewise.
 864         * m88k-dis.c: Delete.
 865         * Makefile.in: Regenerate.
 866         * configure: Regenerate.
 867         * po/POTFILES.in: Regenerate.
 868
 869 2018-04-16  Alan Modra  <amodra@gmail.com>
 870
 871         * Makefile.am: Remove i370 support.
 872         * configure.ac: Likewise.
 873         * disassemble.c: Likewise.
 874         * disassemble.h: Likewise.
 875         * i370-dis.c: Delete.
 876         * i370-opc.c: Delete.
 877         * Makefile.in: Regenerate.
 878         * configure: Regenerate.
 879         * po/POTFILES.in: Regenerate.
 880
 881 2018-04-16  Alan Modra  <amodra@gmail.com>
 882
 883         * Makefile.am: Remove h8500 support.
 884         * configure.ac: Likewise.
 885         * disassemble.c: Likewise.
 886         * disassemble.h: Likewise.
 887         * h8500-dis.c: Delete.
 888         * h8500-opc.h: Delete.
 889         * Makefile.in: Regenerate.
 890         * configure: Regenerate.
 891         * po/POTFILES.in: Regenerate.
 892
 893 2018-04-16  Alan Modra  <amodra@gmail.com>
 894
 895         * configure.ac: Remove tahoe support.
 896         * configure: Regenerate.
 897
 898 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 901         umwait.
 902         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 903         64-bit mode.
 904         * i386-tbl.h: Regenerated.
 905
 906 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 907
 908         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 909         PREFIX_MOD_1_0FAE_REG_6.
 910         (va_mode): New.
 911         (OP_E_register): Use va_mode.
 912         * i386-dis-evex.h (prefix_table):
 913         New instructions (see prefixes above).
 914         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 915         (cpu_flags): Likewise.
 916         * i386-opc.h (enum): Likewise.
 917         (i386_cpu_flags): Likewise.
 918         * i386-opc.tbl: Add umonitor, umwait, tpause.
 919         * i386-init.h: Regenerate.
 920         * i386-tbl.h: Likewise.
 921
 922 2018-04-11  Alan Modra  <amodra@gmail.com>
 923
 924         * opcodes/i860-dis.c: Delete.
 925         * opcodes/i960-dis.c: Delete.
 926         * Makefile.am: Remove i860 and i960 support.
 927         * configure.ac: Likewise.
 928         * disassemble.c: Likewise.
 929         * disassemble.h: Likewise.
 930         * Makefile.in: Regenerate.
 931         * configure: Regenerate.
 932         * po/POTFILES.in: Regenerate.
 933
 934 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 935
 936         PR binutils/23025
 937         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 938         to 0.
 939         (print_insn): Clear vex instead of vex.evex.
 940
 941 2018-04-04  Nick Clifton  <nickc@redhat.com>
 942
 943         * po/es.po: Updated Spanish translation.
 944
 945 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 946
 947         * i386-gen.c (opcode_modifiers): Delete VecESize.
 948         * i386-opc.h (VecESize): Delete.
 949         (struct i386_opcode_modifier): Delete vecesize.
 950         * i386-opc.tbl: Drop VecESize.
 951         * i386-tlb.h: Re-generate.
 952
 953 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 954
 955         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 956         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 957         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 958         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 959         * i386-tlb.h: Re-generate.
 960
 961 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 962
 963         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 964         Fold AVX512 forms
 965         * i386-tlb.h: Re-generate.
 966
 967 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 968
 969         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 970         (vex_len_table): Drop Y for vcvt*2si.
 971         (putop): Replace plain 'Y' handling by abort().
 972
 973 2018-03-28  Nick Clifton  <nickc@redhat.com>
 974
 975         PR 22988
 976         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 977         instructions with only a base address register.
 978         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 979         handle AARHC64_OPND_SVE_ADDR_R.
 980         (aarch64_print_operand): Likewise.
 981         * aarch64-asm-2.c: Regenerate.
 982         * aarch64_dis-2.c: Regenerate.
 983         * aarch64-opc-2.c: Regenerate.
 984
 985 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 986
 987         * i386-opc.tbl: Drop VecESize from register only insn forms and
 988         memory forms not allowing broadcast.
 989         * i386-tlb.h: Re-generate.
 990
 991 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 992
 993         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 994         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 995         sha256*): Drop Disp<N>.
 996
 997 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 998
 999         * i386-dis.c (EbndS, bnd_swap_mode): New.
1000         (prefix_table): Use EbndS.
1001         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1002         * i386-opc.tbl (bndmov): Move misplaced Load.
1003         * i386-tlb.h: Re-generate.
1004
1005 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1006
1007         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1008         templates allowing memory operands and folded ones for register
1009         only flavors.
1010         * i386-tlb.h: Re-generate.
1011
1012 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1013
1014         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1015         256-bit templates. Drop redundant leftover Disp<N>.
1016         * i386-tlb.h: Re-generate.
1017
1018 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1019
1020         * riscv-opc.c (riscv_insn_types): New.
1021
1022 2018-03-13  Nick Clifton  <nickc@redhat.com>
1023
1024         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1025
1026 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1027
1028         * i386-opc.tbl: Add Optimize to clr.
1029         * i386-tbl.h: Regenerated.
1030
1031 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1032
1033         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1034         * i386-opc.h (OldGcc): Removed.
1035         (i386_opcode_modifier): Remove oldgcc.
1036         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1037         instructions for old (<= 2.8.1) versions of gcc.
1038         * i386-tbl.h: Regenerated.
1039
1040 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1041
1042         * i386-opc.h (EVEXDYN): New.
1043         * i386-opc.tbl: Fold various AVX512VL templates.
1044         * i386-tlb.h: Re-generate.
1045
1046 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1047
1048         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1049         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1050         vpexpandd, vpexpandq): Fold AFX512VF templates.
1051         * i386-tlb.h: Re-generate.
1052
1053 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1054
1055         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1056         Fold 128- and 256-bit VEX-encoded templates.
1057         * i386-tlb.h: Re-generate.
1058
1059 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1060
1061         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1062         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1063         vpexpandd, vpexpandq): Fold AVX512F templates.
1064         * i386-tlb.h: Re-generate.
1065
1066 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1069         64-bit templates. Drop Disp<N>.
1070         * i386-tlb.h: Re-generate.
1071
1072 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1075         and 256-bit templates.
1076         * i386-tlb.h: Re-generate.
1077
1078 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1079
1080         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1081         * i386-tlb.h: Re-generate.
1082
1083 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1084
1085         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1086         Drop NoAVX.
1087         * i386-tlb.h: Re-generate.
1088
1089 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1090
1091         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1092         * i386-tlb.h: Re-generate.
1093
1094 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-gen.c (opcode_modifiers): Delete FloatD.
1097         * i386-opc.h (FloatD): Delete.
1098         (struct i386_opcode_modifier): Delete floatd.
1099         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1100         FloatD by D.
1101         * i386-tlb.h: Re-generate.
1102
1103 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1104
1105         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1106
1107 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1108
1109         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1110         * i386-tlb.h: Re-generate.
1111
1112 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1113
1114         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1115         forms.
1116         * i386-tlb.h: Re-generate.
1117
1118 2018-03-07  Alan Modra  <amodra@gmail.com>
1119
1120         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1121         bfd_arch_rs6000.
1122         * disassemble.h (print_insn_rs6000): Delete.
1123         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1124         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1125         (print_insn_rs6000): Delete.
1126
1127 2018-03-03  Alan Modra  <amodra@gmail.com>
1128
1129         * sysdep.h (opcodes_error_handler): Define.
1130         (_bfd_error_handler): Declare.
1131         * Makefile.am: Remove stray #.
1132         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1133         EDIT" comment.
1134         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1135         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1136         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1137         opcodes_error_handler to print errors.  Standardize error messages.
1138         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1139         and include opintl.h.
1140         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1141         * i386-gen.c: Standardize error messages.
1142         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1143         * Makefile.in: Regenerate.
1144         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1145         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1146         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1147         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1148         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1149         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1150         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1151         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1152         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1153         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1154         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1155         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1156         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1157
1158 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1159
1160         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1161         vpsub[bwdq] instructions.
1162         * i386-tbl.h: Regenerated.
1163
1164 2018-03-01  Alan Modra  <amodra@gmail.com>
1165
1166         * configure.ac (ALL_LINGUAS): Sort.
1167         * configure: Regenerate.
1168
1169 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1170
1171         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1172         macro by assignements.
1173
1174 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1175
1176         PR gas/22871
1177         * i386-gen.c (opcode_modifiers): Add Optimize.
1178         * i386-opc.h (Optimize): New enum.
1179         (i386_opcode_modifier): Add optimize.
1180         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1181         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1182         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1183         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1184         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1185         vpxord and vpxorq.
1186         * i386-tbl.h: Regenerated.
1187
1188 2018-02-26  Alan Modra  <amodra@gmail.com>
1189
1190         * crx-dis.c (getregliststring): Allocate a large enough buffer
1191         to silence false positive gcc8 warning.
1192
1193 2018-02-22  Shea Levy <shea@shealevy.com>
1194
1195         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1196
1197 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1198
1199         * i386-opc.tbl: Add {rex},
1200         * i386-tbl.h: Regenerated.
1201
1202 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1203
1204         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1205         (mips16_opcodes): Replace `M' with `m' for "restore".
1206
1207 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1208
1209         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1210
1211 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1212
1213         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1214         variable to `function_index'.
1215
1216 2018-02-13  Nick Clifton  <nickc@redhat.com>
1217
1218         PR 22823
1219         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1220         about truncation of printing.
1221
1222 2018-02-12  Henry Wong <henry@stuffedcow.net>
1223
1224         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1225
1226 2018-02-05  Nick Clifton  <nickc@redhat.com>
1227
1228         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1229
1230 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1231
1232         * i386-dis.c (enum): Add pconfig.
1233         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1234         (cpu_flags): Add CpuPCONFIG.
1235         * i386-opc.h (enum): Add CpuPCONFIG.
1236         (i386_cpu_flags): Add cpupconfig.
1237         * i386-opc.tbl: Add PCONFIG instruction.
1238         * i386-init.h: Regenerate.
1239         * i386-tbl.h: Likewise.
1240
1241 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1242
1243         * i386-dis.c (enum): Add PREFIX_0F09.
1244         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1245         (cpu_flags): Add CpuWBNOINVD.
1246         * i386-opc.h (enum): Add CpuWBNOINVD.
1247         (i386_cpu_flags): Add cpuwbnoinvd.
1248         * i386-opc.tbl: Add WBNOINVD instruction.
1249         * i386-init.h: Regenerate.
1250         * i386-tbl.h: Likewise.
1251
1252 2018-01-17  Jim Wilson  <jimw@sifive.com>
1253
1254         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1255
1256 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1257
1258         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1259         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1260         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1261         (cpu_flags): Add CpuIBT, CpuSHSTK.
1262         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1263         (i386_cpu_flags): Add cpuibt, cpushstk.
1264         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1265         * i386-init.h: Regenerate.
1266         * i386-tbl.h: Likewise.
1267
1268 2018-01-16  Nick Clifton  <nickc@redhat.com>
1269
1270         * po/pt_BR.po: Updated Brazilian Portugese translation.
1271         * po/de.po: Updated German translation.
1272
1273 2018-01-15  Jim Wilson  <jimw@sifive.com>
1274
1275         * riscv-opc.c (match_c_nop): New.
1276         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1277
1278 2018-01-15  Nick Clifton  <nickc@redhat.com>
1279
1280         * po/uk.po: Updated Ukranian translation.
1281
1282 2018-01-13  Nick Clifton  <nickc@redhat.com>
1283
1284         * po/opcodes.pot: Regenerated.
1285
1286 2018-01-13  Nick Clifton  <nickc@redhat.com>
1287
1288         * configure: Regenerate.
1289
1290 2018-01-13  Nick Clifton  <nickc@redhat.com>
1291
1292         2.30 branch created.
1293
1294 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1295
1296         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1297         * i386-tbl.h: Regenerate.
1298
1299 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1300
1301         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1302         * i386-tbl.h: Re-generate.
1303
1304 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1305
1306         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1307         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1308         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1309         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1310         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1311         Disp8MemShift of AVX512VL forms.
1312         * i386-tbl.h: Re-generate.
1313
1314 2018-01-09  Jim Wilson  <jimw@sifive.com>
1315
1316         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1317         then the hi_addr value is zero.
1318
1319 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1320
1321         * arm-dis.c (arm_opcodes): Add csdb.
1322         (thumb32_opcodes): Add csdb.
1323
1324 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1325
1326         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1327         * aarch64-asm-2.c: Regenerate.
1328         * aarch64-dis-2.c: Regenerate.
1329         * aarch64-opc-2.c: Regenerate.
1330
1331 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1332
1333         PR gas/22681
1334         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1335         Remove AVX512 vmovd with 64-bit operands.
1336         * i386-tbl.h: Regenerated.
1337
1338 2018-01-05  Jim Wilson  <jimw@sifive.com>
1339
1340         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1341         jalr.
1342
1343 2018-01-03  Alan Modra  <amodra@gmail.com>
1344
1345         Update year range in copyright notice of all files.
1346
1347 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1348
1349         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1350         and OPERAND_TYPE_REGZMM entries.
1351
1352 For older changes see ChangeLog-2017
1353 \f
1354 Copyright (C) 2018 Free Software Foundation, Inc.
1355
1356 Copying and distribution of this file, with or without modification,
1357 are permitted in any medium without royalty provided the copyright
1358 notice and this notice are preserved.
1359
1360 Local Variables:
1361 mode: change-log
1362 left-margin: 8
1363 fill-column: 74
1364 version-control: never
1365 End: