opcodes/ChangeLog

   1 2023-03-15  Nick Clifton  <nickc@redhat.com>
   2
   3         PR 30231
   4         * mep-dis.c: Regenerate.
   5
   6 2023-03-15  Nick Clifton  <nickc@redhat.com>
   7
   8         PR 30230
   9         * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
  10
  11 2023-02-28  Richard Ball  <richard.ball@arm.com>
  12
  13         * aarch64-opc.c: Add MEC system registers.
  14
  15 2023-01-03  Nick Clifton  <nickc@redhat.com>
  16
  17         * po/de.po: Updated German translation.
  18         * po/ro.po: Updated Romainian translation.
  19         * po/uk.po: Updated Ukrainian translation.
  20
  21 2022-12-31  Nick Clifton  <nickc@redhat.com>
  22
  23         * 2.40 branch created.
  24
  25 2022-11-22  Shahab Vahedi  <shahab@synopsys.com>
  26
  27         * arc-regs.h: Change isa_config address to 0xc1.
  28         isa_config exists for ARC700 and ARCV2 and not ARCALL.
  29
  30 2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
  31
  32         * rx-decode.opc: Switch arguments of the MVTACGU insn.
  33         * rx-decode.c: Regenerate.
  34
  35 2022-09-22  Yoshinori Sato  <ysato@users.sourceforge.jp>
  36
  37         * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
  38         Rm_BANK,Rn is always 1.
  39
  40 2022-07-21  Peter Bergner  <bergner@linux.ibm.com>
  41
  42         * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
  43         (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
  44         xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
  45         xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
  46         xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
  47         xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
  48         xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
  49
  50 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
  51
  52         * disassemble.c (disassemble_init_for_target): Set
  53         created_styled_output for ARC based targets.
  54         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
  55         instead of fprintf_ftype throughout.
  56         (find_format): Likewise.
  57         (print_flags): Likewise.
  58         (print_insn_arc): Likewise.
  59
  60 2022-07-08  Nick Clifton  <nickc@redhat.com>
  61
  62         * 2.39 branch created.
  63
  64 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
  65
  66         * disassemble.c: (disassemble_init_for_target): Set
  67         created_styled_output for AVR based targets.
  68         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
  69         instead of fprintf_ftype throughout.
  70         (avr_operand): Pass in and fill disassembler_style when
  71         parsing operands.
  72
  73 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  74
  75         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
  76         table.
  77
  78 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
  79
  80         * configure.ac: Handle bfd_amdgcn_arch.
  81         * configure: Re-generate.
  82
  83 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
  84             Maciej W. Rozycki  <macro@orcam.me.uk>
  85
  86         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
  87         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
  88         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
  89         "bnez" instructions.
  90
  91 2022-02-17  Nick Clifton  <nickc@redhat.com>
  92
  93         * po/sr.po: Updated Serbian translation.
  94
  95 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
  96
  97         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
  98         * microblaze-opc.h: Follow 'fsqrt' rename.
  99
 100 2022-01-24  Nick Clifton  <nickc@redhat.com>
 101
 102         * po/ro.po: Updated Romanian translation.
 103         * po/uk.po: Updated Ukranian translation.
 104
 105 2022-01-22  Nick Clifton  <nickc@redhat.com>
 106
 107         * configure: Regenerate.
 108         * po/opcodes.pot: Regenerate.
 109
 110 2022-01-22  Nick Clifton  <nickc@redhat.com>
 111
 112         * 2.38 release branch created.
 113
 114 2022-01-17  Nick Clifton  <nickc@redhat.com>
 115
 116         * Makefile.in: Regenerate.
 117         * po/opcodes.pot: Regenerate.
 118
 119 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
 120
 121         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
 122         in insn_type on branching instructions.
 123
 124 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
 125             Simon Cook  <simon.cook@embecosm.com>
 126
 127         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
 128         (riscv_options): New static global.
 129         (disassembler_options_riscv): New function.
 130         (print_riscv_disassembler_options): Rewrite to use
 131         disassembler_options_riscv.
 132
 133 2021-11-25  Nick Clifton  <nickc@redhat.com>
 134
 135         PR 28614
 136         * aarch64-asm.c: Replace assert(0) with real code.
 137         * aarch64-dis.c: Likewise.
 138         * aarch64-opc.c: Likewise.
 139
 140 2021-11-25  Nick Clifton  <nickc@redhat.com>
 141
 142         * po/fr.po; Updated French translation.
 143
 144 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
 145
 146         * Makefile.am: Remove obsolete comment.
 147         * configure.ac: Refer `libbfd.la' to link shared BFD library
 148         except for Cygwin.
 149         * Makefile.in: Regenerate.
 150         * configure: Regenerate.
 151
 152 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 153
 154         * configure: Regenerate.
 155
 156 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 157
 158         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 159         on POWER5 and later.
 160
 161 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 162
 163         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 164         before an unknown instruction, '%d' is replaced with the
 165         instruction length.
 166
 167 2021-09-02  Nick Clifton  <nickc@redhat.com>
 168
 169         PR 28292
 170         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 171         of BFD_RELOC_16.
 172
 173 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 174
 175         * arc-regs.h (DEF): Fix the register numbers.
 176
 177 2021-08-10  Nick Clifton  <nickc@redhat.com>
 178
 179         * po/sr.po: Updated Serbian translation.
 180
 181 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 182
 183         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 184
 185 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 186
 187         * s390-opc.txt: Add qpaci.
 188
 189 2021-07-03  Nick Clifton  <nickc@redhat.com>
 190
 191         * configure: Regenerate.
 192         * po/opcodes.pot: Regenerate.
 193
 194 2021-07-03  Nick Clifton  <nickc@redhat.com>
 195
 196         * 2.37 release branch created.
 197
 198 2021-07-02  Alan Modra  <amodra@gmail.com>
 199
 200         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 201         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 202         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 203         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 204         (nds32_keyword_gpr): Move declarations to..
 205         * nds32-asm.h: ..here, constifying to match definitions.
 206
 207 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 208
 209         * Makefile.am (GUILE): New variable.
 210         (CGEN): Use $(GUILE).
 211         * Makefile.in: Regenerate.
 212
 213 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 214
 215         * mep-asm.c (macros): Mark static & const.
 216         (lookup_macro): Change return & m to const.
 217         (expand_macro): Change mac to const.
 218         (expand_string): Change pmacro to const.
 219
 220 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 221
 222         * nds32-asm.c (operand_fields): Rename to ...
 223         (nds32_operand_fields): ... this.
 224         (keyword_gpr): Rename to ...
 225         (nds32_keyword_gpr): ... this.
 226         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 227         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 228         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 229         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 230         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 231         Mark static.
 232         (keywords): Rename to ...
 233         (nds32_keywords): ... this.
 234         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 235         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 236
 237 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 238
 239         * z80-dis.c (opc_ed): Make const.
 240         (pref_ed): Make p const.
 241
 242 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 243
 244         * microblaze-dis.c (get_field_special): Make op const.
 245         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 246         microblaze_opcodes.
 247         (print_insn_microblaze): Make op & pop const.
 248         (get_insn_microblaze): Make op const.  Rename opcodes to
 249         microblaze_opcodes.
 250         (microblaze_get_target_address): Likewise.
 251         * microblaze-opc.h (struct op_code_struct): Make const.
 252         Rename opcodes to microblaze_opcodes.
 253
 254 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 255
 256         * aarch64-gen.c (aarch64_opcode_table): Add const.
 257         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 258
 259 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 260
 261         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 262         available.
 263
 264 2021-06-22  Alan Modra  <amodra@gmail.com>
 265
 266         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 267         print separator for pcrel insns.
 268
 269 2021-06-19  Alan Modra  <amodra@gmail.com>
 270
 271         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 272
 273 2021-06-19  Alan Modra  <amodra@gmail.com>
 274
 275         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 276         entire buffer.
 277
 278 2021-06-17  Alan Modra  <amodra@gmail.com>
 279
 280         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 281         in table.
 282
 283 2021-06-03  Alan Modra  <amodra@gmail.com>
 284
 285         PR 1202
 286         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 287         Use unsigned int for inst.
 288
 289 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 290
 291         * arc-dis.c (arc_option_arg_t): New enumeration.
 292         (arc_options): New variable.
 293         (disassembler_options_arc): New function.
 294         (print_arc_disassembler_options): Reimplement in terms of
 295         "disassembler_options_arc".
 296
 297 2021-05-29  Alan Modra  <amodra@gmail.com>
 298
 299         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 300         Don't special case PPC_OPCODE_RAW.
 301         (lookup_prefix): Likewise.
 302         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 303         (print_insn_powerpc): ..update caller.
 304         * ppc-opc.c (EXT): Define.
 305         (powerpc_opcodes): Mark extended mnemonics with EXT.
 306         (prefix_opcodes, vle_opcodes): Likewise.
 307         (XISEL, XISEL_MASK): Add cr field and simplify.
 308         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 309         all isel variants to where the base mnemonic belongs.  Sort dstt,
 310         dststt and dssall.
 311
 312 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 313
 314         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 315         COP3 opcode instructions.
 316
 317 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 318
 319         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 320         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 321         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 322         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 323         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 324         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 325         "cop2", and "cop3" entries.
 326
 327 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 328
 329         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 330         entries and associated comments.
 331
 332 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 333
 334         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 335         of "c0".
 336
 337 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 338
 339         * mips-dis.c (mips_cp1_names_mips): New variable.
 340         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 341         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 342         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 343         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 344         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 345         "loongson2f".
 346
 347 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 348
 349         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 350         handling code over to...
 351         <OP_REG_CONTROL>: ... this new case.
 352         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 353         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 354         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 355         replacing the `G' operand code with `g'.  Update "cftc1" and
 356         "cftc2" entries replacing the `E' operand code with `y'.
 357         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 358         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 359         entries replacing the `G' operand code with `g'.
 360
 361 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 362
 363         * mips-dis.c (mips_cp0_names_r3900): New variable.
 364         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 365         for "r3900".
 366
 367 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 368
 369         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 370         and "mtthc2" to using the `G' rather than `g' operand code for
 371         the coprocessor control register referred.
 372
 373 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 374
 375         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 376         entries with each other.
 377
 378 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 379
 380         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 381
 382 2021-05-25  Alan Modra  <amodra@gmail.com>
 383
 384         * cris-desc.c: Regenerate.
 385         * cris-desc.h: Regenerate.
 386         * cris-opc.h: Regenerate.
 387         * po/POTFILES.in: Regenerate.
 388
 389 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 390
 391         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 392         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 393         (CGEN_CPUS): Add cris.
 394         (CRIS_DEPS): Define.
 395         (stamp-cris): New rule.
 396         * cgen.sh: Handle desc action.
 397         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 398         * Makefile.in, configure: Regenerate.
 399
 400 2021-05-18  Job Noorman  <mtvec@pm.me>
 401
 402         PR 27814
 403         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 404         the elf objects.
 405
 406 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 407
 408         * arm-dis.c (mve_opcodes): Fix disassembly of
 409         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 410         (is_mve_encoding_conflict): MVE vector loads should not match
 411         when P = W = 0.
 412         (is_mve_unpredictable): It's not unpredictable to use the same
 413         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 414
 415 2021-05-11  Nick Clifton  <nickc@redhat.com>
 416
 417         PR 27840
 418         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 419         the end of the code buffer.
 420
 421 2021-05-06  Stafford Horne  <shorne@gmail.com>
 422
 423         PR 21464
 424         * or1k-asm.c: Regenerate.
 425
 426 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 427
 428         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 429         info->insn_info_valid.
 430
 431 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-opc.tbl (lea): Add Optimize.
 434         * opcodes/i386-tbl.h: Re-generate.
 435
 436 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 437
 438         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 439         of l32r fetch and display referenced literal value.
 440
 441 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 442
 443         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 444         to 4 for literal disassembly.
 445
 446 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 447
 448         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 449         for TLBI instruction.
 450
 451 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 452
 453         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 454         DC instruction.
 455
 456 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 457
 458         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 459         "qualifier".
 460         (convert_mov_to_movewide): Add initializer for "value".
 461
 462 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 463
 464         * aarch64-opc.c: Add RME system registers.
 465
 466 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 467
 468         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 469         "addi d,CV,z" to "c.mv d,CV".
 470
 471 2021-04-12  Alan Modra  <amodra@gmail.com>
 472
 473         * configure.ac (--enable-checking): Add support.
 474         * config.in: Regenerate.
 475         * configure: Regenerate.
 476
 477 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 478
 479         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 480         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 481
 482 2021-04-09  Alan Modra  <amodra@gmail.com>
 483
 484         * ppc-dis.c (struct dis_private): Add "special".
 485         (POWERPC_DIALECT): Delete.  Replace uses with..
 486         (private_data): ..this.  New inline function.
 487         (disassemble_init_powerpc): Init "special" names.
 488         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 489         field of prefix instructions.
 490         (bsearch_reloc, print_got_plt): New functions.
 491         (print_insn_powerpc): For pcrel instructions, print target address
 492         and symbol if known, and decode plt and got loads too.
 493
 494 2021-04-08  Alan Modra  <amodra@gmail.com>
 495
 496         PR 27684
 497         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 498
 499 2021-04-08  Alan Modra  <amodra@gmail.com>
 500
 501         PR 27676
 502         * ppc-opc.c (DCBT_EO): Move earlier.
 503         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 504         (powerpc_operands): Add THCT and THDS entries.
 505         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 506
 507 2021-04-06  Alan Modra  <amodra@gmail.com>
 508
 509         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 510         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 511         symbol_at_address_func.
 512
 513 2021-04-05  Alan Modra  <amodra@gmail.com>
 514
 515         * configure.ac: Don't check for limits.h, string.h, strings.h or
 516         stdlib.h.
 517         (AC_ISC_POSIX): Don't invoke.
 518         * sysdep.h: Include stdlib.h and string.h unconditionally.
 519         * i386-opc.h: Include limits.h unconditionally.
 520         * wasm32-dis.c: Likewise.
 521         * cgen-opc.c: Don't include alloca-conf.h.
 522         * config.in: Regenerate.
 523         * configure: Regenerate.
 524
 525 2021-04-01  Martin Liska  <mliska@suse.cz>
 526
 527         * arm-dis.c (strneq): Remove strneq and use startswith.
 528         * cr16-dis.c (print_insn_cr16): Likewise.
 529         * score-dis.c (streq): Likewise.
 530         (strneq): Likewise.
 531         * score7-dis.c (strneq): Likewise.
 532
 533 2021-04-01  Alan Modra  <amodra@gmail.com>
 534
 535         PR 27675
 536         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 537
 538 2021-03-31  Alan Modra  <amodra@gmail.com>
 539
 540         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 541         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 542         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 543         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 544         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 545         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 546         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 547         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 548         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 549         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 550         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 551         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 552         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 553         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 554         and TRUE with true throughout.
 555
 556 2021-03-31  Alan Modra  <amodra@gmail.com>
 557
 558         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 559         * aarch64-dis.h: Likewise.
 560         * aarch64-opc.c: Likewise.
 561         * avr-dis.c: Likewise.
 562         * csky-dis.c: Likewise.
 563         * nds32-asm.c: Likewise.
 564         * nds32-dis.c: Likewise.
 565         * nfp-dis.c: Likewise.
 566         * riscv-dis.c: Likewise.
 567         * s12z-dis.c: Likewise.
 568         * wasm32-dis.c: Likewise.
 569
 570 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 573         (i386_seg_prefixes): New.
 574         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 575         (i386_seg_prefixes): Declare.
 576
 577 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 578
 579         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 580
 581 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 582
 583         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 584         * i386-reg.tbl (st): Move down.
 585         (st(0)): Delete. Extend comment.
 586         * i386-tbl.h: Re-generate.
 587
 588 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 591         (cmpsd): Move next to cmps.
 592         (movsd): Move next to movs.
 593         (cmpxchg16b): Move to separate section.
 594         (fisttp, fisttpll): Likewise.
 595         (monitor, mwait): Likewise.
 596         * i386-tbl.h: Re-generate.
 597
 598 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 601         (vpsadbw): Add C.
 602         * i386-tbl.h: Re-generate.
 603
 604 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 605
 606         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 607         pclmul, gfni): New templates. Use them wherever possible. Move
 608         SSE4.1 pextrw into respective section.
 609         * i386-tbl.h: Re-generate.
 610
 611 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 614         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 615         "length".
 616         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 617         Convert all of their uses to representation in opcode.
 618
 619 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 620
 621         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 622         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 623         value of None. Shrink operands to 3 bits.
 624
 625 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 626
 627         * i386-gen.c (process_i386_opcode_modifier): New parameter
 628         "space".
 629         (output_i386_opcode): New local variable "space". Adjust
 630         process_i386_opcode_modifier() invocation.
 631         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 632         invocation.
 633         * i386-tbl.h: Re-generate.
 634
 635 2021-03-29  Alan Modra  <amodra@gmail.com>
 636
 637         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 638         (fp_qualifier_p, get_data_pattern): Likewise.
 639         (aarch64_get_operand_modifier_from_value): Likewise.
 640         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 641         (operand_variant_qualifier_p): Likewise.
 642         (qualifier_value_in_range_constraint_p): Likewise.
 643         (aarch64_get_qualifier_esize): Likewise.
 644         (aarch64_get_qualifier_nelem): Likewise.
 645         (aarch64_get_qualifier_standard_value): Likewise.
 646         (get_lower_bound, get_upper_bound): Likewise.
 647         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 648         (aarch64_print_operand): Likewise.
 649         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 650         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 651         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 652         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 653         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 654         (print_insn_tic6x): Likewise.
 655
 656 2021-03-29  Alan Modra  <amodra@gmail.com>
 657
 658         * arc-dis.c (extract_operand_value): Correct NULL cast.
 659         * frv-opc.h: Regenerate.
 660
 661 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 662
 663         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 664         MMX form.
 665         * i386-tbl.h: Re-generate.
 666
 667 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 668
 669         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 670         immediate in br.n instruction.
 671
 672 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 673
 674         * i386-dis.c (XMGatherD, VexGatherD): New.
 675         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 676         (print_insn): Check masking for S/G insns.
 677         (OP_E_memory): New local variable check_gather. Extend mandatory
 678         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 679         Extend check for disallowed 16-bit addressing.
 680         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 681         if()s to switch(). Check register conflicts for (VEX-encoded)
 682         gathers. Drop no longer reachable cases.
 683         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 684         vgatherdp*.
 685
 686 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 687
 688         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 689         zeroing-masking without masking.
 690
 691 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 694         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 695         single-operand forms as deprecated.
 696         * i386-tbl.h: Re-generate.
 697
 698 2021-03-25  Alan Modra  <amodra@gmail.com>
 699
 700         PR 27647
 701         * ppc-opc.c (XLOCB_MASK): Delete.
 702         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 703         XLBH_MASK.
 704         (powerpc_opcodes): Accept a BH field on all extended forms of
 705         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 706
 707 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 708
 709         * i386-gen.c (output_i386_opcode): Drop processing of
 710         opcode_length. Calculate length from base_opcode. Adjust prefix
 711         encoding determination.
 712         (process_i386_opcodes): Drop output of fake opcode_length.
 713         * i386-opc.h (struct insn_template): Drop opcode_length field.
 714         * i386-opc.tbl: Drop opcode length field from all templates.
 715         * i386-tbl.h: Re-generate.
 716
 717 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 718
 719         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 720         parameter "prefix". Drop local variable "regular_encoding".
 721         Record prefix setting / check for consistency.
 722         (output_i386_opcode): Parse opcode_length and base_opcode
 723         earlier. Derive prefix encoding. Drop no longer applicable
 724         consistency checking. Adjust process_i386_opcode_modifier()
 725         invocation.
 726         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 727         invocation.
 728         * i386-tbl.h: Re-generate.
 729
 730 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 733         check.
 734         * i386-opc.h (Prefix_*): Move #define-s.
 735         * i386-opc.tbl: Move pseudo prefix enumerator values to
 736         extension opcode field. Introduce pseudopfx template.
 737         * i386-tbl.h: Re-generate.
 738
 739 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 742         comment.
 743         * i386-tbl.h: Re-generate.
 744
 745 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 746
 747         * i386-opc.h (struct insn_template): Move cpu_flags field past
 748         opcode_modifier one.
 749         * i386-tbl.h: Re-generate.
 750
 751 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 754         * i386-opc.h (OpcodeSpace): New enumerator.
 755         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 756         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 757         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 758         (struct i386_opcode_modifier): New field opcodespace. Shrink
 759         opcodeprefix field.
 760         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 761         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 762         OpcodePrefix uses.
 763         * i386-tbl.h: Re-generate.
 764
 765 2021-03-22  Martin Liska  <mliska@suse.cz>
 766
 767         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 768         * arc-dis.c (parse_option): Likewise.
 769         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 770         * cris-dis.c (print_with_operands): Likewise.
 771         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 772         * i386-dis.c (print_insn): Likewise.
 773         * ia64-gen.c (fetch_insn_class): Likewise.
 774         (parse_resource_users): Likewise.
 775         (in_iclass): Likewise.
 776         (lookup_specifier): Likewise.
 777         (insert_opcode_dependencies): Likewise.
 778         * mips-dis.c (parse_mips_ase_option): Likewise.
 779         (parse_mips_dis_option): Likewise.
 780         * s390-dis.c (disassemble_init_s390): Likewise.
 781         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 782
 783 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 784
 785         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 786
 787 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 788
 789         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 790         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 791
 792 2021-03-12  Alan Modra  <amodra@gmail.com>
 793
 794         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 795
 796 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 797
 798         * i386-dis.c (OP_XMM): Re-order checks.
 799
 800 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 801
 802         * i386-dis.c (putop): Drop need_vex check when also checking
 803         vex.evex.
 804         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 805         checking vex.b.
 806
 807 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 808
 809         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 810         checks. Move case label past broadcast check.
 811
 812 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 813
 814         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 815         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 816         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 817         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 818         EVEX_W_0F38C7_M_0_L_2): Delete.
 819         (REG_EVEX_0F38C7_M_0_L_2): New.
 820         (intel_operand_size): Handle VEX and EVEX the same for
 821         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 822         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 823         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 824         vex_vsib_q_w_d_mode uses.
 825         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 826         0F38A1, and 0F38A3 entries.
 827         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 828         entry.
 829         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 830         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 831         0F38A3 entries.
 832
 833 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 834
 835         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 836         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 837         MOD_VEX_0FXOP_09_12): Rename to ...
 838         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 839         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 840         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 841         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 842         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 843         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 844         (reg_table): Adjust comments.
 845         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 846         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 847         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 848         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 849         (vex_len_table): Adjust opcode 0A_12 entry.
 850         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 851         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 852         (rm_table): Move hreset entry.
 853
 854 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 855
 856         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 857         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 858         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 859         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 860         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 861         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 862         (get_valid_dis386): Also handle 512-bit vector length when
 863         vectoring into vex_len_table[].
 864         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 865         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 866         entries.
 867         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 868         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 869         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 870         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 871         entries.
 872
 873 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 874
 875         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 876         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 877         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 878         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 879         entries.
 880         * i386-dis-evex-len.h (evex_len_table): Likewise.
 881         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 882
 883 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 884
 885         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 886         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 887         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 888         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 889         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 890         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 891         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 892         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 893         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 894         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 895         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 896         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 897         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 898         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 899         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 900         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 901         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 902         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 903         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 904         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 905         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 906         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 907         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 908         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 909         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 910         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 911         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 912         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 913         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 914         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 915         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 916         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 917         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 918         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 919         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 920         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 921         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 922         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 923         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 924         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 925         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 926         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 927         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 928         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 929         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 930         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 931         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 932         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 933         EVEX_W_0F3A43_L_n): New.
 934         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 935         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 936         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 937         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 938         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 939         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 940         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 941         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 942         0F385B, 0F38C6, and 0F38C7 entries.
 943         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 944         0F38C6 and 0F38C7.
 945         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 946         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 947         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 948         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 949
 950 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 951
 952         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 953         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 954         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 955         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 956         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 957         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 958         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 959         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 960         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 961         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 962         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 963         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 964         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 965         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 966         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 967         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 968         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 969         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 970         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 971         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 972         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 973         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 974         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 975         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 976         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 977         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 978         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 979         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 980         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 981         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 982         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 983         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 984         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 985         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 986         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 987         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 988         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 989         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 990         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 991         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 992         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 993         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 994         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 995         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 996         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 997         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 998         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 999         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1000         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1001         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1002         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1003         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1004         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1005         VEX_W_0F99_P_2_LEN_0): Delete.
1006         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1007         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1008         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1009         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1010         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1011         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1012         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1013         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1014         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1015         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1016         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1017         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1018         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1019         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1020         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1021         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1022         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1023         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1024         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1025         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1026         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1027         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1028         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1029         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1030         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1031         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1032         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1033         (prefix_table): No longer link to vex_len_table[] for opcodes
1034         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1035         0F92, 0F93, 0F98, and 0F99.
1036         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1037         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1038         0F98, and 0F99.
1039         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1040         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1041         0F98, and 0F99.
1042         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1043         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1044         0F98, and 0F99.
1045         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1046         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1047         0F98, and 0F99.
1048
1049 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1050
1051         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1052         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1053         REG_VEX_0F73_M_0 respectively.
1054         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1055         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1056         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1057         MOD_VEX_0F73_REG_7): Delete.
1058         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1059         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1060         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1061         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1062         PREFIX_VEX_0F3AF0_L_0 respectively.
1063         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1064         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1065         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1066         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1067         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1068         VEX_LEN_0F38F7): New.
1069         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1070         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1071         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1072         0F38F3.
1073         (prefix_table): No longer link to vex_len_table[] for opcodes
1074         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1075         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1076         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1077         0F38F6, 0F38F7, and 0F3AF0.
1078         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1079         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1080         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1081         0F73.
1082
1083 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1084
1085         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1086         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1087         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1088         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1089         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1090         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1091         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1092         73.
1093         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1094         0F72, and 0F73.
1095         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1096         0F73.
1097
1098 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1099
1100         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1101         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1102         (reg_table): Don't link to mod_table[] where not needed. Add
1103         PREFIX_IGNORED to nop entries.
1104         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1105         (mod_table): Add nop entries next to prefetch ones. Drop
1106         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1107         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1108         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1109         PREFIX_OPCODE from endbr* entries.
1110         (get_valid_dis386): Also consider entry's name when zapping
1111         vindex.
1112         (print_insn): Handle PREFIX_IGNORED.
1113
1114 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1115
1116         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1117         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1118         element.
1119         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1120         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1121         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1122         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1123         (struct i386_opcode_modifier): Delete notrackprefixok,
1124         islockable, hleprefixok, and repprefixok fields. Add prefixok
1125         field.
1126         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1127         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1128         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1129         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1130         Replace HLEPrefixOk.
1131         * opcodes/i386-tbl.h: Re-generate.
1132
1133 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1134
1135         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1136         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1137         64-bit form.
1138         * opcodes/i386-tbl.h: Re-generate.
1139
1140 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1143         for {} instead of {0}. Don't look for '0'.
1144         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1145         size specifiers.
1146
1147 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1148
1149         PR 27158
1150         * riscv-dis.c (print_insn_args): Updated encoding macros.
1151         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1152         (match_c_addi16sp): Updated encoding macros.
1153         (match_c_lui): Likewise.
1154         (match_c_lui_with_hint): Likewise.
1155         (match_c_addi4spn): Likewise.
1156         (match_c_slli): Likewise.
1157         (match_slli_as_c_slli): Likewise.
1158         (match_c_slli64): Likewise.
1159         (match_srxi_as_c_srxi): Likewise.
1160         (riscv_insn_types): Added .insn css/cl/cs.
1161
1162 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1163
1164         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1165         (default_priv_spec): Updated type to riscv_spec_class.
1166         (parse_riscv_dis_option): Updated.
1167         * riscv-opc.c: Moved stuff and make the file tidy.
1168
1169 2021-02-17  Alan Modra  <amodra@gmail.com>
1170
1171         * wasm32-dis.c: Include limits.h.
1172         (CHAR_BIT): Provide backup define.
1173         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1174         Correct signed overflow checking.
1175
1176 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1177
1178         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1179         * i386-tbl.h: Re-generate.
1180
1181 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1182
1183         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1184         Oword.
1185         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1186
1187 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1188
1189         * s390-mkopc.c (main): Accept arch14 as cpu string.
1190         * s390-opc.txt: Add new arch14 instructions.
1191
1192 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1193
1194         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1195         favour of LIBINTL.
1196         * configure: Regenerated.
1197
1198 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1199
1200         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1201         * tic54x-opc.c (regs): Rename to ...
1202         (tic54x_regs): ... this.
1203         (mmregs): Rename to ...
1204         (tic54x_mmregs): ... this.
1205         (condition_codes): Rename to ...
1206         (tic54x_condition_codes): ... this.
1207         (cc2_codes): Rename to ...
1208         (tic54x_cc2_codes): ... this.
1209         (cc3_codes): Rename to ...
1210         (tic54x_cc3_codes): ... this.
1211         (status_bits): Rename to ...
1212         (tic54x_status_bits): ... this.
1213         (misc_symbols): Rename to ...
1214         (tic54x_misc_symbols): ... this.
1215
1216 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1217
1218         * riscv-opc.c (MASK_RVB_IMM): Removed.
1219         (riscv_opcodes): Removed zb* instructions.
1220         (riscv_ext_version_table): Removed versions for zb*.
1221
1222 2021-01-26  Alan Modra  <amodra@gmail.com>
1223
1224         * i386-gen.c (parse_template): Ensure entire template_instance
1225         is initialised.
1226
1227 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1228
1229         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1230         (riscv_fpr_names_abi): Likewise.
1231         (riscv_opcodes): Likewise.
1232         (riscv_insn_types): Likewise.
1233
1234 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1235
1236         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1237
1238 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1239
1240         * riscv-dis.c: Comments tidy and improvement.
1241         * riscv-opc.c: Likewise.
1242
1243 2021-01-13  Alan Modra  <amodra@gmail.com>
1244
1245         * Makefile.in: Regenerate.
1246
1247 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1248
1249         PR binutils/26792
1250         * configure.ac: Use GNU_MAKE_JOBSERVER.
1251         * aclocal.m4: Regenerated.
1252         * configure: Likewise.
1253
1254 2021-01-12  Nick Clifton  <nickc@redhat.com>
1255
1256         * po/sr.po: Updated Serbian translation.
1257
1258 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1259
1260         PR ld/27173
1261         * configure: Regenerated.
1262
1263 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1264
1265         * aarch64-asm-2.c: Regenerate.
1266         * aarch64-dis-2.c: Likewise.
1267         * aarch64-opc-2.c: Likewise.
1268         * aarch64-opc.c (aarch64_print_operand):
1269         Delete handling of AARCH64_OPND_CSRE_CSR.
1270         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1271         (CSRE): Likewise.
1272         (_CSRE_INSN): Likewise.
1273         (aarch64_opcode_table): Delete csr.
1274
1275 2021-01-11  Nick Clifton  <nickc@redhat.com>
1276
1277         * po/de.po: Updated German translation.
1278         * po/fr.po: Updated French translation.
1279         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1280         * po/sv.po: Updated Swedish translation.
1281         * po/uk.po: Updated Ukranian translation.
1282
1283 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1284
1285         * configure: Regenerated.
1286
1287 2021-01-09  Nick Clifton  <nickc@redhat.com>
1288
1289         * configure: Regenerate.
1290         * po/opcodes.pot: Regenerate.
1291
1292 2021-01-09  Nick Clifton  <nickc@redhat.com>
1293
1294         * 2.36 release branch crated.
1295
1296 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1297
1298         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1299         (DW, (XRC_MASK): Define.
1300         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1301
1302 2021-01-09  Alan Modra  <amodra@gmail.com>
1303
1304         * configure: Regenerate.
1305
1306 2021-01-08  Nick Clifton  <nickc@redhat.com>
1307
1308         * po/sv.po: Updated Swedish translation.
1309
1310 2021-01-08  Nick Clifton  <nickc@redhat.com>
1311
1312         PR 27129
1313         * aarch64-dis.c (determine_disassembling_preference): Move call to
1314         aarch64_match_operands_constraint outside of the assertion.
1315         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1316         Replace with a return of FALSE.
1317
1318         PR 27139
1319         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1320         core system register.
1321
1322 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1323
1324         * configure: Regenerate.
1325
1326 2021-01-07  Nick Clifton  <nickc@redhat.com>
1327
1328         * po/fr.po: Updated French translation.
1329
1330 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1331
1332         * m68k-opc.c (chkl): Change minimum architecture requirement to
1333         m68020.
1334
1335 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1336
1337         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1338
1339 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1340             Jim Wilson  <jimw@sifive.com>
1341             Andrew Waterman  <andrew@sifive.com>
1342             Maxim Blinov  <maxim.blinov@embecosm.com>
1343             Kito Cheng  <kito.cheng@sifive.com>
1344             Nelson Chu  <nelson.chu@sifive.com>
1345
1346         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1347         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1348
1349 2021-01-01  Alan Modra  <amodra@gmail.com>
1350
1351         Update year range in copyright notice of all files.
1352
1353 For older changes see ChangeLog-2020
1354 \f
1355 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1356
1357 Copying and distribution of this file, with or without modification,
1358 are permitted in any medium without royalty provided the copyright
1359 notice and this notice are preserved.
1360
1361 Local Variables:
1362 mode: change-log
1363 left-margin: 8
1364 fill-column: 74
1365 version-control: never
1366 End: