opcodes/ChangeLog

   1 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
   2             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
   3
   4         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
   5         * mips-opc.c (CRC, CRC64): New macros.
   6         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
   7         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
   8         crc32cd for CRC64.
   9
  10 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
  11
  12         PR 20319
  13         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
  14         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
  15
  16 2018-06-06  Alan Modra  <amodra@gmail.com>
  17
  18         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
  19         setjmp.  Move init for some other vars later too.
  20
  21 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
  22
  23         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
  24         (dis_private): Add new fields for property section tracking.
  25         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
  26         (xtensa_instruction_fits): New functions.
  27         (fetch_data): Bump minimal fetch size to 4.
  28         (print_insn_xtensa): Make struct dis_private static.
  29         Load and prepare property table on section change.
  30         Don't disassemble literals. Don't disassemble instructions that
  31         cross property table boundaries.
  32
  33 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * configure: Regenerated.
  36
  37 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
  40         * i386-tbl.h: Re-generate.
  41
  42 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.tbl (sldt, str): Add NoRex64.
  45         * i386-tbl.h: Re-generate.
  46
  47 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-opc.tbl (invpcid): Add Oword.
  50         * i386-tbl.h: Re-generate.
  51
  52 2018-06-01  Alan Modra  <amodra@gmail.com>
  53
  54         * sysdep.h (_bfd_error_handler): Don't declare.
  55         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
  56         * rl78-decode.opc: Likewise.
  57         * msp430-decode.c: Regenerate.
  58         * rl78-decode.c: Regenerate.
  59
  60 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
  61
  62         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
  63         * i386-init.h : Regenerated.
  64
  65 2018-05-25  Alan Modra  <amodra@gmail.com>
  66
  67         * Makefile.in: Regenerate.
  68         * po/POTFILES.in: Regenerate.
  69
  70 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
  71
  72         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
  73         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
  74         (insert_bab, extract_bab, insert_btab, extract_btab,
  75         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
  76         (BAT, BBA VBA RBS XB6S): Delete macros.
  77         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
  78         (BB, BD, RBX, XC6): Update for new macros.
  79         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
  80         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
  81         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
  82         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
  83
  84 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
  85
  86         * Makefile.am: Add support for s12z architecture.
  87         * configure.ac: Likewise.
  88         * disassemble.c: Likewise.
  89         * disassemble.h: Likewise.
  90         * Makefile.in: Regenerate.
  91         * configure: Regenerate.
  92         * s12z-dis.c: New file.
  93         * s12z.h: New file.
  94
  95 2018-05-18  Alan Modra  <amodra@gmail.com>
  96
  97         * nfp-dis.c: Don't #include libbfd.h.
  98         (init_nfp3200_priv): Use bfd_get_section_contents.
  99         (nit_nfp6000_mecsr_sec): Likewise.
 100
 101 2018-05-17  Nick Clifton  <nickc@redhat.com>
 102
 103         * po/zh_CN.po: Updated simplified Chinese translation.
 104
 105 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 106
 107         PR binutils/23109
 108         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 109         * aarch64-dis-2.c: Regenerate.
 110
 111 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 112
 113         PR binutils/21446
 114         * aarch64-asm.c (opintl.h): Include.
 115         (aarch64_ins_sysreg): Enforce read/write constraints.
 116         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 117         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 118         (F_REG_READ, F_REG_WRITE): New.
 119         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 120         AARCH64_OPND_SYSREG.
 121         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 122         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 123         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 124         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 125         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 126         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 127         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 128         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 129         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 130         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 131         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 132         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 133         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 134         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 135         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 136         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 137         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 138
 139 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 140
 141         PR binutils/21446
 142         * aarch64-dis.c (no_notes: New.
 143         (parse_aarch64_dis_option): Support notes.
 144         (aarch64_decode_insn, print_operands): Likewise.
 145         (print_aarch64_disassembler_options): Document notes.
 146         * aarch64-opc.c (aarch64_print_operand): Support notes.
 147
 148 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 149
 150         PR binutils/21446
 151         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 152         and take error struct.
 153         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 154         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 155         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 156         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 157         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 158         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 159         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 160         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 161         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 162         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 163         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 164         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 165         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 166         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 167         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 168         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 169         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 170         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 171         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 172         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 173         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 174         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 175         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 176         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 177         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 178         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 179         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 180         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 181         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 182         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 183         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 184         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 185         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 186         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 187         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 188         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 189         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 190         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 191         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 192         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 193         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 194         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 195         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 196         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 197         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 198         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 199         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 200         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 201         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 202         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 203         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 204         (determine_disassembling_preference, aarch64_decode_insn,
 205         print_insn_aarch64_word, print_insn_data): Take errors struct.
 206         (print_insn_aarch64): Use errors.
 207         * aarch64-asm-2.c: Regenerate.
 208         * aarch64-dis-2.c: Regenerate.
 209         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 210         boolean in aarch64_insert_operan.
 211         (print_operand_extractor): Likewise.
 212         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 213
 214 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 215
 216         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 217
 218 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 221
 222 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 223
 224         * cr16-opc.c (cr16_instruction): Comment typo fix.
 225         * hppa-dis.c (print_insn_hppa): Likewise.
 226
 227 2018-05-08  Jim Wilson  <jimw@sifive.com>
 228
 229         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 230         (match_c_slli64, match_srxi_as_c_srxi): New.
 231         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 232         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 233         <c.slli, c.srli, c.srai>: Use match_s_slli.
 234         <c.slli64, c.srli64, c.srai64>: New.
 235
 236 2018-05-08  Alan Modra  <amodra@gmail.com>
 237
 238         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 239         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 240         partition opcode space for index lookup.
 241
 242 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 243
 244         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 245         <insn_length>: ...with this.  Update usage.
 246         Remove duplicate call to *info->memory_error_func.
 247
 248 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 249             H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         * i386-dis.c (Gva): New.
 252         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 253         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 254         (prefix_table): New instructions (see prefix above).
 255         (mod_table): New instructions (see prefix above).
 256         (OP_G): Handle va_mode.
 257         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 258         CPU_MOVDIR64B_FLAGS.
 259         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 260         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 261         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 262         * i386-opc.tbl: Add movidir{i,64b}.
 263         * i386-init.h: Regenerated.
 264         * i386-tbl.h: Likewise.
 265
 266 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 267
 268         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 269         AddrPrefixOpReg.
 270         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 271         (AddrPrefixOpReg): This.
 272         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 273         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 274
 275 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 276
 277         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 278         (vle_num_opcodes): Likewise.
 279         (spe2_num_opcodes): Likewise.
 280         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 281         initialization loop.
 282         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 283         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 284         only once.
 285
 286 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 287
 288         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 289
 290 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 291
 292         Makefile.am: Added nfp-dis.c.
 293         configure.ac: Added bfd_nfp_arch.
 294         disassemble.h: Added print_insn_nfp prototype.
 295         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 296         nfp-dis.c: New, for NFP support.
 297         po/POTFILES.in: Added nfp-dis.c to the list.
 298         Makefile.in: Regenerate.
 299         configure: Regenerate.
 300
 301 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 304         templates into their base ones.
 305         * i386-tlb.h: Re-generate.
 306
 307 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 310         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 311         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 312         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 313         * i386-init.h: Re-generate.
 314
 315 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 316
 317         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 318         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 319         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 320         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 321         comment.
 322         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 323         and CpuRegMask.
 324         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 325         CpuRegMask: Delete.
 326         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 327         cpuregzmm, and cpuregmask.
 328         * i386-init.h: Re-generate.
 329         * i386-tbl.h: Re-generate.
 330
 331 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 334         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 335         * i386-init.h: Re-generate.
 336
 337 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-gen.c (VexImmExt): Delete.
 340         * i386-opc.h (VexImmExt, veximmext): Delete.
 341         * i386-opc.tbl: Drop all VexImmExt uses.
 342         * i386-tlb.h: Re-generate.
 343
 344 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 347         register-only forms.
 348         * i386-tlb.h: Re-generate.
 349
 350 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 351
 352         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 353
 354 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 355
 356         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 357         PREFIX_0F1C.
 358         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 359         (cpu_flags): Add CpuCLDEMOTE.
 360         * i386-init.h: Regenerate.
 361         * i386-opc.h (enum): Add CpuCLDEMOTE,
 362         (i386_cpu_flags): Add cpucldemote.
 363         * i386-opc.tbl: Add cldemote.
 364         * i386-tbl.h: Regenerate.
 365
 366 2018-04-16  Alan Modra  <amodra@gmail.com>
 367
 368         * Makefile.am: Remove sh5 and sh64 support.
 369         * configure.ac: Likewise.
 370         * disassemble.c: Likewise.
 371         * disassemble.h: Likewise.
 372         * sh-dis.c: Likewise.
 373         * sh64-dis.c: Delete.
 374         * sh64-opc.c: Delete.
 375         * sh64-opc.h: Delete.
 376         * Makefile.in: Regenerate.
 377         * configure: Regenerate.
 378         * po/POTFILES.in: Regenerate.
 379
 380 2018-04-16  Alan Modra  <amodra@gmail.com>
 381
 382         * Makefile.am: Remove w65 support.
 383         * configure.ac: Likewise.
 384         * disassemble.c: Likewise.
 385         * disassemble.h: Likewise.
 386         * w65-dis.c: Delete.
 387         * w65-opc.h: Delete.
 388         * Makefile.in: Regenerate.
 389         * configure: Regenerate.
 390         * po/POTFILES.in: Regenerate.
 391
 392 2018-04-16  Alan Modra  <amodra@gmail.com>
 393
 394         * configure.ac: Remove we32k support.
 395         * configure: Regenerate.
 396
 397 2018-04-16  Alan Modra  <amodra@gmail.com>
 398
 399         * Makefile.am: Remove m88k support.
 400         * configure.ac: Likewise.
 401         * disassemble.c: Likewise.
 402         * disassemble.h: Likewise.
 403         * m88k-dis.c: Delete.
 404         * Makefile.in: Regenerate.
 405         * configure: Regenerate.
 406         * po/POTFILES.in: Regenerate.
 407
 408 2018-04-16  Alan Modra  <amodra@gmail.com>
 409
 410         * Makefile.am: Remove i370 support.
 411         * configure.ac: Likewise.
 412         * disassemble.c: Likewise.
 413         * disassemble.h: Likewise.
 414         * i370-dis.c: Delete.
 415         * i370-opc.c: Delete.
 416         * Makefile.in: Regenerate.
 417         * configure: Regenerate.
 418         * po/POTFILES.in: Regenerate.
 419
 420 2018-04-16  Alan Modra  <amodra@gmail.com>
 421
 422         * Makefile.am: Remove h8500 support.
 423         * configure.ac: Likewise.
 424         * disassemble.c: Likewise.
 425         * disassemble.h: Likewise.
 426         * h8500-dis.c: Delete.
 427         * h8500-opc.h: Delete.
 428         * Makefile.in: Regenerate.
 429         * configure: Regenerate.
 430         * po/POTFILES.in: Regenerate.
 431
 432 2018-04-16  Alan Modra  <amodra@gmail.com>
 433
 434         * configure.ac: Remove tahoe support.
 435         * configure: Regenerate.
 436
 437 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 440         umwait.
 441         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 442         64-bit mode.
 443         * i386-tbl.h: Regenerated.
 444
 445 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 446
 447         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 448         PREFIX_MOD_1_0FAE_REG_6.
 449         (va_mode): New.
 450         (OP_E_register): Use va_mode.
 451         * i386-dis-evex.h (prefix_table):
 452         New instructions (see prefixes above).
 453         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 454         (cpu_flags): Likewise.
 455         * i386-opc.h (enum): Likewise.
 456         (i386_cpu_flags): Likewise.
 457         * i386-opc.tbl: Add umonitor, umwait, tpause.
 458         * i386-init.h: Regenerate.
 459         * i386-tbl.h: Likewise.
 460
 461 2018-04-11  Alan Modra  <amodra@gmail.com>
 462
 463         * opcodes/i860-dis.c: Delete.
 464         * opcodes/i960-dis.c: Delete.
 465         * Makefile.am: Remove i860 and i960 support.
 466         * configure.ac: Likewise.
 467         * disassemble.c: Likewise.
 468         * disassemble.h: Likewise.
 469         * Makefile.in: Regenerate.
 470         * configure: Regenerate.
 471         * po/POTFILES.in: Regenerate.
 472
 473 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 474
 475         PR binutils/23025
 476         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 477         to 0.
 478         (print_insn): Clear vex instead of vex.evex.
 479
 480 2018-04-04  Nick Clifton  <nickc@redhat.com>
 481
 482         * po/es.po: Updated Spanish translation.
 483
 484 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-gen.c (opcode_modifiers): Delete VecESize.
 487         * i386-opc.h (VecESize): Delete.
 488         (struct i386_opcode_modifier): Delete vecesize.
 489         * i386-opc.tbl: Drop VecESize.
 490         * i386-tlb.h: Re-generate.
 491
 492 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 493
 494         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 495         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 496         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 497         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 498         * i386-tlb.h: Re-generate.
 499
 500 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 501
 502         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 503         Fold AVX512 forms
 504         * i386-tlb.h: Re-generate.
 505
 506 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 509         (vex_len_table): Drop Y for vcvt*2si.
 510         (putop): Replace plain 'Y' handling by abort().
 511
 512 2018-03-28  Nick Clifton  <nickc@redhat.com>
 513
 514         PR 22988
 515         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 516         instructions with only a base address register.
 517         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 518         handle AARHC64_OPND_SVE_ADDR_R.
 519         (aarch64_print_operand): Likewise.
 520         * aarch64-asm-2.c: Regenerate.
 521         * aarch64_dis-2.c: Regenerate.
 522         * aarch64-opc-2.c: Regenerate.
 523
 524 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-opc.tbl: Drop VecESize from register only insn forms and
 527         memory forms not allowing broadcast.
 528         * i386-tlb.h: Re-generate.
 529
 530 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 533         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 534         sha256*): Drop Disp<N>.
 535
 536 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 537
 538         * i386-dis.c (EbndS, bnd_swap_mode): New.
 539         (prefix_table): Use EbndS.
 540         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 541         * i386-opc.tbl (bndmov): Move misplaced Load.
 542         * i386-tlb.h: Re-generate.
 543
 544 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 545
 546         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 547         templates allowing memory operands and folded ones for register
 548         only flavors.
 549         * i386-tlb.h: Re-generate.
 550
 551 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 552
 553         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 554         256-bit templates. Drop redundant leftover Disp<N>.
 555         * i386-tlb.h: Re-generate.
 556
 557 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 558
 559         * riscv-opc.c (riscv_insn_types): New.
 560
 561 2018-03-13  Nick Clifton  <nickc@redhat.com>
 562
 563         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 564
 565 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 566
 567         * i386-opc.tbl: Add Optimize to clr.
 568         * i386-tbl.h: Regenerated.
 569
 570 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 571
 572         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 573         * i386-opc.h (OldGcc): Removed.
 574         (i386_opcode_modifier): Remove oldgcc.
 575         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 576         instructions for old (<= 2.8.1) versions of gcc.
 577         * i386-tbl.h: Regenerated.
 578
 579 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 580
 581         * i386-opc.h (EVEXDYN): New.
 582         * i386-opc.tbl: Fold various AVX512VL templates.
 583         * i386-tlb.h: Re-generate.
 584
 585 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 586
 587         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 588         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 589         vpexpandd, vpexpandq): Fold AFX512VF templates.
 590         * i386-tlb.h: Re-generate.
 591
 592 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 595         Fold 128- and 256-bit VEX-encoded templates.
 596         * i386-tlb.h: Re-generate.
 597
 598 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 601         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 602         vpexpandd, vpexpandq): Fold AVX512F templates.
 603         * i386-tlb.h: Re-generate.
 604
 605 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 606
 607         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 608         64-bit templates. Drop Disp<N>.
 609         * i386-tlb.h: Re-generate.
 610
 611 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 614         and 256-bit templates.
 615         * i386-tlb.h: Re-generate.
 616
 617 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 620         * i386-tlb.h: Re-generate.
 621
 622 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 623
 624         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 625         Drop NoAVX.
 626         * i386-tlb.h: Re-generate.
 627
 628 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 629
 630         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 631         * i386-tlb.h: Re-generate.
 632
 633 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 634
 635         * i386-gen.c (opcode_modifiers): Delete FloatD.
 636         * i386-opc.h (FloatD): Delete.
 637         (struct i386_opcode_modifier): Delete floatd.
 638         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 639         FloatD by D.
 640         * i386-tlb.h: Re-generate.
 641
 642 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 643
 644         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 645
 646 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 649         * i386-tlb.h: Re-generate.
 650
 651 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 654         forms.
 655         * i386-tlb.h: Re-generate.
 656
 657 2018-03-07  Alan Modra  <amodra@gmail.com>
 658
 659         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 660         bfd_arch_rs6000.
 661         * disassemble.h (print_insn_rs6000): Delete.
 662         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 663         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 664         (print_insn_rs6000): Delete.
 665
 666 2018-03-03  Alan Modra  <amodra@gmail.com>
 667
 668         * sysdep.h (opcodes_error_handler): Define.
 669         (_bfd_error_handler): Declare.
 670         * Makefile.am: Remove stray #.
 671         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 672         EDIT" comment.
 673         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 674         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 675         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 676         opcodes_error_handler to print errors.  Standardize error messages.
 677         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 678         and include opintl.h.
 679         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 680         * i386-gen.c: Standardize error messages.
 681         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 682         * Makefile.in: Regenerate.
 683         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 684         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 685         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 686         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 687         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 688         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 689         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 690         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 691         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 692         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 693         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 694         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 695         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 696
 697 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 698
 699         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 700         vpsub[bwdq] instructions.
 701         * i386-tbl.h: Regenerated.
 702
 703 2018-03-01  Alan Modra  <amodra@gmail.com>
 704
 705         * configure.ac (ALL_LINGUAS): Sort.
 706         * configure: Regenerate.
 707
 708 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 709
 710         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 711         macro by assignements.
 712
 713 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 714
 715         PR gas/22871
 716         * i386-gen.c (opcode_modifiers): Add Optimize.
 717         * i386-opc.h (Optimize): New enum.
 718         (i386_opcode_modifier): Add optimize.
 719         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 720         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 721         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 722         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 723         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 724         vpxord and vpxorq.
 725         * i386-tbl.h: Regenerated.
 726
 727 2018-02-26  Alan Modra  <amodra@gmail.com>
 728
 729         * crx-dis.c (getregliststring): Allocate a large enough buffer
 730         to silence false positive gcc8 warning.
 731
 732 2018-02-22  Shea Levy <shea@shealevy.com>
 733
 734         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 735
 736 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 737
 738         * i386-opc.tbl: Add {rex},
 739         * i386-tbl.h: Regenerated.
 740
 741 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 742
 743         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 744         (mips16_opcodes): Replace `M' with `m' for "restore".
 745
 746 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 747
 748         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 749
 750 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 751
 752         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 753         variable to `function_index'.
 754
 755 2018-02-13  Nick Clifton  <nickc@redhat.com>
 756
 757         PR 22823
 758         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 759         about truncation of printing.
 760
 761 2018-02-12  Henry Wong <henry@stuffedcow.net>
 762
 763         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 764
 765 2018-02-05  Nick Clifton  <nickc@redhat.com>
 766
 767         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 768
 769 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 770
 771         * i386-dis.c (enum): Add pconfig.
 772         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 773         (cpu_flags): Add CpuPCONFIG.
 774         * i386-opc.h (enum): Add CpuPCONFIG.
 775         (i386_cpu_flags): Add cpupconfig.
 776         * i386-opc.tbl: Add PCONFIG instruction.
 777         * i386-init.h: Regenerate.
 778         * i386-tbl.h: Likewise.
 779
 780 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 781
 782         * i386-dis.c (enum): Add PREFIX_0F09.
 783         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 784         (cpu_flags): Add CpuWBNOINVD.
 785         * i386-opc.h (enum): Add CpuWBNOINVD.
 786         (i386_cpu_flags): Add cpuwbnoinvd.
 787         * i386-opc.tbl: Add WBNOINVD instruction.
 788         * i386-init.h: Regenerate.
 789         * i386-tbl.h: Likewise.
 790
 791 2018-01-17  Jim Wilson  <jimw@sifive.com>
 792
 793         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 794
 795 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 796
 797         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 798         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 799         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 800         (cpu_flags): Add CpuIBT, CpuSHSTK.
 801         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 802         (i386_cpu_flags): Add cpuibt, cpushstk.
 803         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 804         * i386-init.h: Regenerate.
 805         * i386-tbl.h: Likewise.
 806
 807 2018-01-16  Nick Clifton  <nickc@redhat.com>
 808
 809         * po/pt_BR.po: Updated Brazilian Portugese translation.
 810         * po/de.po: Updated German translation.
 811
 812 2018-01-15  Jim Wilson  <jimw@sifive.com>
 813
 814         * riscv-opc.c (match_c_nop): New.
 815         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 816
 817 2018-01-15  Nick Clifton  <nickc@redhat.com>
 818
 819         * po/uk.po: Updated Ukranian translation.
 820
 821 2018-01-13  Nick Clifton  <nickc@redhat.com>
 822
 823         * po/opcodes.pot: Regenerated.
 824
 825 2018-01-13  Nick Clifton  <nickc@redhat.com>
 826
 827         * configure: Regenerate.
 828
 829 2018-01-13  Nick Clifton  <nickc@redhat.com>
 830
 831         2.30 branch created.
 832
 833 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 834
 835         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 836         * i386-tbl.h: Regenerate.
 837
 838 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 839
 840         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 841         * i386-tbl.h: Re-generate.
 842
 843 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 846         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 847         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 848         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 849         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 850         Disp8MemShift of AVX512VL forms.
 851         * i386-tbl.h: Re-generate.
 852
 853 2018-01-09  Jim Wilson  <jimw@sifive.com>
 854
 855         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 856         then the hi_addr value is zero.
 857
 858 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 859
 860         * arm-dis.c (arm_opcodes): Add csdb.
 861         (thumb32_opcodes): Add csdb.
 862
 863 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 864
 865         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 866         * aarch64-asm-2.c: Regenerate.
 867         * aarch64-dis-2.c: Regenerate.
 868         * aarch64-opc-2.c: Regenerate.
 869
 870 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         PR gas/22681
 873         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 874         Remove AVX512 vmovd with 64-bit operands.
 875         * i386-tbl.h: Regenerated.
 876
 877 2018-01-05  Jim Wilson  <jimw@sifive.com>
 878
 879         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 880         jalr.
 881
 882 2018-01-03  Alan Modra  <amodra@gmail.com>
 883
 884         Update year range in copyright notice of all files.
 885
 886 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 887
 888         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 889         and OPERAND_TYPE_REGZMM entries.
 890
 891 For older changes see ChangeLog-2017
 892 \f
 893 Copyright (C) 2018 Free Software Foundation, Inc.
 894
 895 Copying and distribution of this file, with or without modification,
 896 are permitted in any medium without royalty provided the copyright
 897 notice and this notice are preserved.
 898
 899 Local Variables:
 900 mode: change-log
 901 left-margin: 8
 902 fill-column: 74
 903 version-control: never
 904 End: