opcodes/ChangeLog

   1 2021-03-31  Alan Modra  <amodra@gmail.com>
   2
   3         * sysdep.h (POISON_BFD_BOOLEAN): Define.
   4         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
   5         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
   6         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
   7         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
   8         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
   9         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
  10         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
  11         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
  12         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
  13         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
  14         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
  15         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
  16         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
  17         and TRUE with true throughout.
  18
  19 2021-03-31  Alan Modra  <amodra@gmail.com>
  20
  21         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
  22         * aarch64-dis.h: Likewise.
  23         * aarch64-opc.c: Likewise.
  24         * avr-dis.c: Likewise.
  25         * csky-dis.c: Likewise.
  26         * nds32-asm.c: Likewise.
  27         * nds32-dis.c: Likewise.
  28         * nfp-dis.c: Likewise.
  29         * riscv-dis.c: Likewise.
  30         * s12z-dis.c: Likewise.
  31         * wasm32-dis.c: Likewise.
  32
  33 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
  36         (i386_seg_prefixes): New.
  37         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
  38         (i386_seg_prefixes): Declare.
  39
  40 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  41
  42         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
  43
  44 2021-03-30  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
  47         * i386-reg.tbl (st): Move down.
  48         (st(0)): Delete. Extend comment.
  49         * i386-tbl.h: Re-generate.
  50
  51 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
  54         (cmpsd): Move next to cmps.
  55         (movsd): Move next to movs.
  56         (cmpxchg16b): Move to separate section.
  57         (fisttp, fisttpll): Likewise.
  58         (monitor, mwait): Likewise.
  59         * i386-tbl.h: Re-generate.
  60
  61 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  62
  63         * i386-opc.tbl (psadbw): Add <sse2:comm>.
  64         (vpsadbw): Add C.
  65         * i386-tbl.h: Re-generate.
  66
  67 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
  70         pclmul, gfni): New templates. Use them wherever possible. Move
  71         SSE4.1 pextrw into respective section.
  72         * i386-tbl.h: Re-generate.
  73
  74 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
  77         strtoull(). Bump upper loop bound. Widen masks. Sanity check
  78         "length".
  79         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
  80         Convert all of their uses to representation in opcode.
  81
  82 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
  85         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
  86         value of None. Shrink operands to 3 bits.
  87
  88 2021-03-29  Jan Beulich  <jbeulich@suse.com>
  89
  90         * i386-gen.c (process_i386_opcode_modifier): New parameter
  91         "space".
  92         (output_i386_opcode): New local variable "space". Adjust
  93         process_i386_opcode_modifier() invocation.
  94         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  95         invocation.
  96         * i386-tbl.h: Re-generate.
  97
  98 2021-03-29  Alan Modra  <amodra@gmail.com>
  99
 100         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 101         (fp_qualifier_p, get_data_pattern): Likewise.
 102         (aarch64_get_operand_modifier_from_value): Likewise.
 103         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 104         (operand_variant_qualifier_p): Likewise.
 105         (qualifier_value_in_range_constraint_p): Likewise.
 106         (aarch64_get_qualifier_esize): Likewise.
 107         (aarch64_get_qualifier_nelem): Likewise.
 108         (aarch64_get_qualifier_standard_value): Likewise.
 109         (get_lower_bound, get_upper_bound): Likewise.
 110         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 111         (aarch64_print_operand): Likewise.
 112         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 113         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 114         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 115         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 116         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 117         (print_insn_tic6x): Likewise.
 118
 119 2021-03-29  Alan Modra  <amodra@gmail.com>
 120
 121         * arc-dis.c (extract_operand_value): Correct NULL cast.
 122         * frv-opc.h: Regenerate.
 123
 124 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 127         MMX form.
 128         * i386-tbl.h: Re-generate.
 129
 130 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 131
 132         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 133         immediate in br.n instruction.
 134
 135 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-dis.c (XMGatherD, VexGatherD): New.
 138         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 139         (print_insn): Check masking for S/G insns.
 140         (OP_E_memory): New local variable check_gather. Extend mandatory
 141         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 142         Extend check for disallowed 16-bit addressing.
 143         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 144         if()s to switch(). Check register conflicts for (VEX-encoded)
 145         gathers. Drop no longer reachable cases.
 146         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 147         vgatherdp*.
 148
 149 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 152         zeroing-masking without masking.
 153
 154 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 157         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 158         single-operand forms as deprecated.
 159         * i386-tbl.h: Re-generate.
 160
 161 2021-03-25  Alan Modra  <amodra@gmail.com>
 162
 163         PR 27647
 164         * ppc-opc.c (XLOCB_MASK): Delete.
 165         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 166         XLBH_MASK.
 167         (powerpc_opcodes): Accept a BH field on all extended forms of
 168         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 169
 170 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 171
 172         * i386-gen.c (output_i386_opcode): Drop processing of
 173         opcode_length. Calculate length from base_opcode. Adjust prefix
 174         encoding determination.
 175         (process_i386_opcodes): Drop output of fake opcode_length.
 176         * i386-opc.h (struct insn_template): Drop opcode_length field.
 177         * i386-opc.tbl: Drop opcode length field from all templates.
 178         * i386-tbl.h: Re-generate.
 179
 180 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 183         parameter "prefix". Drop local variable "regular_encoding".
 184         Record prefix setting / check for consistency.
 185         (output_i386_opcode): Parse opcode_length and base_opcode
 186         earlier. Derive prefix encoding. Drop no longer applicable
 187         consistency checking. Adjust process_i386_opcode_modifier()
 188         invocation.
 189         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 190         invocation.
 191         * i386-tbl.h: Re-generate.
 192
 193 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 196         check.
 197         * i386-opc.h (Prefix_*): Move #define-s.
 198         * i386-opc.tbl: Move pseudo prefix enumerator values to
 199         extension opcode field. Introduce pseudopfx template.
 200         * i386-tbl.h: Re-generate.
 201
 202 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 203
 204         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 205         comment.
 206         * i386-tbl.h: Re-generate.
 207
 208 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-opc.h (struct insn_template): Move cpu_flags field past
 211         opcode_modifier one.
 212         * i386-tbl.h: Re-generate.
 213
 214 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 215
 216         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 217         * i386-opc.h (OpcodeSpace): New enumerator.
 218         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 219         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 220         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 221         (struct i386_opcode_modifier): New field opcodespace. Shrink
 222         opcodeprefix field.
 223         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 224         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 225         OpcodePrefix uses.
 226         * i386-tbl.h: Re-generate.
 227
 228 2021-03-22  Martin Liska  <mliska@suse.cz>
 229
 230         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 231         * arc-dis.c (parse_option): Likewise.
 232         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 233         * cris-dis.c (print_with_operands): Likewise.
 234         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 235         * i386-dis.c (print_insn): Likewise.
 236         * ia64-gen.c (fetch_insn_class): Likewise.
 237         (parse_resource_users): Likewise.
 238         (in_iclass): Likewise.
 239         (lookup_specifier): Likewise.
 240         (insert_opcode_dependencies): Likewise.
 241         * mips-dis.c (parse_mips_ase_option): Likewise.
 242         (parse_mips_dis_option): Likewise.
 243         * s390-dis.c (disassemble_init_s390): Likewise.
 244         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 245
 246 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 247
 248         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 249
 250 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 251
 252         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 253         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 254
 255 2021-03-12  Alan Modra  <amodra@gmail.com>
 256
 257         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 258
 259 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-dis.c (OP_XMM): Re-order checks.
 262
 263 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-dis.c (putop): Drop need_vex check when also checking
 266         vex.evex.
 267         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 268         checking vex.b.
 269
 270 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 273         checks. Move case label past broadcast check.
 274
 275 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 276
 277         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 278         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 279         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 280         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 281         EVEX_W_0F38C7_M_0_L_2): Delete.
 282         (REG_EVEX_0F38C7_M_0_L_2): New.
 283         (intel_operand_size): Handle VEX and EVEX the same for
 284         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 285         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 286         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 287         vex_vsib_q_w_d_mode uses.
 288         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 289         0F38A1, and 0F38A3 entries.
 290         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 291         entry.
 292         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 293         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 294         0F38A3 entries.
 295
 296 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 297
 298         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 299         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 300         MOD_VEX_0FXOP_09_12): Rename to ...
 301         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 302         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 303         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 304         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 305         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 306         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 307         (reg_table): Adjust comments.
 308         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 309         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 310         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 311         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 312         (vex_len_table): Adjust opcode 0A_12 entry.
 313         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 314         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 315         (rm_table): Move hreset entry.
 316
 317 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 318
 319         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 320         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 321         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 322         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 323         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 324         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 325         (get_valid_dis386): Also handle 512-bit vector length when
 326         vectoring into vex_len_table[].
 327         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 328         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 329         entries.
 330         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 331         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 332         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 333         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 334         entries.
 335
 336 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 337
 338         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 339         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 340         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 341         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 342         entries.
 343         * i386-dis-evex-len.h (evex_len_table): Likewise.
 344         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 345
 346 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 347
 348         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 349         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 350         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 351         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 352         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 353         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 354         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 355         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 356         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 357         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 358         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 359         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 360         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 361         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 362         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 363         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 364         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 365         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 366         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 367         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 368         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 369         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 370         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 371         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 372         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 373         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 374         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 375         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 376         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 377         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 378         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 379         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 380         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 381         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 382         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 383         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 384         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 385         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 386         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 387         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 388         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 389         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 390         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 391         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 392         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 393         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 394         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 395         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 396         EVEX_W_0F3A43_L_n): New.
 397         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 398         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 399         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 400         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 401         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 402         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 403         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 404         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 405         0F385B, 0F38C6, and 0F38C7 entries.
 406         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 407         0F38C6 and 0F38C7.
 408         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 409         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 410         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 411         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 412
 413 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 414
 415         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 416         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 417         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 418         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 419         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 420         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 421         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 422         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 423         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 424         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 425         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 426         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 427         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 428         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 429         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 430         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 431         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 432         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 433         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 434         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 435         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 436         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 437         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 438         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 439         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 440         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 441         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 442         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 443         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 444         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 445         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 446         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 447         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 448         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 449         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 450         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 451         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 452         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 453         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 454         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 455         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 456         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 457         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 458         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 459         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 460         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 461         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 462         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 463         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 464         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 465         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 466         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 467         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 468         VEX_W_0F99_P_2_LEN_0): Delete.
 469         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 470         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 471         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 472         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 473         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 474         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 475         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 476         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 477         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 478         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 479         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 480         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 481         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 482         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 483         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 484         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 485         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 486         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 487         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 488         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 489         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 490         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 491         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 492         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 493         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 494         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 495         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 496         (prefix_table): No longer link to vex_len_table[] for opcodes
 497         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 498         0F92, 0F93, 0F98, and 0F99.
 499         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 500         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 501         0F98, and 0F99.
 502         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 503         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 504         0F98, and 0F99.
 505         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 506         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 507         0F98, and 0F99.
 508         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 509         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 510         0F98, and 0F99.
 511
 512 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 513
 514         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 515         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 516         REG_VEX_0F73_M_0 respectively.
 517         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 518         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 519         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 520         MOD_VEX_0F73_REG_7): Delete.
 521         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 522         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 523         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 524         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 525         PREFIX_VEX_0F3AF0_L_0 respectively.
 526         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 527         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 528         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 529         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 530         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 531         VEX_LEN_0F38F7): New.
 532         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 533         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 534         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 535         0F38F3.
 536         (prefix_table): No longer link to vex_len_table[] for opcodes
 537         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 538         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 539         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 540         0F38F6, 0F38F7, and 0F3AF0.
 541         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 542         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 543         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 544         0F73.
 545
 546 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 547
 548         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 549         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 550         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 551         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 552         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 553         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 554         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 555         73.
 556         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 557         0F72, and 0F73.
 558         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 559         0F73.
 560
 561 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 562
 563         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 564         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 565         (reg_table): Don't link to mod_table[] where not needed. Add
 566         PREFIX_IGNORED to nop entries.
 567         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 568         (mod_table): Add nop entries next to prefetch ones. Drop
 569         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 570         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 571         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 572         PREFIX_OPCODE from endbr* entries.
 573         (get_valid_dis386): Also consider entry's name when zapping
 574         vindex.
 575         (print_insn): Handle PREFIX_IGNORED.
 576
 577 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 578
 579         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 580         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 581         element.
 582         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 583         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 584         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 585         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 586         (struct i386_opcode_modifier): Delete notrackprefixok,
 587         islockable, hleprefixok, and repprefixok fields. Add prefixok
 588         field.
 589         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 590         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 591         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 592         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 593         Replace HLEPrefixOk.
 594         * opcodes/i386-tbl.h: Re-generate.
 595
 596 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 597
 598         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 599         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 600         64-bit form.
 601         * opcodes/i386-tbl.h: Re-generate.
 602
 603 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 604
 605         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 606         for {} instead of {0}. Don't look for '0'.
 607         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 608         size specifiers.
 609
 610 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 611
 612         PR 27158
 613         * riscv-dis.c (print_insn_args): Updated encoding macros.
 614         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 615         (match_c_addi16sp): Updated encoding macros.
 616         (match_c_lui): Likewise.
 617         (match_c_lui_with_hint): Likewise.
 618         (match_c_addi4spn): Likewise.
 619         (match_c_slli): Likewise.
 620         (match_slli_as_c_slli): Likewise.
 621         (match_c_slli64): Likewise.
 622         (match_srxi_as_c_srxi): Likewise.
 623         (riscv_insn_types): Added .insn css/cl/cs.
 624
 625 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 626
 627         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 628         (default_priv_spec): Updated type to riscv_spec_class.
 629         (parse_riscv_dis_option): Updated.
 630         * riscv-opc.c: Moved stuff and make the file tidy.
 631
 632 2021-02-17  Alan Modra  <amodra@gmail.com>
 633
 634         * wasm32-dis.c: Include limits.h.
 635         (CHAR_BIT): Provide backup define.
 636         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 637         Correct signed overflow checking.
 638
 639 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 640
 641         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 642         * i386-tbl.h: Re-generate.
 643
 644 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 645
 646         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 647         Oword.
 648         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 649
 650 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 651
 652         * s390-mkopc.c (main): Accept arch14 as cpu string.
 653         * s390-opc.txt: Add new arch14 instructions.
 654
 655 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 656
 657         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 658         favour of LIBINTL.
 659         * configure: Regenerated.
 660
 661 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 662
 663         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 664         * tic54x-opc.c (regs): Rename to ...
 665         (tic54x_regs): ... this.
 666         (mmregs): Rename to ...
 667         (tic54x_mmregs): ... this.
 668         (condition_codes): Rename to ...
 669         (tic54x_condition_codes): ... this.
 670         (cc2_codes): Rename to ...
 671         (tic54x_cc2_codes): ... this.
 672         (cc3_codes): Rename to ...
 673         (tic54x_cc3_codes): ... this.
 674         (status_bits): Rename to ...
 675         (tic54x_status_bits): ... this.
 676         (misc_symbols): Rename to ...
 677         (tic54x_misc_symbols): ... this.
 678
 679 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 680
 681         * riscv-opc.c (MASK_RVB_IMM): Removed.
 682         (riscv_opcodes): Removed zb* instructions.
 683         (riscv_ext_version_table): Removed versions for zb*.
 684
 685 2021-01-26  Alan Modra  <amodra@gmail.com>
 686
 687         * i386-gen.c (parse_template): Ensure entire template_instance
 688         is initialised.
 689
 690 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 691
 692         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 693         (riscv_fpr_names_abi): Likewise.
 694         (riscv_opcodes): Likewise.
 695         (riscv_insn_types): Likewise.
 696
 697 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 698
 699         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 700
 701 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 702
 703         * riscv-dis.c: Comments tidy and improvement.
 704         * riscv-opc.c: Likewise.
 705
 706 2021-01-13  Alan Modra  <amodra@gmail.com>
 707
 708         * Makefile.in: Regenerate.
 709
 710 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 711
 712         PR binutils/26792
 713         * configure.ac: Use GNU_MAKE_JOBSERVER.
 714         * aclocal.m4: Regenerated.
 715         * configure: Likewise.
 716
 717 2021-01-12  Nick Clifton  <nickc@redhat.com>
 718
 719         * po/sr.po: Updated Serbian translation.
 720
 721 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         PR ld/27173
 724         * configure: Regenerated.
 725
 726 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 727
 728         * aarch64-asm-2.c: Regenerate.
 729         * aarch64-dis-2.c: Likewise.
 730         * aarch64-opc-2.c: Likewise.
 731         * aarch64-opc.c (aarch64_print_operand):
 732         Delete handling of AARCH64_OPND_CSRE_CSR.
 733         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 734         (CSRE): Likewise.
 735         (_CSRE_INSN): Likewise.
 736         (aarch64_opcode_table): Delete csr.
 737
 738 2021-01-11  Nick Clifton  <nickc@redhat.com>
 739
 740         * po/de.po: Updated German translation.
 741         * po/fr.po: Updated French translation.
 742         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 743         * po/sv.po: Updated Swedish translation.
 744         * po/uk.po: Updated Ukranian translation.
 745
 746 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 747
 748         * configure: Regenerated.
 749
 750 2021-01-09  Nick Clifton  <nickc@redhat.com>
 751
 752         * configure: Regenerate.
 753         * po/opcodes.pot: Regenerate.
 754
 755 2021-01-09  Nick Clifton  <nickc@redhat.com>
 756
 757         * 2.36 release branch crated.
 758
 759 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 760
 761         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 762         (DW, (XRC_MASK): Define.
 763         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 764
 765 2021-01-09  Alan Modra  <amodra@gmail.com>
 766
 767         * configure: Regenerate.
 768
 769 2021-01-08  Nick Clifton  <nickc@redhat.com>
 770
 771         * po/sv.po: Updated Swedish translation.
 772
 773 2021-01-08  Nick Clifton  <nickc@redhat.com>
 774
 775         PR 27129
 776         * aarch64-dis.c (determine_disassembling_preference): Move call to
 777         aarch64_match_operands_constraint outside of the assertion.
 778         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 779         Replace with a return of FALSE.
 780
 781         PR 27139
 782         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 783         core system register.
 784
 785 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 786
 787         * configure: Regenerate.
 788
 789 2021-01-07  Nick Clifton  <nickc@redhat.com>
 790
 791         * po/fr.po: Updated French translation.
 792
 793 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 794
 795         * m68k-opc.c (chkl): Change minimum architecture requirement to
 796         m68020.
 797
 798 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 799
 800         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 801
 802 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 803             Jim Wilson  <jimw@sifive.com>
 804             Andrew Waterman  <andrew@sifive.com>
 805             Maxim Blinov  <maxim.blinov@embecosm.com>
 806             Kito Cheng  <kito.cheng@sifive.com>
 807             Nelson Chu  <nelson.chu@sifive.com>
 808
 809         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 810         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 811
 812 2021-01-01  Alan Modra  <amodra@gmail.com>
 813
 814         Update year range in copyright notice of all files.
 815
 816 For older changes see ChangeLog-2020
 817 \f
 818 Copyright (C) 2021 Free Software Foundation, Inc.
 819
 820 Copying and distribution of this file, with or without modification,
 821 are permitted in any medium without royalty provided the copyright
 822 notice and this notice are preserved.
 823
 824 Local Variables:
 825 mode: change-log
 826 left-margin: 8
 827 fill-column: 74
 828 version-control: never
 829 End: