1 2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
3 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
4 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
7 2020-09-10 Nick Clifton <nickc@redhat.com>
9 * csky-dis.c (csky_output_operand): Coerce the immediate values to
12 2020-09-10 Alan Modra <amodra@gmail.com>
14 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
16 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
18 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
21 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
23 * csky-dis.c (csky_output_operand): Add handlers for
24 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
25 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
26 to support FPUV3 instructions.
27 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
28 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
29 OPRND_TYPE_DFLOAT_FMOVI.
30 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
31 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
32 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
33 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
34 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
35 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
36 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
37 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
38 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
39 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
40 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
41 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
42 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
43 (csky_v2_opcodes): Add FPUV3 instructions.
45 2020-09-08 Alex Coplan <alex.coplan@arm.com>
47 * aarch64-dis.c (print_operands): Pass CPU features to
48 aarch64_print_operand().
49 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
50 preferred disassembly of system registers.
51 (SR_RNG): Refactor to use new SR_FEAT2 macro.
58 (SR_EXPAND_EL12): New.
59 (aarch64_sys_regs): Specify which registers are only on
60 A-profile, add R-profile system registers.
64 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
67 2020-09-08 Alex Coplan <alex.coplan@arm.com>
69 * aarch64-tbl.h (aarch64_feature_v8_r): New.
72 (aarch64_opcode_table): Add dfb.
73 * aarch64-opc-2.c: Regenerate.
74 * aarch64-asm-2.c: Regenerate.
75 * aarch64-dis-2.c: Regenerate.
77 2020-09-08 Alex Coplan <alex.coplan@arm.com>
79 * aarch64-dis.c (arch_variant): New.
80 (determine_disassembling_preference): Disassemble according to
82 (select_aarch64_variant): New.
83 (print_insn_aarch64): Set feature set.
85 2020-09-02 Alan Modra <amodra@gmail.com>
87 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
88 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
89 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
90 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
91 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
92 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
93 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
94 for value parameter and update code to suit.
95 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
96 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
98 2020-09-02 Alan Modra <amodra@gmail.com>
100 * i386-dis.c (OP_E_memory): Don't cast to signed type when
102 (get32, get32s): Use unsigned types in shift expressions.
104 2020-09-02 Alan Modra <amodra@gmail.com>
106 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
108 2020-09-02 Alan Modra <amodra@gmail.com>
110 * crx-dis.c: Whitespace.
111 (print_arg): Use unsigned type for longdisp and mask variables,
112 and for left shift constant.
114 2020-09-02 Alan Modra <amodra@gmail.com>
116 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
117 * bpf-ibld.c: Regenerate.
118 * epiphany-ibld.c: Regenerate.
119 * fr30-ibld.c: Regenerate.
120 * frv-ibld.c: Regenerate.
121 * ip2k-ibld.c: Regenerate.
122 * iq2000-ibld.c: Regenerate.
123 * lm32-ibld.c: Regenerate.
124 * m32c-ibld.c: Regenerate.
125 * m32r-ibld.c: Regenerate.
126 * mep-ibld.c: Regenerate.
127 * mt-ibld.c: Regenerate.
128 * or1k-ibld.c: Regenerate.
129 * xc16x-ibld.c: Regenerate.
130 * xstormy16-ibld.c: Regenerate.
132 2020-09-02 Alan Modra <amodra@gmail.com>
134 * bfin-dis.c (MASKBITS): Use SIGNBIT.
136 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
138 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
139 to CSKYV2_ISA_3E3R3 instruction set.
141 2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
143 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
145 2020-09-01 Alan Modra <amodra@gmail.com>
147 * mep-ibld.c: Regenerate.
149 2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
151 * csky-dis.c (csky_output_operand): Assign dis_info.value for
154 2020-08-30 Alan Modra <amodra@gmail.com>
156 * cr16-dis.c: Formatting.
157 (parameter): Delete struct typedef. Use dwordU instead
159 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
161 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
163 2020-08-29 Alan Modra <amodra@gmail.com>
166 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
167 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
169 2020-08-28 Alan Modra <amodra@gmail.com>
173 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
174 (extract_normal): Likewise.
175 (insert_normal): Likewise, and move past zero length test.
176 (put_insn_int_value): Handle mask for zero length, use 1UL.
177 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
178 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
179 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
180 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
182 2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
184 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
185 (csky_dis_info): Add member isa.
186 (csky_find_inst_info): Skip instructions that do not belong to
188 (csky_get_disassembler): Get infomation from attribute section.
189 (print_insn_csky): Set defualt ISA flag.
190 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
191 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
192 isa_flag32'type to unsigned 64 bits.
194 2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
196 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
198 2020-08-26 David Faust <david.faust@oracle.com>
200 * bpf-desc.c: Regenerate.
201 * bpf-desc.h: Likewise.
202 * bpf-opc.c: Likewise.
203 * bpf-opc.h: Likewise.
204 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
205 ISA when appropriate.
207 2020-08-25 Alan Modra <amodra@gmail.com>
210 * vax-dis.c (parse_disassembler_options): Always add at least one
211 to entry_addr_total_slots.
213 2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
215 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
216 in other CPUs to speed up disassembling.
217 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
218 Change plsli.u16 to plsli.16, change sync's operand format.
220 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
222 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
224 2020-08-21 Nick Clifton <nickc@redhat.com>
226 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
229 2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
231 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
233 2020-08-19 Alan Modra <amodra@gmail.com>
235 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
238 2020-08-18 Peter Bergner <bergner@linux.ibm.com>
240 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
241 <xvcvbf16spn>: ...to this.
243 2020-08-12 Alex Coplan <alex.coplan@arm.com>
245 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
247 2020-08-12 Nick Clifton <nickc@redhat.com>
249 * po/sr.po: Updated Serbian translation.
251 2020-08-11 Alan Modra <amodra@gmail.com>
253 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
255 2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
257 * aarch64-opc.c (aarch64_print_operand):
258 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
259 (aarch64_sys_reg_supported_p): Function removed.
260 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
261 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
264 2020-08-10 Alan Modra <amodra@gmail.com>
266 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
269 2020-08-10 Alan Modra <amodra@gmail.com>
271 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
272 Enable icbt for power5, miso for power8.
274 2020-08-10 Alan Modra <amodra@gmail.com>
276 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
277 mtvsrd, and similarly for mfvsrd.
279 2020-08-04 Christian Groessler <chris@groessler.org>
280 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
282 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
283 opcodes (special "out" to absolute address).
284 * z8k-opc.h: Regenerate.
286 2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
289 * i386-opc.h (Prefix_Disp8): New.
290 (Prefix_Disp16): Likewise.
291 (Prefix_Disp32): Likewise.
292 (Prefix_Load): Likewise.
293 (Prefix_Store): Likewise.
294 (Prefix_VEX): Likewise.
295 (Prefix_VEX3): Likewise.
296 (Prefix_EVEX): Likewise.
297 (Prefix_REX): Likewise.
298 (Prefix_NoOptimize): Likewise.
299 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
300 * i386-tbl.h: Regenerated.
302 2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
304 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
305 default case with abort() instead of printing an error message and
306 continuing, to avoid a maybe-uninitialized warning.
308 2020-07-24 Nick Clifton <nickc@redhat.com>
310 * po/de.po: Updated German translation.
312 2020-07-21 Jan Beulich <jbeulich@suse.com>
314 * i386-dis.c (OP_E_memory): Revert previous change.
316 2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
319 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
320 without base nor index registers.
322 2020-07-15 Jan Beulich <jbeulich@suse.com>
324 * i386-dis.c (putop): Move 'V' and 'W' handling.
326 2020-07-15 Jan Beulich <jbeulich@suse.com>
328 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
329 construct for push/pop of register.
330 (putop): Honor cond when handling 'P'. Drop handling of plain
333 2020-07-15 Jan Beulich <jbeulich@suse.com>
335 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
336 description. Drop '&' description. Use P for push of immediate,
337 pushf/popf, enter, and leave. Use %LP for lret/retf.
338 (dis386_twobyte): Use P for push/pop of fs/gs.
339 (reg_table): Use P for push/pop. Use @ for near call/jmp.
340 (x86_64_table): Use P for far call/jmp.
341 (putop): Drop handling of 'U' and '&'. Move and adjust handling
342 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
344 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
345 and dqw_mode (unconditional).
347 2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
350 * i386-dis.c (OP_E_memory): Without base nor index registers,
351 32-bit displacement to 64 bits.
353 2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
355 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
356 faulty double register pair is detected.
358 2020-07-14 Jan Beulich <jbeulich@suse.com>
360 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
362 2020-07-14 Jan Beulich <jbeulich@suse.com>
364 * i386-dis.c (OP_R, Rm): Delete.
365 (MOD_0F24, MOD_0F26): Rename to ...
366 (X86_64_0F24, X86_64_0F26): ... respectively.
367 (dis386): Update 'L' and 'Z' comments.
368 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
370 (mod_table): Move opcode 0F24 and 0F26 entries ...
371 (x86_64_table): ... here.
372 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
375 2020-07-14 Jan Beulich <jbeulich@suse.com>
377 * i386-dis.c (Rd, Rdq, MaskR): Delete.
378 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
379 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
380 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
381 MOD_EVEX_0F387C): New enumerators.
382 (reg_table): Use Edq for rdssp.
383 (prefix_table): Use Edq for incssp.
384 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
385 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
386 ktest*, and kshift*. Use Edq / MaskE for kmov*.
387 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
388 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
389 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
390 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
391 0F3828_P_1 and 0F3838_P_1.
392 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
393 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
395 2020-07-14 Jan Beulich <jbeulich@suse.com>
397 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
398 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
399 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
400 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
401 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
402 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
403 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
404 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
405 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
406 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
407 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
408 (reg_table, prefix_table, three_byte_table, vex_table,
409 vex_len_table, mod_table, rm_table): Replace / remove respective
411 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
412 of PREFIX_DATA in used_prefixes.
414 2020-07-14 Jan Beulich <jbeulich@suse.com>
416 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
417 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
418 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
419 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
420 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
421 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
422 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
423 VEX_W_0F3A33_L_0): Delete.
424 (dis386): Adjust "BW" description.
425 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
426 0F3A31, 0F3A32, and 0F3A33.
427 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
429 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
432 2020-07-14 Jan Beulich <jbeulich@suse.com>
434 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
435 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
436 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
437 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
438 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
439 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
440 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
441 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
442 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
443 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
444 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
445 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
446 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
447 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
448 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
449 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
450 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
451 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
452 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
453 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
454 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
455 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
456 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
457 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
458 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
459 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
460 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
461 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
462 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
463 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
464 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
465 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
466 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
467 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
468 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
469 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
470 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
471 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
472 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
473 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
474 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
475 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
476 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
477 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
478 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
479 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
480 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
481 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
482 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
483 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
484 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
485 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
486 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
487 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
488 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
489 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
490 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
491 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
492 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
493 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
494 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
495 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
496 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
497 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
498 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
499 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
500 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
501 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
502 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
503 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
504 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
505 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
506 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
507 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
508 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
509 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
510 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
511 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
512 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
513 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
514 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
515 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
516 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
517 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
518 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
519 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
520 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
521 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
522 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
523 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
524 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
525 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
526 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
527 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
528 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
529 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
530 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
531 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
532 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
533 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
534 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
535 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
536 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
537 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
538 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
539 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
540 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
541 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
542 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
543 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
544 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
545 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
546 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
547 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
548 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
549 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
550 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
551 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
552 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
553 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
554 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
555 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
556 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
557 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
558 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
559 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
560 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
561 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
562 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
563 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
564 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
565 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
566 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
567 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
568 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
569 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
570 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
571 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
572 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
573 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
574 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
575 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
576 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
577 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
578 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
579 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
580 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
581 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
582 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
583 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
584 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
585 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
586 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
587 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
588 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
589 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
590 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
591 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
592 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
593 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
594 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
595 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
596 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
597 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
598 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
599 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
600 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
601 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
602 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
603 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
604 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
605 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
606 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
607 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
608 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
609 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
610 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
611 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
612 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
613 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
614 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
615 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
616 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
617 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
618 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
619 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
620 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
621 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
622 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
623 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
624 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
625 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
626 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
627 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
628 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
629 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
630 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
631 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
632 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
633 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
634 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
635 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
636 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
637 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
638 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
639 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
640 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
641 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
642 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
643 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
644 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
645 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
646 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
647 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
648 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
649 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
650 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
651 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
652 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
653 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
654 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
655 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
656 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
657 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
658 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
659 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
660 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
661 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
662 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
663 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
664 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
665 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
666 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
667 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
668 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
669 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
670 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
671 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
672 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
673 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
674 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
675 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
676 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
677 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
678 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
679 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
680 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
681 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
682 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
683 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
684 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
685 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
686 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
687 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
688 EVEX_W_0F3A72_P_2): Rename to ...
689 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
690 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
691 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
692 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
693 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
694 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
695 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
696 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
697 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
698 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
699 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
700 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
701 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
702 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
703 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
704 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
705 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
706 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
707 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
708 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
709 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
710 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
711 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
712 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
713 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
714 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
715 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
716 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
717 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
718 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
719 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
720 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
721 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
722 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
723 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
724 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
725 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
726 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
727 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
728 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
729 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
730 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
731 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
732 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
733 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
734 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
735 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
736 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
737 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
738 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
739 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
740 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
741 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
742 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
743 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
744 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
745 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
746 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
747 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
748 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
749 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
750 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
751 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
752 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
753 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
754 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
755 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
756 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
757 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
758 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
759 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
760 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
762 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
763 vex_w_table, mod_table): Replace / remove respective entries.
764 (print_insn): Move up dp->prefix_requirement handling. Handle
766 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
767 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
768 Replace / remove respective entries.
770 2020-07-14 Jan Beulich <jbeulich@suse.com>
772 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
773 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
774 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
775 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
776 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
778 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
779 0F2C, 0F2D, 0F2E, and 0F2F.
780 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
783 2020-07-14 Jan Beulich <jbeulich@suse.com>
785 * i386-dis.c (OP_VexR, VexScalarR): New.
786 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
787 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
788 need_vex_reg): Delete.
789 (prefix_table): Replace VexScalar by VexScalarR and
790 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
791 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
792 (vex_len_table): Replace EXqVexScalarS by EXqS.
793 (get_valid_dis386): Don't set need_vex_reg.
794 (print_insn): Don't initialize need_vex_reg.
795 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
796 q_scalar_swap_mode cases.
797 (OP_EX): Don't check for d_scalar_swap_mode and
799 (OP_VEX): Done check need_vex_reg.
800 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
801 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
802 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
804 2020-07-14 Jan Beulich <jbeulich@suse.com>
806 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
807 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
808 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
809 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
810 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
811 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
812 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
813 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
814 (vex_table): Replace Vex128 by Vex.
815 (vex_len_table): Likewise. Adjust referenced enum names.
816 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
817 referenced enum names.
818 (OP_VEX): Drop vex128_mode and vex256_mode cases.
819 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
821 2020-07-14 Jan Beulich <jbeulich@suse.com>
823 * i386-dis.c (dis386): "LW" description now applies to "DQ".
824 (putop): Handle "DQ". Don't handle "LW" anymore.
825 (prefix_table, mod_table): Replace %LW by %DQ.
826 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
828 2020-07-14 Jan Beulich <jbeulich@suse.com>
830 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
831 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
832 d_scalar_swap_mode case handling. Move shift adjsutment into
833 the case its applicable to.
835 2020-07-14 Jan Beulich <jbeulich@suse.com>
837 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
838 (EXbScalar, EXwScalar): Fold to ...
839 (EXbwUnit): ... this.
840 (b_scalar_mode, w_scalar_mode): Fold to ...
841 (bw_unit_mode): ... this.
842 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
843 w_scalar_mode handling by bw_unit_mode one.
844 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
846 * i386-dis-evex-prefix.h: ... here.
848 2020-07-14 Jan Beulich <jbeulich@suse.com>
850 * i386-dis.c (PCMPESTR_Fixup): Delete.
851 (dis386): Adjust "LQ" description.
852 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
853 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
854 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
855 vpcmpestrm, and vpcmpestri.
856 (putop): Honor "cond" when handling LQ.
857 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
858 vcvtsi2ss and vcvtusi2ss.
859 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
860 vcvtsi2sd and vcvtusi2sd.
862 2020-07-14 Jan Beulich <jbeulich@suse.com>
864 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
865 (simd_cmp_op): Add const.
866 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
867 (CMP_Fixup): Handle VEX case.
868 (prefix_table): Replace VCMP by CMP.
869 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
871 2020-07-14 Jan Beulich <jbeulich@suse.com>
873 * i386-dis.c (MOVBE_Fixup): Delete.
875 (prefix_table): Use Mv for movbe entries.
877 2020-07-14 Jan Beulich <jbeulich@suse.com>
879 * i386-dis.c (CRC32_Fixup): Delete.
880 (prefix_table): Use Eb/Ev for crc32 entries.
882 2020-07-14 Jan Beulich <jbeulich@suse.com>
884 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
885 Conditionalize invocations of "USED_REX (0)".
887 2020-07-14 Jan Beulich <jbeulich@suse.com>
889 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
890 CH, DH, BH, AX, DX): Delete.
891 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
892 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
893 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
895 2020-07-10 Lili Cui <lili.cui@intel.com>
897 * i386-dis.c (TMM): New.
900 (MVexSIBMEM): Likewise.
901 (tmm_mode): Likewise.
902 (vex_sibmem_mode): Likewise.
903 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
904 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
905 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
906 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
907 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
908 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
909 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
910 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
911 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
912 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
913 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
914 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
915 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
916 (PREFIX_VEX_0F3849_X86_64): Likewise.
917 (PREFIX_VEX_0F384B_X86_64): Likewise.
918 (PREFIX_VEX_0F385C_X86_64): Likewise.
919 (PREFIX_VEX_0F385E_X86_64): Likewise.
920 (X86_64_VEX_0F3849): Likewise.
921 (X86_64_VEX_0F384B): Likewise.
922 (X86_64_VEX_0F385C): Likewise.
923 (X86_64_VEX_0F385E): Likewise.
924 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
925 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
926 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
927 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
928 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
929 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
930 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
931 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
932 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
933 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
934 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
935 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
936 (VEX_W_0F3849_X86_64_P_0): Likewise.
937 (VEX_W_0F3849_X86_64_P_2): Likewise.
938 (VEX_W_0F3849_X86_64_P_3): Likewise.
939 (VEX_W_0F384B_X86_64_P_1): Likewise.
940 (VEX_W_0F384B_X86_64_P_2): Likewise.
941 (VEX_W_0F384B_X86_64_P_3): Likewise.
942 (VEX_W_0F385C_X86_64_P_1): Likewise.
943 (VEX_W_0F385E_X86_64_P_0): Likewise.
944 (VEX_W_0F385E_X86_64_P_1): Likewise.
945 (VEX_W_0F385E_X86_64_P_2): Likewise.
946 (VEX_W_0F385E_X86_64_P_3): Likewise.
947 (names_tmm): Likewise.
948 (att_names_tmm): Likewise.
949 (intel_operand_size): Handle void_mode.
950 (OP_XMM): Handle tmm_mode.
953 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
954 CpuAMX_BF16 and CpuAMX_TILE.
955 (operand_type_shorthands): Add RegTMM.
956 (operand_type_init): Likewise.
957 (operand_types): Add Tmmword.
958 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
959 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
960 * i386-opc.h (CpuAMX_INT8): New.
961 (CpuAMX_BF16): Likewise.
962 (CpuAMX_TILE): Likewise.
965 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
966 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
967 (i386_operand_type): Add tmmword.
968 * i386-opc.tbl: Add AMX instructions.
969 * i386-reg.tbl: Add AMX registers.
970 * i386-init.h: Regenerated.
971 * i386-tbl.h: Likewise.
973 2020-07-08 Jan Beulich <jbeulich@suse.com>
975 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
976 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
978 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
979 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
981 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
982 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
983 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
984 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
985 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
986 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
987 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
988 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
989 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
990 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
991 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
992 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
993 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
994 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
995 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
996 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
997 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
998 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
999 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1000 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1001 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1002 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1003 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1004 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1005 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1006 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1007 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1008 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1009 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1010 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1011 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1012 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1013 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1014 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1015 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1016 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1017 (reg_table): Re-order XOP entries. Adjust their operands.
1018 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1019 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1020 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1021 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1022 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1023 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1024 entries by references ...
1025 (vex_len_table): ... to resepctive new entries here. For several
1026 new and existing entries reference ...
1027 (vex_w_table): ... new entries here.
1028 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1030 2020-07-08 Jan Beulich <jbeulich@suse.com>
1032 * i386-dis.c (XMVexScalarI4): Define.
1033 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1034 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1035 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1036 (vex_len_table): Move scalar FMA4 entries ...
1037 (prefix_table): ... here.
1038 (OP_REG_VexI4): Handle scalar_mode.
1039 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1040 * i386-tbl.h: Re-generate.
1042 2020-07-08 Jan Beulich <jbeulich@suse.com>
1044 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1045 Vex_2src_2): Delete.
1046 (OP_VexW, VexW): New.
1047 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1048 for shifts and rotates by register.
1050 2020-07-08 Jan Beulich <jbeulich@suse.com>
1052 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1053 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1054 OP_EX_VexReg): Delete.
1055 (OP_VexI4, VexI4): New.
1056 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1057 (prefix_table): ... here.
1058 (print_insn): Drop setting of vex_w_done.
1060 2020-07-08 Jan Beulich <jbeulich@suse.com>
1062 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1063 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1064 (xop_table): Replace operands of 4-operand insns.
1065 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1067 2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1069 * arc-opc.c (insert_rbd): New function.
1072 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1075 2020-07-07 Jan Beulich <jbeulich@suse.com>
1077 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1078 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1079 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1080 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1082 (putop): Handle "BW".
1083 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1084 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1086 * i386-dis-evex-prefix.h: ... here.
1088 2020-07-06 Jan Beulich <jbeulich@suse.com>
1090 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1091 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1092 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1093 VEX_W_0FXOP_09_83): New enumerators.
1094 (xop_table): Reference the above.
1095 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1096 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1097 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1098 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1100 2020-07-06 Jan Beulich <jbeulich@suse.com>
1102 * i386-dis.c (EVEX_W_0F3838_P_1,
1103 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1104 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1105 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1106 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1107 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1108 (putop): Centralize management of last[]. Delete SAVE_LAST.
1109 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1110 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1111 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1112 * i386-dis-evex-prefix.h: here.
1114 2020-07-06 Jan Beulich <jbeulich@suse.com>
1116 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1117 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1118 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1119 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1121 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1122 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1123 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1124 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1125 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1126 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1127 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1128 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1129 these, respectively.
1130 * i386-dis-evex-len.h: Adjust comments.
1131 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1132 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1133 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1134 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1135 MOD_EVEX_0F385B_P_2_W_1 table entries.
1136 * i386-dis-evex-w.h: Reference mod_table[] for
1137 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1140 2020-07-06 Jan Beulich <jbeulich@suse.com>
1142 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1143 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1145 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1146 Likewise. Mark 256-bit entries invalid.
1148 2020-07-06 Jan Beulich <jbeulich@suse.com>
1150 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1151 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1152 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1153 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1154 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1155 PREFIX_EVEX_0F382B): Delete.
1156 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1157 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1158 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1159 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1160 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1162 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1163 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1164 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1165 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1167 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1168 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1169 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1170 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1171 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1172 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1173 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1174 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1175 PREFIX_EVEX_0F382B): Remove table entries.
1176 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1177 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1178 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1180 2020-07-06 Jan Beulich <jbeulich@suse.com>
1182 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1183 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1185 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1186 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1187 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1188 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1191 2020-07-06 Jan Beulich <jbeulich@suse.com>
1193 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1194 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1195 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1196 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1197 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1198 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1199 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1200 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1201 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1204 2020-07-06 Jan Beulich <jbeulich@suse.com>
1206 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1207 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1208 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1210 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1212 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1214 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1216 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1218 2020-07-06 Jan Beulich <jbeulich@suse.com>
1220 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1221 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1222 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1223 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1224 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1225 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1226 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1227 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1228 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1229 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1230 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1231 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1232 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1233 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1234 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1235 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1236 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1237 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1238 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1239 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1240 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1241 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1242 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1243 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1244 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1245 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1246 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1247 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1248 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1249 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1250 (prefix_table): Add EXxEVexR to FMA table entries.
1251 (OP_Rounding): Move abort() invocation.
1252 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1253 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1254 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1255 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1256 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1257 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1258 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1259 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1260 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1261 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1263 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1264 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1265 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1266 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1267 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1268 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1269 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1270 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1271 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1272 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1273 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1274 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1275 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1276 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1277 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1278 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1279 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1280 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1281 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1282 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1283 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1284 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1285 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1286 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1287 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1288 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1289 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1290 Delete table entries.
1291 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1292 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1293 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1296 2020-07-06 Jan Beulich <jbeulich@suse.com>
1298 * i386-dis.c (EXqScalarS): Delete.
1299 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1300 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1302 2020-07-06 Jan Beulich <jbeulich@suse.com>
1304 * i386-dis.c (safe-ctype.h): Include.
1305 (EXdScalar, EXqScalar): Delete.
1306 (d_scalar_mode, q_scalar_mode): Delete.
1307 (prefix_table, vex_len_table): Use EXxmm_md in place of
1308 EXdScalar and EXxmm_mq in place of EXqScalar.
1309 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1310 d_scalar_mode and q_scalar_mode.
1311 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1312 (vmovsd): Use EXxmm_mq.
1314 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1317 * arc-dis.c: Fix spelling mistake.
1318 * po/opcodes.pot: Regenerate.
1320 2020-07-06 Nick Clifton <nickc@redhat.com>
1322 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1323 * po/uk.po: Updated Ukranian translation.
1325 2020-07-04 Nick Clifton <nickc@redhat.com>
1327 * configure: Regenerate.
1328 * po/opcodes.pot: Regenerate.
1330 2020-07-04 Nick Clifton <nickc@redhat.com>
1332 Binutils 2.35 branch created.
1334 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1336 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1337 * i386-opc.h (VexSwapSources): New.
1338 (i386_opcode_modifier): Add vexswapsources.
1339 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1340 with two source operands swapped.
1341 * i386-tbl.h: Regenerated.
1343 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
1345 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1346 unprivileged CSR can also be initialized.
1348 2020-06-29 Alan Modra <amodra@gmail.com>
1350 * arm-dis.c: Use C style comments.
1351 * cr16-opc.c: Likewise.
1352 * ft32-dis.c: Likewise.
1353 * moxie-opc.c: Likewise.
1354 * tic54x-dis.c: Likewise.
1355 * s12z-opc.c: Remove useless comment.
1356 * xgate-dis.c: Likewise.
1358 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1360 * i386-opc.tbl: Add a blank line.
1362 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1364 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1365 (VecSIB128): Renamed to ...
1367 (VecSIB256): Renamed to ...
1369 (VecSIB512): Renamed to ...
1371 (VecSIB): Renamed to ...
1373 (i386_opcode_modifier): Replace vecsib with sib.
1374 * i386-opc.tbl (VecSIB128): New.
1375 (VecSIB256): Likewise.
1376 (VecSIB512): Likewise.
1377 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
1378 and VecSIB512, respectively.
1380 2020-06-26 Jan Beulich <jbeulich@suse.com>
1382 * i386-dis.c: Adjust description of I macro.
1383 (x86_64_table): Drop use of I.
1384 (float_mem): Replace use of I.
1385 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1387 2020-06-26 Jan Beulich <jbeulich@suse.com>
1389 * i386-dis.c: (print_insn): Avoid straight assignment to
1390 priv.orig_sizeflag when processing -M sub-options.
1392 2020-06-25 Jan Beulich <jbeulich@suse.com>
1394 * i386-dis.c: Adjust description of J macro.
1395 (dis386, x86_64_table, mod_table): Replace J.
1396 (putop): Remove handling of J.
1398 2020-06-25 Jan Beulich <jbeulich@suse.com>
1400 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1402 2020-06-25 Jan Beulich <jbeulich@suse.com>
1404 * i386-dis.c: Adjust description of "LQ" macro.
1405 (dis386_twobyte): Use LQ for sysret.
1406 (putop): Adjust handling of LQ.
1408 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
1410 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1411 * riscv-dis.c: Include elfxx-riscv.h.
1413 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1415 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1417 2020-06-17 Lili Cui <lili.cui@intel.com>
1419 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1421 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1424 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1425 * i386-opc.tbl: Likewise.
1426 * i386-tbl.h: Regenerated.
1428 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
1430 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1432 2020-06-11 Alex Coplan <alex.coplan@arm.com>
1434 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1435 (SR_CORE): Likewise.
1436 (SR_FEAT): Likewise.
1438 (SR_V8_1): Likewise.
1439 (SR_V8_2): Likewise.
1440 (SR_V8_3): Likewise.
1441 (SR_V8_4): Likewise.
1444 (SR_SSBS): Likewise.
1446 (SR_ID_PFR2): Likewise.
1447 (SR_PROFILE): Likewise.
1448 (SR_MEMTAG): Likewise.
1449 (SR_SCXTNUM): Likewise.
1450 (aarch64_sys_regs): Refactor to store feature information in the table.
1451 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1452 that now describe their own features.
1453 (aarch64_pstatefield_supported_p): Likewise.
1455 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1457 * i386-dis.c (prefix_table): Fix a typo in comments.
1459 2020-06-09 Jan Beulich <jbeulich@suse.com>
1461 * i386-dis.c (rex_ignored): Delete.
1462 (ckprefix): Drop rex_ignored initialization.
1463 (get_valid_dis386): Drop setting of rex_ignored.
1464 (print_insn): Drop checking of rex_ignored. Don't record data
1465 size prefix as used with VEX-and-alike encodings.
1467 2020-06-09 Jan Beulich <jbeulich@suse.com>
1469 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1470 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1471 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1472 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1473 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1474 VEX_0F12, and VEX_0F16.
1475 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1476 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1477 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1478 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1479 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1480 MOD_VEX_0F16_PREFIX_2 entries.
1482 2020-06-09 Jan Beulich <jbeulich@suse.com>
1484 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1485 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1486 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1487 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1488 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1489 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1490 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1491 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1492 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1493 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1494 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1495 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1496 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1497 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1498 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1499 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1500 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1501 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1502 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1503 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1504 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1505 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1506 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1507 EVEX_W_0FC6_P_2): Delete.
1508 (print_insn): Add EVEX.W vs embedded prefix consistency check
1509 to prefix validation.
1510 * i386-dis-evex.h (evex_table): Don't further descend for
1511 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1512 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1514 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1515 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1516 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1517 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1518 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1519 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1520 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1521 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1522 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1523 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1524 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1525 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1526 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1527 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1528 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1529 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1530 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1531 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1532 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1533 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1534 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1535 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1536 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1537 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1538 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1539 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1540 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1542 2020-06-09 Jan Beulich <jbeulich@suse.com>
1544 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1545 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1546 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1548 (print_insn): Drop pointless check against bad_opcode. Split
1549 prefix validation into legacy and VEX-and-alike parts.
1550 (putop): Re-work 'X' macro handling.
1552 2020-06-09 Jan Beulich <jbeulich@suse.com>
1554 * i386-dis.c (MOD_0F51): Rename to ...
1555 (MOD_0F50): ... this.
1557 2020-06-08 Alex Coplan <alex.coplan@arm.com>
1559 * arm-dis.c (arm_opcodes): Add dfb.
1560 (thumb32_opcodes): Add dfb.
1562 2020-06-08 Jan Beulich <jbeulich@suse.com>
1564 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1566 2020-06-06 Alan Modra <amodra@gmail.com>
1568 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1570 2020-06-05 Alan Modra <amodra@gmail.com>
1572 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1573 size is large enough.
1575 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1577 * disassemble.c (disassemble_init_for_target): Set endian_code for
1579 * bpf-desc.c: Regenerate.
1580 * bpf-opc.c: Likewise.
1581 * bpf-dis.c: Likewise.
1583 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1585 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1586 (cgen_put_insn_value): Likewise.
1587 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1588 * cgen-dis.in (print_insn): Likewise.
1589 * cgen-ibld.in (insert_1): Likewise.
1590 (insert_1): Likewise.
1591 (insert_insn_normal): Likewise.
1592 (extract_1): Likewise.
1593 * bpf-dis.c: Regenerate.
1594 * bpf-ibld.c: Likewise.
1595 * bpf-ibld.c: Likewise.
1596 * cgen-dis.in: Likewise.
1597 * cgen-ibld.in: Likewise.
1598 * cgen-opc.c: Likewise.
1599 * epiphany-dis.c: Likewise.
1600 * epiphany-ibld.c: Likewise.
1601 * fr30-dis.c: Likewise.
1602 * fr30-ibld.c: Likewise.
1603 * frv-dis.c: Likewise.
1604 * frv-ibld.c: Likewise.
1605 * ip2k-dis.c: Likewise.
1606 * ip2k-ibld.c: Likewise.
1607 * iq2000-dis.c: Likewise.
1608 * iq2000-ibld.c: Likewise.
1609 * lm32-dis.c: Likewise.
1610 * lm32-ibld.c: Likewise.
1611 * m32c-dis.c: Likewise.
1612 * m32c-ibld.c: Likewise.
1613 * m32r-dis.c: Likewise.
1614 * m32r-ibld.c: Likewise.
1615 * mep-dis.c: Likewise.
1616 * mep-ibld.c: Likewise.
1617 * mt-dis.c: Likewise.
1618 * mt-ibld.c: Likewise.
1619 * or1k-dis.c: Likewise.
1620 * or1k-ibld.c: Likewise.
1621 * xc16x-dis.c: Likewise.
1622 * xc16x-ibld.c: Likewise.
1623 * xstormy16-dis.c: Likewise.
1624 * xstormy16-ibld.c: Likewise.
1626 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1628 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1629 (print_insn_): Handle instruction endian.
1630 * bpf-dis.c: Regenerate.
1631 * bpf-desc.c: Regenerate.
1632 * epiphany-dis.c: Likewise.
1633 * epiphany-desc.c: Likewise.
1634 * fr30-dis.c: Likewise.
1635 * fr30-desc.c: Likewise.
1636 * frv-dis.c: Likewise.
1637 * frv-desc.c: Likewise.
1638 * ip2k-dis.c: Likewise.
1639 * ip2k-desc.c: Likewise.
1640 * iq2000-dis.c: Likewise.
1641 * iq2000-desc.c: Likewise.
1642 * lm32-dis.c: Likewise.
1643 * lm32-desc.c: Likewise.
1644 * m32c-dis.c: Likewise.
1645 * m32c-desc.c: Likewise.
1646 * m32r-dis.c: Likewise.
1647 * m32r-desc.c: Likewise.
1648 * mep-dis.c: Likewise.
1649 * mep-desc.c: Likewise.
1650 * mt-dis.c: Likewise.
1651 * mt-desc.c: Likewise.
1652 * or1k-dis.c: Likewise.
1653 * or1k-desc.c: Likewise.
1654 * xc16x-dis.c: Likewise.
1655 * xc16x-desc.c: Likewise.
1656 * xstormy16-dis.c: Likewise.
1657 * xstormy16-desc.c: Likewise.
1659 2020-06-03 Nick Clifton <nickc@redhat.com>
1661 * po/sr.po: Updated Serbian translation.
1663 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
1665 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1666 (riscv_get_priv_spec_class): Likewise.
1668 2020-06-01 Alan Modra <amodra@gmail.com>
1670 * bpf-desc.c: Regenerate.
1672 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1673 David Faust <david.faust@oracle.com>
1675 * bpf-desc.c: Regenerate.
1676 * bpf-opc.h: Likewise.
1677 * bpf-opc.c: Likewise.
1678 * bpf-dis.c: Likewise.
1680 2020-05-28 Alan Modra <amodra@gmail.com>
1682 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1685 2020-05-28 Alan Modra <amodra@gmail.com>
1687 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1689 (print_insn_ns32k): Revert last change.
1691 2020-05-28 Nick Clifton <nickc@redhat.com>
1693 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1696 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1698 Fix extraction of signed constants in nios2 disassembler (again).
1700 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1701 extractions of signed fields.
1703 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1705 * s390-opc.txt: Relocate vector load/store instructions with
1706 additional alignment parameter and change architecture level
1707 constraint from z14 to z13.
1709 2020-05-21 Alan Modra <amodra@gmail.com>
1711 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1712 * sparc-dis.c: Likewise.
1713 * tic4x-dis.c: Likewise.
1714 * xtensa-dis.c: Likewise.
1715 * bpf-desc.c: Regenerate.
1716 * epiphany-desc.c: Regenerate.
1717 * fr30-desc.c: Regenerate.
1718 * frv-desc.c: Regenerate.
1719 * ip2k-desc.c: Regenerate.
1720 * iq2000-desc.c: Regenerate.
1721 * lm32-desc.c: Regenerate.
1722 * m32c-desc.c: Regenerate.
1723 * m32r-desc.c: Regenerate.
1724 * mep-asm.c: Regenerate.
1725 * mep-desc.c: Regenerate.
1726 * mt-desc.c: Regenerate.
1727 * or1k-desc.c: Regenerate.
1728 * xc16x-desc.c: Regenerate.
1729 * xstormy16-desc.c: Regenerate.
1731 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
1733 * riscv-opc.c (riscv_ext_version_table): The table used to store
1734 all information about the supported spec and the corresponding ISA
1735 versions. Currently, only Zicsr is supported to verify the
1736 correctness of Z sub extension settings. Others will be supported
1737 in the future patches.
1738 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1739 classes and the corresponding strings.
1740 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1741 spec class by giving a ISA spec string.
1742 * riscv-opc.c (struct priv_spec_t): New structure.
1743 (struct priv_spec_t priv_specs): List for all supported privilege spec
1744 classes and the corresponding strings.
1745 (riscv_get_priv_spec_class): New function. Get the corresponding
1746 privilege spec class by giving a spec string.
1747 (riscv_get_priv_spec_name): New function. Get the corresponding
1748 privilege spec string by giving a CSR version class.
1749 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1750 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1751 according to the chosen version. Build a hash table riscv_csr_hash to
1752 store the valid CSR for the chosen pirv verison. Dump the direct
1753 CSR address rather than it's name if it is invalid.
1754 (parse_riscv_dis_option_without_args): New function. Parse the options
1756 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1757 parse the options without arguments first, and then handle the options
1758 with arguments. Add the new option -Mpriv-spec, which has argument.
1759 * riscv-dis.c (print_riscv_disassembler_options): Add description
1760 about the new OBJDUMP option.
1762 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
1764 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1765 WC values on POWER10 sync, dcbf and wait instructions.
1766 (insert_pl, extract_pl): New functions.
1767 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1768 (LS3): New , 3-bit L for sync.
1769 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1770 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1771 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1772 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1773 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1774 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1775 <wait>: Enable PL operand on POWER10.
1776 <dcbf>: Enable L3OPT operand on POWER10.
1777 <sync>: Enable SC2 operand on POWER10.
1779 2020-05-19 Stafford Horne <shorne@gmail.com>
1782 * or1k-asm.c: Regenerate.
1783 * or1k-desc.c: Regenerate.
1784 * or1k-desc.h: Regenerate.
1785 * or1k-dis.c: Regenerate.
1786 * or1k-ibld.c: Regenerate.
1787 * or1k-opc.c: Regenerate.
1788 * or1k-opc.h: Regenerate.
1789 * or1k-opinst.c: Regenerate.
1791 2020-05-11 Alan Modra <amodra@gmail.com>
1793 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1796 2020-05-11 Alan Modra <amodra@gmail.com>
1798 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1799 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1801 2020-05-11 Alan Modra <amodra@gmail.com>
1803 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1805 2020-05-11 Alan Modra <amodra@gmail.com>
1807 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1808 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1810 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1812 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1815 2020-05-11 Alan Modra <amodra@gmail.com>
1817 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1818 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1819 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1820 (prefix_opcodes): Add xxeval.
1822 2020-05-11 Alan Modra <amodra@gmail.com>
1824 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1825 xxgenpcvwm, xxgenpcvdm.
1827 2020-05-11 Alan Modra <amodra@gmail.com>
1829 * ppc-opc.c (MP, VXVAM_MASK): Define.
1830 (VXVAPS_MASK): Use VXVA_MASK.
1831 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1832 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1833 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1834 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1836 2020-05-11 Alan Modra <amodra@gmail.com>
1837 Peter Bergner <bergner@linux.ibm.com>
1839 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1841 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1842 YMSK2, XA6a, XA6ap, XB6a entries.
1843 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1844 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1846 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1847 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1848 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1849 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1850 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1851 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1852 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1853 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1854 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1855 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1856 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1857 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1858 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1859 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1861 2020-05-11 Alan Modra <amodra@gmail.com>
1863 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1864 (insert_xts, extract_xts): New functions.
1865 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1866 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1867 (VXRC_MASK, VXSH_MASK): Define.
1868 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1869 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1870 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1871 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1872 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1873 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1874 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1876 2020-05-11 Alan Modra <amodra@gmail.com>
1878 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1879 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1880 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1881 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1882 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1884 2020-05-11 Alan Modra <amodra@gmail.com>
1886 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1887 (XTP, DQXP, DQXP_MASK): Define.
1888 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1889 (prefix_opcodes): Add plxvp and pstxvp.
1891 2020-05-11 Alan Modra <amodra@gmail.com>
1893 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1894 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1895 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1897 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1899 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1901 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1903 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1905 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1907 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
1909 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1911 2020-05-11 Alan Modra <amodra@gmail.com>
1913 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1915 2020-05-11 Alan Modra <amodra@gmail.com>
1917 * ppc-dis.c (ppc_opts): Add "power10" entry.
1918 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1919 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1921 2020-05-11 Nick Clifton <nickc@redhat.com>
1923 * po/fr.po: Updated French translation.
1925 2020-04-30 Alex Coplan <alex.coplan@arm.com>
1927 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1928 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1929 (operand_general_constraint_met_p): validate
1930 AARCH64_OPND_UNDEFINED.
1931 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1933 * aarch64-asm-2.c: Regenerated.
1934 * aarch64-dis-2.c: Regenerated.
1935 * aarch64-opc-2.c: Regenerated.
1937 2020-04-29 Nick Clifton <nickc@redhat.com>
1940 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1943 2020-04-29 Nick Clifton <nickc@redhat.com>
1945 * po/sv.po: Updated Swedish translation.
1947 2020-04-29 Nick Clifton <nickc@redhat.com>
1950 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1951 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1952 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1955 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1958 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1959 cmpi only on m68020up and cpu32.
1961 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1963 * aarch64-asm.c (aarch64_ins_none): New.
1964 * aarch64-asm.h (ins_none): New declaration.
1965 * aarch64-dis.c (aarch64_ext_none): New.
1966 * aarch64-dis.h (ext_none): New declaration.
1967 * aarch64-opc.c (aarch64_print_operand): Update case for
1968 AARCH64_OPND_BARRIER_PSB.
1969 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1970 (AARCH64_OPERANDS): Update inserter/extracter for
1971 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1972 * aarch64-asm-2.c: Regenerated.
1973 * aarch64-dis-2.c: Regenerated.
1974 * aarch64-opc-2.c: Regenerated.
1976 2020-04-20 Sudakshina Das <sudi.das@arm.com>
1978 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1979 (aarch64_feature_ras, RAS): Likewise.
1980 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1981 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1982 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1983 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1984 * aarch64-asm-2.c: Regenerated.
1985 * aarch64-dis-2.c: Regenerated.
1986 * aarch64-opc-2.c: Regenerated.
1988 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
1990 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1991 (print_insn_neon): Support disassembly of conditional
1994 2020-02-16 David Faust <david.faust@oracle.com>
1996 * bpf-desc.c: Regenerate.
1997 * bpf-desc.h: Likewise.
1998 * bpf-opc.c: Regenerate.
1999 * bpf-opc.h: Likewise.
2001 2020-04-07 Lili Cui <lili.cui@intel.com>
2003 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2004 (prefix_table): New instructions (see prefixes above).
2005 (rm_table): Likewise
2006 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2007 CPU_ANY_TSXLDTRK_FLAGS.
2008 (cpu_flags): Add CpuTSXLDTRK.
2009 * i386-opc.h (enum): Add CpuTSXLDTRK.
2010 (i386_cpu_flags): Add cputsxldtrk.
2011 * i386-opc.tbl: Add XSUSPLDTRK insns.
2012 * i386-init.h: Regenerate.
2013 * i386-tbl.h: Likewise.
2015 2020-04-02 Lili Cui <lili.cui@intel.com>
2017 * i386-dis.c (prefix_table): New instructions serialize.
2018 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2019 CPU_ANY_SERIALIZE_FLAGS.
2020 (cpu_flags): Add CpuSERIALIZE.
2021 * i386-opc.h (enum): Add CpuSERIALIZE.
2022 (i386_cpu_flags): Add cpuserialize.
2023 * i386-opc.tbl: Add SERIALIZE insns.
2024 * i386-init.h: Regenerate.
2025 * i386-tbl.h: Likewise.
2027 2020-03-26 Alan Modra <amodra@gmail.com>
2029 * disassemble.h (opcodes_assert): Declare.
2030 (OPCODES_ASSERT): Define.
2031 * disassemble.c: Don't include assert.h. Include opintl.h.
2032 (opcodes_assert): New function.
2033 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2034 (bfd_h8_disassemble): Reduce size of data array. Correctly
2035 calculate maxlen. Omit insn decoding when insn length exceeds
2036 maxlen. Exit from nibble loop when looking for E, before
2037 accessing next data byte. Move processing of E outside loop.
2038 Replace tests of maxlen in loop with assertions.
2040 2020-03-26 Alan Modra <amodra@gmail.com>
2042 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2044 2020-03-25 Alan Modra <amodra@gmail.com>
2046 * z80-dis.c (suffix): Init mybuf.
2048 2020-03-22 Alan Modra <amodra@gmail.com>
2050 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2051 successflly read from section.
2053 2020-03-22 Alan Modra <amodra@gmail.com>
2055 * arc-dis.c (find_format): Use ISO C string concatenation rather
2056 than line continuation within a string. Don't access needs_limm
2057 before testing opcode != NULL.
2059 2020-03-22 Alan Modra <amodra@gmail.com>
2061 * ns32k-dis.c (print_insn_arg): Update comment.
2062 (print_insn_ns32k): Reduce size of index_offset array, and
2063 initialize, passing -1 to print_insn_arg for args that are not
2064 an index. Don't exit arg loop early. Abort on bad arg number.
2066 2020-03-22 Alan Modra <amodra@gmail.com>
2068 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2069 * s12z-opc.c: Formatting.
2070 (operands_f): Return an int.
2071 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2072 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2073 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2074 (exg_sex_discrim): Likewise.
2075 (create_immediate_operand, create_bitfield_operand),
2076 (create_register_operand_with_size, create_register_all_operand),
2077 (create_register_all16_operand, create_simple_memory_operand),
2078 (create_memory_operand, create_memory_auto_operand): Don't
2079 segfault on malloc failure.
2080 (z_ext24_decode): Return an int status, negative on fail, zero
2082 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2083 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2084 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2085 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2086 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2087 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2088 (loop_primitive_decode, shift_decode, psh_pul_decode),
2089 (bit_field_decode): Similarly.
2090 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2091 to return value, update callers.
2092 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2093 Don't segfault on NULL operand.
2094 (decode_operation): Return OP_INVALID on first fail.
2095 (decode_s12z): Check all reads, returning -1 on fail.
2097 2020-03-20 Alan Modra <amodra@gmail.com>
2099 * metag-dis.c (print_insn_metag): Don't ignore status from
2102 2020-03-20 Alan Modra <amodra@gmail.com>
2104 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2105 Initialize parts of buffer not written when handling a possible
2106 2-byte insn at end of section. Don't attempt decoding of such
2107 an insn by the 4-byte machinery.
2109 2020-03-20 Alan Modra <amodra@gmail.com>
2111 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2112 partially filled buffer. Prevent lookup of 4-byte insns when
2113 only VLE 2-byte insns are possible due to section size. Print
2114 ".word" rather than ".long" for 2-byte leftovers.
2116 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2119 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2121 2020-03-13 Jan Beulich <jbeulich@suse.com>
2123 * i386-dis.c (X86_64_0D): Rename to ...
2124 (X86_64_0E): ... this.
2126 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2128 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2129 * Makefile.in: Regenerated.
2131 2020-03-09 Jan Beulich <jbeulich@suse.com>
2133 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2135 * i386-tbl.h: Re-generate.
2137 2020-03-09 Jan Beulich <jbeulich@suse.com>
2139 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2140 vprot*, vpsha*, and vpshl*.
2141 * i386-tbl.h: Re-generate.
2143 2020-03-09 Jan Beulich <jbeulich@suse.com>
2145 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2146 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2147 * i386-tbl.h: Re-generate.
2149 2020-03-09 Jan Beulich <jbeulich@suse.com>
2151 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2152 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2153 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2154 * i386-tbl.h: Re-generate.
2156 2020-03-09 Jan Beulich <jbeulich@suse.com>
2158 * i386-gen.c (struct template_arg, struct template_instance,
2159 struct template_param, struct template, templates,
2160 parse_template, expand_templates): New.
2161 (process_i386_opcodes): Various local variables moved to
2162 expand_templates. Call parse_template and expand_templates.
2163 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2164 * i386-tbl.h: Re-generate.
2166 2020-03-06 Jan Beulich <jbeulich@suse.com>
2168 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2169 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2170 register and memory source templates. Replace VexW= by VexW*
2172 * i386-tbl.h: Re-generate.
2174 2020-03-06 Jan Beulich <jbeulich@suse.com>
2176 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2177 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2178 * i386-tbl.h: Re-generate.
2180 2020-03-06 Jan Beulich <jbeulich@suse.com>
2182 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2183 * i386-tbl.h: Re-generate.
2185 2020-03-06 Jan Beulich <jbeulich@suse.com>
2187 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2188 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2189 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2190 VexW0 on SSE2AVX variants.
2191 (vmovq): Drop NoRex64 from XMM/XMM variants.
2192 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2193 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2194 applicable use VexW0.
2195 * i386-tbl.h: Re-generate.
2197 2020-03-06 Jan Beulich <jbeulich@suse.com>
2199 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2200 * i386-opc.h (Rex64): Delete.
2201 (struct i386_opcode_modifier): Remove rex64 field.
2202 * i386-opc.tbl (crc32): Drop Rex64.
2203 Replace Rex64 with Size64 everywhere else.
2204 * i386-tbl.h: Re-generate.
2206 2020-03-06 Jan Beulich <jbeulich@suse.com>
2208 * i386-dis.c (OP_E_memory): Exclude recording of used address
2209 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2210 addressed memory operands for MPX insns.
2212 2020-03-06 Jan Beulich <jbeulich@suse.com>
2214 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2215 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2216 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2217 (ptwrite): Split into non-64-bit and 64-bit forms.
2218 * i386-tbl.h: Re-generate.
2220 2020-03-06 Jan Beulich <jbeulich@suse.com>
2222 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2224 * i386-tbl.h: Re-generate.
2226 2020-03-04 Jan Beulich <jbeulich@suse.com>
2228 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2229 (prefix_table): Move vmmcall here. Add vmgexit.
2230 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2231 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2232 (cpu_flags): Add CpuSEV_ES entry.
2233 * i386-opc.h (CpuSEV_ES): New.
2234 (union i386_cpu_flags): Add cpusev_es field.
2235 * i386-opc.tbl (vmgexit): New.
2236 * i386-init.h, i386-tbl.h: Re-generate.
2238 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2240 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2242 * i386-opc.h (IGNORESIZE): New.
2243 (DEFAULTSIZE): Likewise.
2244 (IgnoreSize): Removed.
2245 (DefaultSize): Likewise.
2246 (MnemonicSize): New.
2247 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2249 * i386-opc.tbl (IgnoreSize): New.
2250 (DefaultSize): Likewise.
2251 * i386-tbl.h: Regenerated.
2253 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2256 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2259 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2262 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2263 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2264 * i386-tbl.h: Regenerated.
2266 2020-02-26 Alan Modra <amodra@gmail.com>
2268 * aarch64-asm.c: Indent labels correctly.
2269 * aarch64-dis.c: Likewise.
2270 * aarch64-gen.c: Likewise.
2271 * aarch64-opc.c: Likewise.
2272 * alpha-dis.c: Likewise.
2273 * i386-dis.c: Likewise.
2274 * nds32-asm.c: Likewise.
2275 * nfp-dis.c: Likewise.
2276 * visium-dis.c: Likewise.
2278 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2280 * arc-regs.h (int_vector_base): Make it available for all ARC
2283 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
2285 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2288 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
2290 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2291 c.mv/c.li if rs1 is zero.
2293 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2295 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2296 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2298 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2299 * i386-opc.h (CpuABM): Removed.
2301 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2302 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2303 popcnt. Remove CpuABM from lzcnt.
2304 * i386-init.h: Regenerated.
2305 * i386-tbl.h: Likewise.
2307 2020-02-17 Jan Beulich <jbeulich@suse.com>
2309 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2310 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2311 VexW1 instead of open-coding them.
2312 * i386-tbl.h: Re-generate.
2314 2020-02-17 Jan Beulich <jbeulich@suse.com>
2316 * i386-opc.tbl (AddrPrefixOpReg): Define.
2317 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2318 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2319 templates. Drop NoRex64.
2320 * i386-tbl.h: Re-generate.
2322 2020-02-17 Jan Beulich <jbeulich@suse.com>
2325 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2326 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2327 into Intel syntax instance (with Unpsecified) and AT&T one
2329 (vcvtneps2bf16): Likewise, along with folding the two so far
2331 * i386-tbl.h: Re-generate.
2333 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2335 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2336 CPU_ANY_SSE4A_FLAGS.
2338 2020-02-17 Alan Modra <amodra@gmail.com>
2340 * i386-gen.c (cpu_flag_init): Correct last change.
2342 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2344 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2347 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2349 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2352 2020-02-14 Jan Beulich <jbeulich@suse.com>
2355 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2356 destination for Cpu64-only variant.
2357 (movzx): Fold patterns.
2358 * i386-tbl.h: Re-generate.
2360 2020-02-13 Jan Beulich <jbeulich@suse.com>
2362 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2363 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2364 CPU_ANY_SSE4_FLAGS entry.
2365 * i386-init.h: Re-generate.
2367 2020-02-12 Jan Beulich <jbeulich@suse.com>
2369 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2370 with Unspecified, making the present one AT&T syntax only.
2371 * i386-tbl.h: Re-generate.
2373 2020-02-12 Jan Beulich <jbeulich@suse.com>
2375 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2376 * i386-tbl.h: Re-generate.
2378 2020-02-12 Jan Beulich <jbeulich@suse.com>
2381 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2382 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2383 Amd64 and Intel64 templates.
2384 (call, jmp): Likewise for far indirect variants. Dro
2386 * i386-tbl.h: Re-generate.
2388 2020-02-11 Jan Beulich <jbeulich@suse.com>
2390 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2391 * i386-opc.h (ShortForm): Delete.
2392 (struct i386_opcode_modifier): Remove shortform field.
2393 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2394 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2395 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2396 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2398 * i386-tbl.h: Re-generate.
2400 2020-02-11 Jan Beulich <jbeulich@suse.com>
2402 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2403 fucompi): Drop ShortForm from operand-less templates.
2404 * i386-tbl.h: Re-generate.
2406 2020-02-11 Alan Modra <amodra@gmail.com>
2408 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2409 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2410 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2411 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2412 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2414 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2416 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2417 (cde_opcodes): Add VCX* instructions.
2419 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2420 Matthew Malcomson <matthew.malcomson@arm.com>
2422 * arm-dis.c (struct cdeopcode32): New.
2423 (CDE_OPCODE): New macro.
2424 (cde_opcodes): New disassembly table.
2425 (regnames): New option to table.
2426 (cde_coprocs): New global variable.
2427 (print_insn_cde): New
2428 (print_insn_thumb32): Use print_insn_cde.
2429 (parse_arm_disassembler_options): Parse coprocN args.
2431 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2434 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2436 * i386-opc.h (AMD64): Removed.
2437 (Intel64): Likewose.
2439 (INTEL64): Likewise.
2440 (INTEL64ONLY): Likewise.
2441 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2442 * i386-opc.tbl (Amd64): New.
2443 (Intel64): Likewise.
2444 (Intel64Only): Likewise.
2445 Replace AMD64 with Amd64. Update sysenter/sysenter with
2446 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2447 * i386-tbl.h: Regenerated.
2449 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2452 * z80-dis.c: Add support for GBZ80 opcodes.
2454 2020-02-04 Alan Modra <amodra@gmail.com>
2456 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2458 2020-02-03 Alan Modra <amodra@gmail.com>
2460 * m32c-ibld.c: Regenerate.
2462 2020-02-01 Alan Modra <amodra@gmail.com>
2464 * frv-ibld.c: Regenerate.
2466 2020-01-31 Jan Beulich <jbeulich@suse.com>
2468 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2469 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2470 (OP_E_memory): Replace xmm_mdq_mode case label by
2471 vex_scalar_w_dq_mode one.
2472 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2474 2020-01-31 Jan Beulich <jbeulich@suse.com>
2476 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2477 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2478 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2479 (intel_operand_size): Drop vex_w_dq_mode case label.
2481 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2483 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2484 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2486 2020-01-30 Alan Modra <amodra@gmail.com>
2488 * m32c-ibld.c: Regenerate.
2490 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2492 * bpf-opc.c: Regenerate.
2494 2020-01-30 Jan Beulich <jbeulich@suse.com>
2496 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2497 (dis386): Use them to replace C2/C3 table entries.
2498 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2499 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2500 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2501 * i386-tbl.h: Re-generate.
2503 2020-01-30 Jan Beulich <jbeulich@suse.com>
2505 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2507 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2509 * i386-tbl.h: Re-generate.
2511 2020-01-30 Alan Modra <amodra@gmail.com>
2513 * tic4x-dis.c (tic4x_dp): Make unsigned.
2515 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2516 Jan Beulich <jbeulich@suse.com>
2519 * i386-dis.c (MOVSXD_Fixup): New function.
2520 (movsxd_mode): New enum.
2521 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2522 (intel_operand_size): Handle movsxd_mode.
2523 (OP_E_register): Likewise.
2525 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2526 register on movsxd. Add movsxd with 16-bit destination register
2527 for AMD64 and Intel64 ISAs.
2528 * i386-tbl.h: Regenerated.
2530 2020-01-27 Tamar Christina <tamar.christina@arm.com>
2533 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2534 * aarch64-asm-2.c: Regenerate
2535 * aarch64-dis-2.c: Likewise.
2536 * aarch64-opc-2.c: Likewise.
2538 2020-01-21 Jan Beulich <jbeulich@suse.com>
2540 * i386-opc.tbl (sysret): Drop DefaultSize.
2541 * i386-tbl.h: Re-generate.
2543 2020-01-21 Jan Beulich <jbeulich@suse.com>
2545 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2547 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2548 * i386-tbl.h: Re-generate.
2550 2020-01-20 Nick Clifton <nickc@redhat.com>
2552 * po/de.po: Updated German translation.
2553 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2554 * po/uk.po: Updated Ukranian translation.
2556 2020-01-20 Alan Modra <amodra@gmail.com>
2558 * hppa-dis.c (fput_const): Remove useless cast.
2560 2020-01-20 Alan Modra <amodra@gmail.com>
2562 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2564 2020-01-18 Nick Clifton <nickc@redhat.com>
2566 * configure: Regenerate.
2567 * po/opcodes.pot: Regenerate.
2569 2020-01-18 Nick Clifton <nickc@redhat.com>
2571 Binutils 2.34 branch created.
2573 2020-01-17 Christian Biesinger <cbiesinger@google.com>
2575 * opintl.h: Fix spelling error (seperate).
2577 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2579 * i386-opc.tbl: Add {vex} pseudo prefix.
2580 * i386-tbl.h: Regenerated.
2582 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2585 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2586 (neon_opcodes): Likewise.
2587 (select_arm_features): Make sure we enable MVE bits when selecting
2588 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2591 2020-01-16 Jan Beulich <jbeulich@suse.com>
2593 * i386-opc.tbl: Drop stale comment from XOP section.
2595 2020-01-16 Jan Beulich <jbeulich@suse.com>
2597 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2598 (extractps): Add VexWIG to SSE2AVX forms.
2599 * i386-tbl.h: Re-generate.
2601 2020-01-16 Jan Beulich <jbeulich@suse.com>
2603 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2604 Size64 from and use VexW1 on SSE2AVX forms.
2605 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2606 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2607 * i386-tbl.h: Re-generate.
2609 2020-01-15 Alan Modra <amodra@gmail.com>
2611 * tic4x-dis.c (tic4x_version): Make unsigned long.
2612 (optab, optab_special, registernames): New file scope vars.
2613 (tic4x_print_register): Set up registernames rather than
2614 malloc'd registertable.
2615 (tic4x_disassemble): Delete optable and optable_special. Use
2616 optab and optab_special instead. Throw away old optab,
2617 optab_special and registernames when info->mach changes.
2619 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2622 * z80-dis.c (suffix): Use .db instruction to generate double
2625 2020-01-14 Alan Modra <amodra@gmail.com>
2627 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2628 values to unsigned before shifting.
2630 2020-01-13 Thomas Troeger <tstroege@gmx.de>
2632 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2634 (print_insn_thumb16, print_insn_thumb32): Likewise.
2635 (print_insn): Initialize the insn info.
2636 * i386-dis.c (print_insn): Initialize the insn info fields, and
2639 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2641 * arc-opc.c (C_NE): Make it required.
2643 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2645 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2646 reserved register name.
2648 2020-01-13 Alan Modra <amodra@gmail.com>
2650 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2651 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2653 2020-01-13 Alan Modra <amodra@gmail.com>
2655 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2656 result of wasm_read_leb128 in a uint64_t and check that bits
2657 are not lost when copying to other locals. Use uint32_t for
2658 most locals. Use PRId64 when printing int64_t.
2660 2020-01-13 Alan Modra <amodra@gmail.com>
2662 * score-dis.c: Formatting.
2663 * score7-dis.c: Formatting.
2665 2020-01-13 Alan Modra <amodra@gmail.com>
2667 * score-dis.c (print_insn_score48): Use unsigned variables for
2668 unsigned values. Don't left shift negative values.
2669 (print_insn_score32): Likewise.
2670 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2672 2020-01-13 Alan Modra <amodra@gmail.com>
2674 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2676 2020-01-13 Alan Modra <amodra@gmail.com>
2678 * fr30-ibld.c: Regenerate.
2680 2020-01-13 Alan Modra <amodra@gmail.com>
2682 * xgate-dis.c (print_insn): Don't left shift signed value.
2683 (ripBits): Formatting, use 1u.
2685 2020-01-10 Alan Modra <amodra@gmail.com>
2687 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2688 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2690 2020-01-10 Alan Modra <amodra@gmail.com>
2692 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2693 and XRREG value earlier to avoid a shift with negative exponent.
2694 * m10200-dis.c (disassemble): Similarly.
2696 2020-01-09 Nick Clifton <nickc@redhat.com>
2699 * z80-dis.c (ld_ii_ii): Use correct cast.
2701 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2704 * z80-dis.c (ld_ii_ii): Use character constant when checking
2707 2020-01-09 Jan Beulich <jbeulich@suse.com>
2709 * i386-dis.c (SEP_Fixup): New.
2711 (dis386_twobyte): Use it for sysenter/sysexit.
2712 (enum x86_64_isa): Change amd64 enumerator to value 1.
2713 (OP_J): Compare isa64 against intel64 instead of amd64.
2714 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2716 * i386-tbl.h: Re-generate.
2718 2020-01-08 Alan Modra <amodra@gmail.com>
2720 * z8k-dis.c: Include libiberty.h
2721 (instr_data_s): Make max_fetched unsigned.
2722 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2723 Don't exceed byte_info bounds.
2724 (output_instr): Make num_bytes unsigned.
2725 (unpack_instr): Likewise for nibl_count and loop.
2726 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2728 * z8k-opc.h: Regenerate.
2730 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
2732 * arc-tbl.h (llock): Use 'LLOCK' as class.
2734 (scond): Use 'SCOND' as class.
2736 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2739 2020-01-06 Alan Modra <amodra@gmail.com>
2741 * m32c-ibld.c: Regenerate.
2743 2020-01-06 Alan Modra <amodra@gmail.com>
2746 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2747 Peek at next byte to prevent recursion on repeated prefix bytes.
2748 Ensure uninitialised "mybuf" is not accessed.
2749 (print_insn_z80): Don't zero n_fetch and n_used here,..
2750 (print_insn_z80_buf): ..do it here instead.
2752 2020-01-04 Alan Modra <amodra@gmail.com>
2754 * m32r-ibld.c: Regenerate.
2756 2020-01-04 Alan Modra <amodra@gmail.com>
2758 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2760 2020-01-04 Alan Modra <amodra@gmail.com>
2762 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2764 2020-01-04 Alan Modra <amodra@gmail.com>
2766 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2768 2020-01-03 Jan Beulich <jbeulich@suse.com>
2770 * aarch64-tbl.h (aarch64_opcode_table): Use
2771 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2773 2020-01-03 Jan Beulich <jbeulich@suse.com>
2775 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
2776 forms of SUDOT and USDOT.
2778 2020-01-03 Jan Beulich <jbeulich@suse.com>
2780 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
2782 * opcodes/aarch64-dis-2.c: Re-generate.
2784 2020-01-03 Jan Beulich <jbeulich@suse.com>
2786 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
2788 * opcodes/aarch64-dis-2.c: Re-generate.
2790 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2792 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2794 2020-01-01 Alan Modra <amodra@gmail.com>
2796 Update year range in copyright notice of all files.
2798 For older changes see ChangeLog-2019
2800 Copyright (C) 2020 Free Software Foundation, Inc.
2802 Copying and distribution of this file, with or without modification,
2803 are permitted in any medium without royalty provided the copyright
2804 notice and this notice are preserved.
2810 version-control: never
projects / thirdparty / binutils-gdb.git / blob