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x86/Intel: accept memory operand size specifiers for CET insns
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
1 2018-07-11 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (wrssd, wrussd): Add Dword.
4 (wrssq, wrussq): Add Qword.
5 * i386-tbl.h: Re-generate.
6
7 2018-07-11 Jan Beulich <jbeulich@suse.com>
8
9 * i386-opc.h: Rename OTMax to OTNum.
10 (OTNumOfUints): Adjust calculation.
11 (OTUnused): Directly alias to OTNum.
12
13 2018-07-09 Maciej W. Rozycki <macro@mips.com>
14
15 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
16 `reg_xys'.
17 (lea_reg_xys): Likewise.
18 (print_insn_loop_primitive): Rename `reg' local variable to
19 `reg_dxy'.
20
21 2018-07-06 Tamar Christina <tamar.christina@arm.com>
22
23 PR binutils/23242
24 * aarch64-tbl.h (ldarh): Fix disassembly mask.
25
26 2018-07-06 Tamar Christina <tamar.christina@arm.com>
27
28 PR binutils/23369
29 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
30 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
31
32 2018-07-02 Maciej W. Rozycki <macro@mips.com>
33
34 PR tdep/8282
35 * mips-dis.c (mips_option_arg_t): New enumeration.
36 (mips_options): New variable.
37 (disassembler_options_mips): New function.
38 (print_mips_disassembler_options): Reimplement in terms of
39 `disassembler_options_mips'.
40 * arm-dis.c (disassembler_options_arm): Adapt to using the
41 `disasm_options_and_args_t' structure.
42 * ppc-dis.c (disassembler_options_powerpc): Likewise.
43 * s390-dis.c (disassembler_options_s390): Likewise.
44
45 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
46
47 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
48 expected result.
49 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
50 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
51 * testsuite/ld-arm/tls-longplt.d: Likewise.
52
53 2018-06-29 Tamar Christina <tamar.christina@arm.com>
54
55 PR binutils/23192
56 * aarch64-asm-2.c: Regenerate.
57 * aarch64-dis-2.c: Likewise.
58 * aarch64-opc-2.c: Likewise.
59 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
60 * aarch64-opc.c (operand_general_constraint_met_p,
61 aarch64_print_operand): Likewise.
62 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
63 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
64 fmlal2, fmlsl2.
65 (AARCH64_OPERANDS): Add Em2.
66
67 2018-06-26 Nick Clifton <nickc@redhat.com>
68
69 * po/uk.po: Updated Ukranian translation.
70 * po/de.po: Updated German translation.
71 * po/pt_BR.po: Updated Brazilian Portuguese translation.
72
73 2018-06-26 Nick Clifton <nickc@redhat.com>
74
75 * nfp-dis.c: Fix spelling mistake.
76
77 2018-06-24 Nick Clifton <nickc@redhat.com>
78
79 * configure: Regenerate.
80 * po/opcodes.pot: Regenerate.
81
82 2018-06-24 Nick Clifton <nickc@redhat.com>
83
84 2.31 branch created.
85
86 2018-06-19 Tamar Christina <tamar.christina@arm.com>
87
88 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
89 * aarch64-asm-2.c: Regenerate.
90 * aarch64-dis-2.c: Likewise.
91
92 2018-06-21 Maciej W. Rozycki <macro@mips.com>
93
94 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
95 `-M ginv' option description.
96
97 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
98
99 PR gas/23305
100 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
101 la and lla.
102
103 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
104
105 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
106 * configure.ac: Remove AC_PREREQ.
107 * Makefile.in: Re-generate.
108 * aclocal.m4: Re-generate.
109 * configure: Re-generate.
110
111 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
112
113 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
114 mips64r6 descriptors.
115 (parse_mips_ase_option): Handle -Mginv option.
116 (print_mips_disassembler_options): Document -Mginv.
117 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
118 (GINV): New macro.
119 (mips_opcodes): Define ginvi and ginvt.
120
121 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
122 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
123
124 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
125 * mips-opc.c (CRC, CRC64): New macros.
126 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
127 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
128 crc32cd for CRC64.
129
130 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
131
132 PR 20319
133 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
134 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
135
136 2018-06-06 Alan Modra <amodra@gmail.com>
137
138 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
139 setjmp. Move init for some other vars later too.
140
141 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
142
143 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
144 (dis_private): Add new fields for property section tracking.
145 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
146 (xtensa_instruction_fits): New functions.
147 (fetch_data): Bump minimal fetch size to 4.
148 (print_insn_xtensa): Make struct dis_private static.
149 Load and prepare property table on section change.
150 Don't disassemble literals. Don't disassemble instructions that
151 cross property table boundaries.
152
153 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
154
155 * configure: Regenerated.
156
157 2018-06-01 Jan Beulich <jbeulich@suse.com>
158
159 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
160 * i386-tbl.h: Re-generate.
161
162 2018-06-01 Jan Beulich <jbeulich@suse.com>
163
164 * i386-opc.tbl (sldt, str): Add NoRex64.
165 * i386-tbl.h: Re-generate.
166
167 2018-06-01 Jan Beulich <jbeulich@suse.com>
168
169 * i386-opc.tbl (invpcid): Add Oword.
170 * i386-tbl.h: Re-generate.
171
172 2018-06-01 Alan Modra <amodra@gmail.com>
173
174 * sysdep.h (_bfd_error_handler): Don't declare.
175 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
176 * rl78-decode.opc: Likewise.
177 * msp430-decode.c: Regenerate.
178 * rl78-decode.c: Regenerate.
179
180 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
181
182 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
183 * i386-init.h : Regenerated.
184
185 2018-05-25 Alan Modra <amodra@gmail.com>
186
187 * Makefile.in: Regenerate.
188 * po/POTFILES.in: Regenerate.
189
190 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
191
192 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
193 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
194 (insert_bab, extract_bab, insert_btab, extract_btab,
195 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
196 (BAT, BBA VBA RBS XB6S): Delete macros.
197 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
198 (BB, BD, RBX, XC6): Update for new macros.
199 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
200 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
201 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
202 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
203
204 2018-05-18 John Darrington <john@darrington.wattle.id.au>
205
206 * Makefile.am: Add support for s12z architecture.
207 * configure.ac: Likewise.
208 * disassemble.c: Likewise.
209 * disassemble.h: Likewise.
210 * Makefile.in: Regenerate.
211 * configure: Regenerate.
212 * s12z-dis.c: New file.
213 * s12z.h: New file.
214
215 2018-05-18 Alan Modra <amodra@gmail.com>
216
217 * nfp-dis.c: Don't #include libbfd.h.
218 (init_nfp3200_priv): Use bfd_get_section_contents.
219 (nit_nfp6000_mecsr_sec): Likewise.
220
221 2018-05-17 Nick Clifton <nickc@redhat.com>
222
223 * po/zh_CN.po: Updated simplified Chinese translation.
224
225 2018-05-16 Tamar Christina <tamar.christina@arm.com>
226
227 PR binutils/23109
228 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
229 * aarch64-dis-2.c: Regenerate.
230
231 2018-05-15 Tamar Christina <tamar.christina@arm.com>
232
233 PR binutils/21446
234 * aarch64-asm.c (opintl.h): Include.
235 (aarch64_ins_sysreg): Enforce read/write constraints.
236 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
237 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
238 (F_REG_READ, F_REG_WRITE): New.
239 * aarch64-opc.c (aarch64_print_operand): Generate notes for
240 AARCH64_OPND_SYSREG.
241 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
242 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
243 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
244 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
245 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
246 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
247 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
248 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
249 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
250 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
251 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
252 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
253 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
254 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
255 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
256 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
257 msr (F_SYS_WRITE), mrs (F_SYS_READ).
258
259 2018-05-15 Tamar Christina <tamar.christina@arm.com>
260
261 PR binutils/21446
262 * aarch64-dis.c (no_notes: New.
263 (parse_aarch64_dis_option): Support notes.
264 (aarch64_decode_insn, print_operands): Likewise.
265 (print_aarch64_disassembler_options): Document notes.
266 * aarch64-opc.c (aarch64_print_operand): Support notes.
267
268 2018-05-15 Tamar Christina <tamar.christina@arm.com>
269
270 PR binutils/21446
271 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
272 and take error struct.
273 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
274 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
275 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
276 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
277 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
278 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
279 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
280 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
281 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
282 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
283 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
284 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
285 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
286 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
287 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
288 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
289 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
290 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
291 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
292 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
293 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
294 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
295 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
296 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
297 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
298 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
299 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
300 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
301 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
302 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
303 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
304 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
305 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
306 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
307 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
308 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
309 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
310 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
311 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
312 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
313 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
314 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
315 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
316 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
317 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
318 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
319 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
320 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
321 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
322 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
323 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
324 (determine_disassembling_preference, aarch64_decode_insn,
325 print_insn_aarch64_word, print_insn_data): Take errors struct.
326 (print_insn_aarch64): Use errors.
327 * aarch64-asm-2.c: Regenerate.
328 * aarch64-dis-2.c: Regenerate.
329 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
330 boolean in aarch64_insert_operan.
331 (print_operand_extractor): Likewise.
332 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
333
334 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
335
336 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
337
338 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
339
340 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
341
342 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
343
344 * cr16-opc.c (cr16_instruction): Comment typo fix.
345 * hppa-dis.c (print_insn_hppa): Likewise.
346
347 2018-05-08 Jim Wilson <jimw@sifive.com>
348
349 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
350 (match_c_slli64, match_srxi_as_c_srxi): New.
351 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
352 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
353 <c.slli, c.srli, c.srai>: Use match_s_slli.
354 <c.slli64, c.srli64, c.srai64>: New.
355
356 2018-05-08 Alan Modra <amodra@gmail.com>
357
358 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
359 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
360 partition opcode space for index lookup.
361
362 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
363
364 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
365 <insn_length>: ...with this. Update usage.
366 Remove duplicate call to *info->memory_error_func.
367
368 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
369 H.J. Lu <hongjiu.lu@intel.com>
370
371 * i386-dis.c (Gva): New.
372 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
373 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
374 (prefix_table): New instructions (see prefix above).
375 (mod_table): New instructions (see prefix above).
376 (OP_G): Handle va_mode.
377 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
378 CPU_MOVDIR64B_FLAGS.
379 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
380 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
381 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
382 * i386-opc.tbl: Add movidir{i,64b}.
383 * i386-init.h: Regenerated.
384 * i386-tbl.h: Likewise.
385
386 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
387
388 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
389 AddrPrefixOpReg.
390 * i386-opc.h (AddrPrefixOp0): Renamed to ...
391 (AddrPrefixOpReg): This.
392 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
393 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
394
395 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
396
397 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
398 (vle_num_opcodes): Likewise.
399 (spe2_num_opcodes): Likewise.
400 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
401 initialization loop.
402 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
403 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
404 only once.
405
406 2018-05-01 Tamar Christina <tamar.christina@arm.com>
407
408 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
409
410 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
411
412 Makefile.am: Added nfp-dis.c.
413 configure.ac: Added bfd_nfp_arch.
414 disassemble.h: Added print_insn_nfp prototype.
415 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
416 nfp-dis.c: New, for NFP support.
417 po/POTFILES.in: Added nfp-dis.c to the list.
418 Makefile.in: Regenerate.
419 configure: Regenerate.
420
421 2018-04-26 Jan Beulich <jbeulich@suse.com>
422
423 * i386-opc.tbl: Fold various non-memory operand AVX512VL
424 templates into their base ones.
425 * i386-tlb.h: Re-generate.
426
427 2018-04-26 Jan Beulich <jbeulich@suse.com>
428
429 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
430 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
431 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
432 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
433 * i386-init.h: Re-generate.
434
435 2018-04-26 Jan Beulich <jbeulich@suse.com>
436
437 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
438 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
439 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
440 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
441 comment.
442 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
443 and CpuRegMask.
444 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
445 CpuRegMask: Delete.
446 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
447 cpuregzmm, and cpuregmask.
448 * i386-init.h: Re-generate.
449 * i386-tbl.h: Re-generate.
450
451 2018-04-26 Jan Beulich <jbeulich@suse.com>
452
453 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
454 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
455 * i386-init.h: Re-generate.
456
457 2018-04-26 Jan Beulich <jbeulich@suse.com>
458
459 * i386-gen.c (VexImmExt): Delete.
460 * i386-opc.h (VexImmExt, veximmext): Delete.
461 * i386-opc.tbl: Drop all VexImmExt uses.
462 * i386-tlb.h: Re-generate.
463
464 2018-04-25 Jan Beulich <jbeulich@suse.com>
465
466 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
467 register-only forms.
468 * i386-tlb.h: Re-generate.
469
470 2018-04-25 Tamar Christina <tamar.christina@arm.com>
471
472 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
473
474 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
475
476 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
477 PREFIX_0F1C.
478 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
479 (cpu_flags): Add CpuCLDEMOTE.
480 * i386-init.h: Regenerate.
481 * i386-opc.h (enum): Add CpuCLDEMOTE,
482 (i386_cpu_flags): Add cpucldemote.
483 * i386-opc.tbl: Add cldemote.
484 * i386-tbl.h: Regenerate.
485
486 2018-04-16 Alan Modra <amodra@gmail.com>
487
488 * Makefile.am: Remove sh5 and sh64 support.
489 * configure.ac: Likewise.
490 * disassemble.c: Likewise.
491 * disassemble.h: Likewise.
492 * sh-dis.c: Likewise.
493 * sh64-dis.c: Delete.
494 * sh64-opc.c: Delete.
495 * sh64-opc.h: Delete.
496 * Makefile.in: Regenerate.
497 * configure: Regenerate.
498 * po/POTFILES.in: Regenerate.
499
500 2018-04-16 Alan Modra <amodra@gmail.com>
501
502 * Makefile.am: Remove w65 support.
503 * configure.ac: Likewise.
504 * disassemble.c: Likewise.
505 * disassemble.h: Likewise.
506 * w65-dis.c: Delete.
507 * w65-opc.h: Delete.
508 * Makefile.in: Regenerate.
509 * configure: Regenerate.
510 * po/POTFILES.in: Regenerate.
511
512 2018-04-16 Alan Modra <amodra@gmail.com>
513
514 * configure.ac: Remove we32k support.
515 * configure: Regenerate.
516
517 2018-04-16 Alan Modra <amodra@gmail.com>
518
519 * Makefile.am: Remove m88k support.
520 * configure.ac: Likewise.
521 * disassemble.c: Likewise.
522 * disassemble.h: Likewise.
523 * m88k-dis.c: Delete.
524 * Makefile.in: Regenerate.
525 * configure: Regenerate.
526 * po/POTFILES.in: Regenerate.
527
528 2018-04-16 Alan Modra <amodra@gmail.com>
529
530 * Makefile.am: Remove i370 support.
531 * configure.ac: Likewise.
532 * disassemble.c: Likewise.
533 * disassemble.h: Likewise.
534 * i370-dis.c: Delete.
535 * i370-opc.c: Delete.
536 * Makefile.in: Regenerate.
537 * configure: Regenerate.
538 * po/POTFILES.in: Regenerate.
539
540 2018-04-16 Alan Modra <amodra@gmail.com>
541
542 * Makefile.am: Remove h8500 support.
543 * configure.ac: Likewise.
544 * disassemble.c: Likewise.
545 * disassemble.h: Likewise.
546 * h8500-dis.c: Delete.
547 * h8500-opc.h: Delete.
548 * Makefile.in: Regenerate.
549 * configure: Regenerate.
550 * po/POTFILES.in: Regenerate.
551
552 2018-04-16 Alan Modra <amodra@gmail.com>
553
554 * configure.ac: Remove tahoe support.
555 * configure: Regenerate.
556
557 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
558
559 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
560 umwait.
561 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
562 64-bit mode.
563 * i386-tbl.h: Regenerated.
564
565 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
566
567 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
568 PREFIX_MOD_1_0FAE_REG_6.
569 (va_mode): New.
570 (OP_E_register): Use va_mode.
571 * i386-dis-evex.h (prefix_table):
572 New instructions (see prefixes above).
573 * i386-gen.c (cpu_flag_init): Add WAITPKG.
574 (cpu_flags): Likewise.
575 * i386-opc.h (enum): Likewise.
576 (i386_cpu_flags): Likewise.
577 * i386-opc.tbl: Add umonitor, umwait, tpause.
578 * i386-init.h: Regenerate.
579 * i386-tbl.h: Likewise.
580
581 2018-04-11 Alan Modra <amodra@gmail.com>
582
583 * opcodes/i860-dis.c: Delete.
584 * opcodes/i960-dis.c: Delete.
585 * Makefile.am: Remove i860 and i960 support.
586 * configure.ac: Likewise.
587 * disassemble.c: Likewise.
588 * disassemble.h: Likewise.
589 * Makefile.in: Regenerate.
590 * configure: Regenerate.
591 * po/POTFILES.in: Regenerate.
592
593 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
594
595 PR binutils/23025
596 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
597 to 0.
598 (print_insn): Clear vex instead of vex.evex.
599
600 2018-04-04 Nick Clifton <nickc@redhat.com>
601
602 * po/es.po: Updated Spanish translation.
603
604 2018-03-28 Jan Beulich <jbeulich@suse.com>
605
606 * i386-gen.c (opcode_modifiers): Delete VecESize.
607 * i386-opc.h (VecESize): Delete.
608 (struct i386_opcode_modifier): Delete vecesize.
609 * i386-opc.tbl: Drop VecESize.
610 * i386-tlb.h: Re-generate.
611
612 2018-03-28 Jan Beulich <jbeulich@suse.com>
613
614 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
615 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
616 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
617 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
618 * i386-tlb.h: Re-generate.
619
620 2018-03-28 Jan Beulich <jbeulich@suse.com>
621
622 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
623 Fold AVX512 forms
624 * i386-tlb.h: Re-generate.
625
626 2018-03-28 Jan Beulich <jbeulich@suse.com>
627
628 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
629 (vex_len_table): Drop Y for vcvt*2si.
630 (putop): Replace plain 'Y' handling by abort().
631
632 2018-03-28 Nick Clifton <nickc@redhat.com>
633
634 PR 22988
635 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
636 instructions with only a base address register.
637 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
638 handle AARHC64_OPND_SVE_ADDR_R.
639 (aarch64_print_operand): Likewise.
640 * aarch64-asm-2.c: Regenerate.
641 * aarch64_dis-2.c: Regenerate.
642 * aarch64-opc-2.c: Regenerate.
643
644 2018-03-22 Jan Beulich <jbeulich@suse.com>
645
646 * i386-opc.tbl: Drop VecESize from register only insn forms and
647 memory forms not allowing broadcast.
648 * i386-tlb.h: Re-generate.
649
650 2018-03-22 Jan Beulich <jbeulich@suse.com>
651
652 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
653 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
654 sha256*): Drop Disp<N>.
655
656 2018-03-22 Jan Beulich <jbeulich@suse.com>
657
658 * i386-dis.c (EbndS, bnd_swap_mode): New.
659 (prefix_table): Use EbndS.
660 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
661 * i386-opc.tbl (bndmov): Move misplaced Load.
662 * i386-tlb.h: Re-generate.
663
664 2018-03-22 Jan Beulich <jbeulich@suse.com>
665
666 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
667 templates allowing memory operands and folded ones for register
668 only flavors.
669 * i386-tlb.h: Re-generate.
670
671 2018-03-22 Jan Beulich <jbeulich@suse.com>
672
673 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
674 256-bit templates. Drop redundant leftover Disp<N>.
675 * i386-tlb.h: Re-generate.
676
677 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
678
679 * riscv-opc.c (riscv_insn_types): New.
680
681 2018-03-13 Nick Clifton <nickc@redhat.com>
682
683 * po/pt_BR.po: Updated Brazilian Portuguese translation.
684
685 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
686
687 * i386-opc.tbl: Add Optimize to clr.
688 * i386-tbl.h: Regenerated.
689
690 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
691
692 * i386-gen.c (opcode_modifiers): Remove OldGcc.
693 * i386-opc.h (OldGcc): Removed.
694 (i386_opcode_modifier): Remove oldgcc.
695 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
696 instructions for old (<= 2.8.1) versions of gcc.
697 * i386-tbl.h: Regenerated.
698
699 2018-03-08 Jan Beulich <jbeulich@suse.com>
700
701 * i386-opc.h (EVEXDYN): New.
702 * i386-opc.tbl: Fold various AVX512VL templates.
703 * i386-tlb.h: Re-generate.
704
705 2018-03-08 Jan Beulich <jbeulich@suse.com>
706
707 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
708 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
709 vpexpandd, vpexpandq): Fold AFX512VF templates.
710 * i386-tlb.h: Re-generate.
711
712 2018-03-08 Jan Beulich <jbeulich@suse.com>
713
714 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
715 Fold 128- and 256-bit VEX-encoded templates.
716 * i386-tlb.h: Re-generate.
717
718 2018-03-08 Jan Beulich <jbeulich@suse.com>
719
720 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
721 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
722 vpexpandd, vpexpandq): Fold AVX512F templates.
723 * i386-tlb.h: Re-generate.
724
725 2018-03-08 Jan Beulich <jbeulich@suse.com>
726
727 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
728 64-bit templates. Drop Disp<N>.
729 * i386-tlb.h: Re-generate.
730
731 2018-03-08 Jan Beulich <jbeulich@suse.com>
732
733 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
734 and 256-bit templates.
735 * i386-tlb.h: Re-generate.
736
737 2018-03-08 Jan Beulich <jbeulich@suse.com>
738
739 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
740 * i386-tlb.h: Re-generate.
741
742 2018-03-08 Jan Beulich <jbeulich@suse.com>
743
744 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
745 Drop NoAVX.
746 * i386-tlb.h: Re-generate.
747
748 2018-03-08 Jan Beulich <jbeulich@suse.com>
749
750 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
751 * i386-tlb.h: Re-generate.
752
753 2018-03-08 Jan Beulich <jbeulich@suse.com>
754
755 * i386-gen.c (opcode_modifiers): Delete FloatD.
756 * i386-opc.h (FloatD): Delete.
757 (struct i386_opcode_modifier): Delete floatd.
758 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
759 FloatD by D.
760 * i386-tlb.h: Re-generate.
761
762 2018-03-08 Jan Beulich <jbeulich@suse.com>
763
764 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
765
766 2018-03-08 Jan Beulich <jbeulich@suse.com>
767
768 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
769 * i386-tlb.h: Re-generate.
770
771 2018-03-08 Jan Beulich <jbeulich@suse.com>
772
773 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
774 forms.
775 * i386-tlb.h: Re-generate.
776
777 2018-03-07 Alan Modra <amodra@gmail.com>
778
779 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
780 bfd_arch_rs6000.
781 * disassemble.h (print_insn_rs6000): Delete.
782 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
783 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
784 (print_insn_rs6000): Delete.
785
786 2018-03-03 Alan Modra <amodra@gmail.com>
787
788 * sysdep.h (opcodes_error_handler): Define.
789 (_bfd_error_handler): Declare.
790 * Makefile.am: Remove stray #.
791 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
792 EDIT" comment.
793 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
794 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
795 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
796 opcodes_error_handler to print errors. Standardize error messages.
797 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
798 and include opintl.h.
799 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
800 * i386-gen.c: Standardize error messages.
801 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
802 * Makefile.in: Regenerate.
803 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
804 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
805 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
806 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
807 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
808 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
809 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
810 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
811 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
812 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
813 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
814 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
815 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
816
817 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
818
819 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
820 vpsub[bwdq] instructions.
821 * i386-tbl.h: Regenerated.
822
823 2018-03-01 Alan Modra <amodra@gmail.com>
824
825 * configure.ac (ALL_LINGUAS): Sort.
826 * configure: Regenerate.
827
828 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
829
830 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
831 macro by assignements.
832
833 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
834
835 PR gas/22871
836 * i386-gen.c (opcode_modifiers): Add Optimize.
837 * i386-opc.h (Optimize): New enum.
838 (i386_opcode_modifier): Add optimize.
839 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
840 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
841 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
842 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
843 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
844 vpxord and vpxorq.
845 * i386-tbl.h: Regenerated.
846
847 2018-02-26 Alan Modra <amodra@gmail.com>
848
849 * crx-dis.c (getregliststring): Allocate a large enough buffer
850 to silence false positive gcc8 warning.
851
852 2018-02-22 Shea Levy <shea@shealevy.com>
853
854 * disassemble.c (ARCH_riscv): Define if ARCH_all.
855
856 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
857
858 * i386-opc.tbl: Add {rex},
859 * i386-tbl.h: Regenerated.
860
861 2018-02-20 Maciej W. Rozycki <macro@mips.com>
862
863 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
864 (mips16_opcodes): Replace `M' with `m' for "restore".
865
866 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
867
868 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
869
870 2018-02-13 Maciej W. Rozycki <macro@mips.com>
871
872 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
873 variable to `function_index'.
874
875 2018-02-13 Nick Clifton <nickc@redhat.com>
876
877 PR 22823
878 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
879 about truncation of printing.
880
881 2018-02-12 Henry Wong <henry@stuffedcow.net>
882
883 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
884
885 2018-02-05 Nick Clifton <nickc@redhat.com>
886
887 * po/pt_BR.po: Updated Brazilian Portuguese translation.
888
889 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
890
891 * i386-dis.c (enum): Add pconfig.
892 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
893 (cpu_flags): Add CpuPCONFIG.
894 * i386-opc.h (enum): Add CpuPCONFIG.
895 (i386_cpu_flags): Add cpupconfig.
896 * i386-opc.tbl: Add PCONFIG instruction.
897 * i386-init.h: Regenerate.
898 * i386-tbl.h: Likewise.
899
900 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
901
902 * i386-dis.c (enum): Add PREFIX_0F09.
903 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
904 (cpu_flags): Add CpuWBNOINVD.
905 * i386-opc.h (enum): Add CpuWBNOINVD.
906 (i386_cpu_flags): Add cpuwbnoinvd.
907 * i386-opc.tbl: Add WBNOINVD instruction.
908 * i386-init.h: Regenerate.
909 * i386-tbl.h: Likewise.
910
911 2018-01-17 Jim Wilson <jimw@sifive.com>
912
913 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
914
915 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
916
917 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
918 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
919 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
920 (cpu_flags): Add CpuIBT, CpuSHSTK.
921 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
922 (i386_cpu_flags): Add cpuibt, cpushstk.
923 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
924 * i386-init.h: Regenerate.
925 * i386-tbl.h: Likewise.
926
927 2018-01-16 Nick Clifton <nickc@redhat.com>
928
929 * po/pt_BR.po: Updated Brazilian Portugese translation.
930 * po/de.po: Updated German translation.
931
932 2018-01-15 Jim Wilson <jimw@sifive.com>
933
934 * riscv-opc.c (match_c_nop): New.
935 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
936
937 2018-01-15 Nick Clifton <nickc@redhat.com>
938
939 * po/uk.po: Updated Ukranian translation.
940
941 2018-01-13 Nick Clifton <nickc@redhat.com>
942
943 * po/opcodes.pot: Regenerated.
944
945 2018-01-13 Nick Clifton <nickc@redhat.com>
946
947 * configure: Regenerate.
948
949 2018-01-13 Nick Clifton <nickc@redhat.com>
950
951 2.30 branch created.
952
953 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
954
955 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
956 * i386-tbl.h: Regenerate.
957
958 2018-01-10 Jan Beulich <jbeulich@suse.com>
959
960 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
961 * i386-tbl.h: Re-generate.
962
963 2018-01-10 Jan Beulich <jbeulich@suse.com>
964
965 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
966 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
967 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
968 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
969 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
970 Disp8MemShift of AVX512VL forms.
971 * i386-tbl.h: Re-generate.
972
973 2018-01-09 Jim Wilson <jimw@sifive.com>
974
975 * riscv-dis.c (maybe_print_address): If base_reg is zero,
976 then the hi_addr value is zero.
977
978 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
979
980 * arm-dis.c (arm_opcodes): Add csdb.
981 (thumb32_opcodes): Add csdb.
982
983 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
984
985 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
986 * aarch64-asm-2.c: Regenerate.
987 * aarch64-dis-2.c: Regenerate.
988 * aarch64-opc-2.c: Regenerate.
989
990 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
991
992 PR gas/22681
993 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
994 Remove AVX512 vmovd with 64-bit operands.
995 * i386-tbl.h: Regenerated.
996
997 2018-01-05 Jim Wilson <jimw@sifive.com>
998
999 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1000 jalr.
1001
1002 2018-01-03 Alan Modra <amodra@gmail.com>
1003
1004 Update year range in copyright notice of all files.
1005
1006 2018-01-02 Jan Beulich <jbeulich@suse.com>
1007
1008 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1009 and OPERAND_TYPE_REGZMM entries.
1010
1011 For older changes see ChangeLog-2017
1012 \f
1013 Copyright (C) 2018 Free Software Foundation, Inc.
1014
1015 Copying and distribution of this file, with or without modification,
1016 are permitted in any medium without royalty provided the copyright
1017 notice and this notice are preserved.
1018
1019 Local Variables:
1020 mode: change-log
1021 left-margin: 8
1022 fill-column: 74
1023 version-control: never
1024 End: