opcodes/ChangeLog

   1 2018-07-19  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl: Fold AVX512BW templates into their respective
   4         AVX512VL counterparts where possible, using Disp8ShiftVL and
   5         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
   6         IgnoreSize) as appropriate.
   7         * i386-tbl.h: Re-generate.
   8
   9 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  10
  11         * i386-opc.tbl: Fold AVX512CD templates into their respective
  12         AVX512VL counterparts where possible, using Disp8ShiftVL and
  13         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  14         IgnoreSize) as appropriate.
  15         * i386-tbl.h: Re-generate.
  16
  17 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  18
  19         * i386-opc.h (DISP8_SHIFT_VL): New.
  20         * i386-opc.tbl (Disp8ShiftVL):  Define.
  21         (various): Fold AVX512VL templates into their respective
  22         AVX512F counterparts where possible, using Disp8ShiftVL and
  23         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  24         IgnoreSize) as appropriate.
  25         * i386-tbl.h: Re-generate.
  26
  27 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  28
  29         * Makefile.am: Change dependencies and rule for
  30         $(srcdir)/i386-init.h.
  31         * Makefile.in: Re-generate.
  32         * i386-gen.c (process_i386_opcodes): New local variable
  33         "marker". Drop opening of input file. Recognize marker and line
  34         number directives.
  35         * i386-opc.tbl (OPCODE_I386_H): Define.
  36         (i386-opc.h): Include it.
  37         (None): Undefine.
  38
  39 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  40
  41         PR gas/23418
  42         * i386-opc.h (Byte): Update comments.
  43         (Word): Likewise.
  44         (Dword): Likewise.
  45         (Fword): Likewise.
  46         (Qword): Likewise.
  47         (Tbyte): Likewise.
  48         (Xmmword): Likewise.
  49         (Ymmword): Likewise.
  50         (Zmmword): Likewise.
  51         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
  52         vcvttps2uqq.
  53         * i386-tbl.h: Regenerated.
  54
  55 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
  56
  57         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
  58         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
  59         * aarch64-asm-2.c: Regenerate.
  60         * aarch64-dis-2.c: Regenerate.
  61         * aarch64-opc-2.c: Regenerate.
  62
  63 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
  64
  65         PR binutils/23192
  66         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
  67         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
  68         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
  69         sqdmulh, sqrdmulh): Use Em16.
  70
  71 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
  72
  73         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
  74         csdb together with them.
  75         (thumb32_opcodes): Likewise.
  76
  77 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  78
  79         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
  80         requiring 32-bit registers as operands 2 and 3. Improve
  81         comments.
  82         (mwait, mwaitx): Fold templates. Improve comments.
  83         OPERAND_TYPE_INOUTPORTREG.
  84         * i386-tbl.h: Re-generate.
  85
  86 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  87
  88         * i386-gen.c (operand_type_init): Remove
  89         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
  90         OPERAND_TYPE_INOUTPORTREG.
  91         * i386-init.h: Re-generate.
  92
  93 2018-07-11  Jan Beulich  <jbeulich@suse.com>
  94
  95         * i386-opc.tbl (wrssd, wrussd): Add Dword.
  96         (wrssq, wrussq): Add Qword.
  97         * i386-tbl.h: Re-generate.
  98
  99 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-opc.h: Rename OTMax to OTNum.
 102         (OTNumOfUints): Adjust calculation.
 103         (OTUnused): Directly alias to OTNum.
 104
 105 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 106
 107         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 108         `reg_xys'.
 109         (lea_reg_xys): Likewise.
 110         (print_insn_loop_primitive): Rename `reg' local variable to
 111         `reg_dxy'.
 112
 113 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 114
 115         PR binutils/23242
 116         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 117
 118 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 119
 120         PR binutils/23369
 121         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 122         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 123
 124 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 125
 126         PR tdep/8282
 127         * mips-dis.c (mips_option_arg_t): New enumeration.
 128         (mips_options): New variable.
 129         (disassembler_options_mips): New function.
 130         (print_mips_disassembler_options): Reimplement in terms of
 131         `disassembler_options_mips'.
 132         * arm-dis.c (disassembler_options_arm): Adapt to using the
 133         `disasm_options_and_args_t' structure.
 134         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 135         * s390-dis.c (disassembler_options_s390): Likewise.
 136
 137 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 138
 139         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 140         expected result.
 141         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 142         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 143         * testsuite/ld-arm/tls-longplt.d: Likewise.
 144
 145 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 146
 147         PR binutils/23192
 148         * aarch64-asm-2.c: Regenerate.
 149         * aarch64-dis-2.c: Likewise.
 150         * aarch64-opc-2.c: Likewise.
 151         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 152         * aarch64-opc.c (operand_general_constraint_met_p,
 153         aarch64_print_operand): Likewise.
 154         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 155         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 156         fmlal2, fmlsl2.
 157         (AARCH64_OPERANDS): Add Em2.
 158
 159 2018-06-26  Nick Clifton  <nickc@redhat.com>
 160
 161         * po/uk.po: Updated Ukranian translation.
 162         * po/de.po: Updated German translation.
 163         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 164
 165 2018-06-26  Nick Clifton  <nickc@redhat.com>
 166
 167         * nfp-dis.c: Fix spelling mistake.
 168
 169 2018-06-24  Nick Clifton  <nickc@redhat.com>
 170
 171         * configure: Regenerate.
 172         * po/opcodes.pot: Regenerate.
 173
 174 2018-06-24  Nick Clifton  <nickc@redhat.com>
 175
 176         2.31 branch created.
 177
 178 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 179
 180         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 181         * aarch64-asm-2.c: Regenerate.
 182         * aarch64-dis-2.c: Likewise.
 183
 184 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 185
 186         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 187         `-M ginv' option description.
 188
 189 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 190
 191         PR gas/23305
 192         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 193         la and lla.
 194
 195 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 196
 197         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 198         * configure.ac: Remove AC_PREREQ.
 199         * Makefile.in: Re-generate.
 200         * aclocal.m4: Re-generate.
 201         * configure: Re-generate.
 202
 203 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 204
 205         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 206         mips64r6 descriptors.
 207         (parse_mips_ase_option): Handle -Mginv option.
 208         (print_mips_disassembler_options): Document -Mginv.
 209         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 210         (GINV): New macro.
 211         (mips_opcodes): Define ginvi and ginvt.
 212
 213 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 214             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 215
 216         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 217         * mips-opc.c (CRC, CRC64): New macros.
 218         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 219         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 220         crc32cd for CRC64.
 221
 222 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 223
 224         PR 20319
 225         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 226         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 227
 228 2018-06-06  Alan Modra  <amodra@gmail.com>
 229
 230         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 231         setjmp.  Move init for some other vars later too.
 232
 233 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 234
 235         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 236         (dis_private): Add new fields for property section tracking.
 237         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 238         (xtensa_instruction_fits): New functions.
 239         (fetch_data): Bump minimal fetch size to 4.
 240         (print_insn_xtensa): Make struct dis_private static.
 241         Load and prepare property table on section change.
 242         Don't disassemble literals. Don't disassemble instructions that
 243         cross property table boundaries.
 244
 245 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 246
 247         * configure: Regenerated.
 248
 249 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 250
 251         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 252         * i386-tbl.h: Re-generate.
 253
 254 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl (sldt, str): Add NoRex64.
 257         * i386-tbl.h: Re-generate.
 258
 259 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 260
 261         * i386-opc.tbl (invpcid): Add Oword.
 262         * i386-tbl.h: Re-generate.
 263
 264 2018-06-01  Alan Modra  <amodra@gmail.com>
 265
 266         * sysdep.h (_bfd_error_handler): Don't declare.
 267         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 268         * rl78-decode.opc: Likewise.
 269         * msp430-decode.c: Regenerate.
 270         * rl78-decode.c: Regenerate.
 271
 272 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 273
 274         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 275         * i386-init.h : Regenerated.
 276
 277 2018-05-25  Alan Modra  <amodra@gmail.com>
 278
 279         * Makefile.in: Regenerate.
 280         * po/POTFILES.in: Regenerate.
 281
 282 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 283
 284         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 285         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 286         (insert_bab, extract_bab, insert_btab, extract_btab,
 287         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 288         (BAT, BBA VBA RBS XB6S): Delete macros.
 289         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 290         (BB, BD, RBX, XC6): Update for new macros.
 291         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 292         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 293         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 294         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 295
 296 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 297
 298         * Makefile.am: Add support for s12z architecture.
 299         * configure.ac: Likewise.
 300         * disassemble.c: Likewise.
 301         * disassemble.h: Likewise.
 302         * Makefile.in: Regenerate.
 303         * configure: Regenerate.
 304         * s12z-dis.c: New file.
 305         * s12z.h: New file.
 306
 307 2018-05-18  Alan Modra  <amodra@gmail.com>
 308
 309         * nfp-dis.c: Don't #include libbfd.h.
 310         (init_nfp3200_priv): Use bfd_get_section_contents.
 311         (nit_nfp6000_mecsr_sec): Likewise.
 312
 313 2018-05-17  Nick Clifton  <nickc@redhat.com>
 314
 315         * po/zh_CN.po: Updated simplified Chinese translation.
 316
 317 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 318
 319         PR binutils/23109
 320         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 321         * aarch64-dis-2.c: Regenerate.
 322
 323 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 324
 325         PR binutils/21446
 326         * aarch64-asm.c (opintl.h): Include.
 327         (aarch64_ins_sysreg): Enforce read/write constraints.
 328         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 329         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 330         (F_REG_READ, F_REG_WRITE): New.
 331         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 332         AARCH64_OPND_SYSREG.
 333         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 334         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 335         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 336         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 337         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 338         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 339         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 340         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 341         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 342         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 343         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 344         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 345         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 346         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 347         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 348         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 349         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 350
 351 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 352
 353         PR binutils/21446
 354         * aarch64-dis.c (no_notes: New.
 355         (parse_aarch64_dis_option): Support notes.
 356         (aarch64_decode_insn, print_operands): Likewise.
 357         (print_aarch64_disassembler_options): Document notes.
 358         * aarch64-opc.c (aarch64_print_operand): Support notes.
 359
 360 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 361
 362         PR binutils/21446
 363         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 364         and take error struct.
 365         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 366         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 367         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 368         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 369         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 370         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 371         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 372         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 373         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 374         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 375         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 376         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 377         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 378         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 379         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 380         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 381         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 382         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 383         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 384         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 385         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 386         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 387         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 388         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 389         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 390         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 391         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 392         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 393         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 394         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 395         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 396         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 397         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 398         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 399         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 400         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 401         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 402         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 403         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 404         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 405         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 406         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 407         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 408         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 409         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 410         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 411         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 412         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 413         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 414         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 415         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 416         (determine_disassembling_preference, aarch64_decode_insn,
 417         print_insn_aarch64_word, print_insn_data): Take errors struct.
 418         (print_insn_aarch64): Use errors.
 419         * aarch64-asm-2.c: Regenerate.
 420         * aarch64-dis-2.c: Regenerate.
 421         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 422         boolean in aarch64_insert_operan.
 423         (print_operand_extractor): Likewise.
 424         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 425
 426 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 427
 428         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 429
 430 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 431
 432         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 433
 434 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 435
 436         * cr16-opc.c (cr16_instruction): Comment typo fix.
 437         * hppa-dis.c (print_insn_hppa): Likewise.
 438
 439 2018-05-08  Jim Wilson  <jimw@sifive.com>
 440
 441         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 442         (match_c_slli64, match_srxi_as_c_srxi): New.
 443         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 444         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 445         <c.slli, c.srli, c.srai>: Use match_s_slli.
 446         <c.slli64, c.srli64, c.srai64>: New.
 447
 448 2018-05-08  Alan Modra  <amodra@gmail.com>
 449
 450         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 451         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 452         partition opcode space for index lookup.
 453
 454 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 455
 456         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 457         <insn_length>: ...with this.  Update usage.
 458         Remove duplicate call to *info->memory_error_func.
 459
 460 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 461             H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * i386-dis.c (Gva): New.
 464         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 465         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 466         (prefix_table): New instructions (see prefix above).
 467         (mod_table): New instructions (see prefix above).
 468         (OP_G): Handle va_mode.
 469         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 470         CPU_MOVDIR64B_FLAGS.
 471         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 472         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 473         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 474         * i386-opc.tbl: Add movidir{i,64b}.
 475         * i386-init.h: Regenerated.
 476         * i386-tbl.h: Likewise.
 477
 478 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 479
 480         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 481         AddrPrefixOpReg.
 482         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 483         (AddrPrefixOpReg): This.
 484         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 485         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 486
 487 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 488
 489         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 490         (vle_num_opcodes): Likewise.
 491         (spe2_num_opcodes): Likewise.
 492         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 493         initialization loop.
 494         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 495         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 496         only once.
 497
 498 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 499
 500         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 501
 502 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 503
 504         Makefile.am: Added nfp-dis.c.
 505         configure.ac: Added bfd_nfp_arch.
 506         disassemble.h: Added print_insn_nfp prototype.
 507         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 508         nfp-dis.c: New, for NFP support.
 509         po/POTFILES.in: Added nfp-dis.c to the list.
 510         Makefile.in: Regenerate.
 511         configure: Regenerate.
 512
 513 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 514
 515         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 516         templates into their base ones.
 517         * i386-tlb.h: Re-generate.
 518
 519 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 522         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 523         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 524         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 525         * i386-init.h: Re-generate.
 526
 527 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 530         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 531         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 532         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 533         comment.
 534         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 535         and CpuRegMask.
 536         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 537         CpuRegMask: Delete.
 538         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 539         cpuregzmm, and cpuregmask.
 540         * i386-init.h: Re-generate.
 541         * i386-tbl.h: Re-generate.
 542
 543 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 544
 545         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 546         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 547         * i386-init.h: Re-generate.
 548
 549 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-gen.c (VexImmExt): Delete.
 552         * i386-opc.h (VexImmExt, veximmext): Delete.
 553         * i386-opc.tbl: Drop all VexImmExt uses.
 554         * i386-tlb.h: Re-generate.
 555
 556 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 557
 558         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 559         register-only forms.
 560         * i386-tlb.h: Re-generate.
 561
 562 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 563
 564         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 565
 566 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 567
 568         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 569         PREFIX_0F1C.
 570         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 571         (cpu_flags): Add CpuCLDEMOTE.
 572         * i386-init.h: Regenerate.
 573         * i386-opc.h (enum): Add CpuCLDEMOTE,
 574         (i386_cpu_flags): Add cpucldemote.
 575         * i386-opc.tbl: Add cldemote.
 576         * i386-tbl.h: Regenerate.
 577
 578 2018-04-16  Alan Modra  <amodra@gmail.com>
 579
 580         * Makefile.am: Remove sh5 and sh64 support.
 581         * configure.ac: Likewise.
 582         * disassemble.c: Likewise.
 583         * disassemble.h: Likewise.
 584         * sh-dis.c: Likewise.
 585         * sh64-dis.c: Delete.
 586         * sh64-opc.c: Delete.
 587         * sh64-opc.h: Delete.
 588         * Makefile.in: Regenerate.
 589         * configure: Regenerate.
 590         * po/POTFILES.in: Regenerate.
 591
 592 2018-04-16  Alan Modra  <amodra@gmail.com>
 593
 594         * Makefile.am: Remove w65 support.
 595         * configure.ac: Likewise.
 596         * disassemble.c: Likewise.
 597         * disassemble.h: Likewise.
 598         * w65-dis.c: Delete.
 599         * w65-opc.h: Delete.
 600         * Makefile.in: Regenerate.
 601         * configure: Regenerate.
 602         * po/POTFILES.in: Regenerate.
 603
 604 2018-04-16  Alan Modra  <amodra@gmail.com>
 605
 606         * configure.ac: Remove we32k support.
 607         * configure: Regenerate.
 608
 609 2018-04-16  Alan Modra  <amodra@gmail.com>
 610
 611         * Makefile.am: Remove m88k support.
 612         * configure.ac: Likewise.
 613         * disassemble.c: Likewise.
 614         * disassemble.h: Likewise.
 615         * m88k-dis.c: Delete.
 616         * Makefile.in: Regenerate.
 617         * configure: Regenerate.
 618         * po/POTFILES.in: Regenerate.
 619
 620 2018-04-16  Alan Modra  <amodra@gmail.com>
 621
 622         * Makefile.am: Remove i370 support.
 623         * configure.ac: Likewise.
 624         * disassemble.c: Likewise.
 625         * disassemble.h: Likewise.
 626         * i370-dis.c: Delete.
 627         * i370-opc.c: Delete.
 628         * Makefile.in: Regenerate.
 629         * configure: Regenerate.
 630         * po/POTFILES.in: Regenerate.
 631
 632 2018-04-16  Alan Modra  <amodra@gmail.com>
 633
 634         * Makefile.am: Remove h8500 support.
 635         * configure.ac: Likewise.
 636         * disassemble.c: Likewise.
 637         * disassemble.h: Likewise.
 638         * h8500-dis.c: Delete.
 639         * h8500-opc.h: Delete.
 640         * Makefile.in: Regenerate.
 641         * configure: Regenerate.
 642         * po/POTFILES.in: Regenerate.
 643
 644 2018-04-16  Alan Modra  <amodra@gmail.com>
 645
 646         * configure.ac: Remove tahoe support.
 647         * configure: Regenerate.
 648
 649 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 652         umwait.
 653         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 654         64-bit mode.
 655         * i386-tbl.h: Regenerated.
 656
 657 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 658
 659         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 660         PREFIX_MOD_1_0FAE_REG_6.
 661         (va_mode): New.
 662         (OP_E_register): Use va_mode.
 663         * i386-dis-evex.h (prefix_table):
 664         New instructions (see prefixes above).
 665         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 666         (cpu_flags): Likewise.
 667         * i386-opc.h (enum): Likewise.
 668         (i386_cpu_flags): Likewise.
 669         * i386-opc.tbl: Add umonitor, umwait, tpause.
 670         * i386-init.h: Regenerate.
 671         * i386-tbl.h: Likewise.
 672
 673 2018-04-11  Alan Modra  <amodra@gmail.com>
 674
 675         * opcodes/i860-dis.c: Delete.
 676         * opcodes/i960-dis.c: Delete.
 677         * Makefile.am: Remove i860 and i960 support.
 678         * configure.ac: Likewise.
 679         * disassemble.c: Likewise.
 680         * disassemble.h: Likewise.
 681         * Makefile.in: Regenerate.
 682         * configure: Regenerate.
 683         * po/POTFILES.in: Regenerate.
 684
 685 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 686
 687         PR binutils/23025
 688         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 689         to 0.
 690         (print_insn): Clear vex instead of vex.evex.
 691
 692 2018-04-04  Nick Clifton  <nickc@redhat.com>
 693
 694         * po/es.po: Updated Spanish translation.
 695
 696 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-gen.c (opcode_modifiers): Delete VecESize.
 699         * i386-opc.h (VecESize): Delete.
 700         (struct i386_opcode_modifier): Delete vecesize.
 701         * i386-opc.tbl: Drop VecESize.
 702         * i386-tlb.h: Re-generate.
 703
 704 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 705
 706         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 707         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 708         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 709         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 710         * i386-tlb.h: Re-generate.
 711
 712 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 715         Fold AVX512 forms
 716         * i386-tlb.h: Re-generate.
 717
 718 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 719
 720         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 721         (vex_len_table): Drop Y for vcvt*2si.
 722         (putop): Replace plain 'Y' handling by abort().
 723
 724 2018-03-28  Nick Clifton  <nickc@redhat.com>
 725
 726         PR 22988
 727         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 728         instructions with only a base address register.
 729         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 730         handle AARHC64_OPND_SVE_ADDR_R.
 731         (aarch64_print_operand): Likewise.
 732         * aarch64-asm-2.c: Regenerate.
 733         * aarch64_dis-2.c: Regenerate.
 734         * aarch64-opc-2.c: Regenerate.
 735
 736 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-opc.tbl: Drop VecESize from register only insn forms and
 739         memory forms not allowing broadcast.
 740         * i386-tlb.h: Re-generate.
 741
 742 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 745         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 746         sha256*): Drop Disp<N>.
 747
 748 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-dis.c (EbndS, bnd_swap_mode): New.
 751         (prefix_table): Use EbndS.
 752         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 753         * i386-opc.tbl (bndmov): Move misplaced Load.
 754         * i386-tlb.h: Re-generate.
 755
 756 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 759         templates allowing memory operands and folded ones for register
 760         only flavors.
 761         * i386-tlb.h: Re-generate.
 762
 763 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 764
 765         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 766         256-bit templates. Drop redundant leftover Disp<N>.
 767         * i386-tlb.h: Re-generate.
 768
 769 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 770
 771         * riscv-opc.c (riscv_insn_types): New.
 772
 773 2018-03-13  Nick Clifton  <nickc@redhat.com>
 774
 775         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 776
 777 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 778
 779         * i386-opc.tbl: Add Optimize to clr.
 780         * i386-tbl.h: Regenerated.
 781
 782 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 783
 784         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 785         * i386-opc.h (OldGcc): Removed.
 786         (i386_opcode_modifier): Remove oldgcc.
 787         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 788         instructions for old (<= 2.8.1) versions of gcc.
 789         * i386-tbl.h: Regenerated.
 790
 791 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 792
 793         * i386-opc.h (EVEXDYN): New.
 794         * i386-opc.tbl: Fold various AVX512VL templates.
 795         * i386-tlb.h: Re-generate.
 796
 797 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 798
 799         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 800         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 801         vpexpandd, vpexpandq): Fold AFX512VF templates.
 802         * i386-tlb.h: Re-generate.
 803
 804 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 807         Fold 128- and 256-bit VEX-encoded templates.
 808         * i386-tlb.h: Re-generate.
 809
 810 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 811
 812         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 813         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 814         vpexpandd, vpexpandq): Fold AVX512F templates.
 815         * i386-tlb.h: Re-generate.
 816
 817 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 818
 819         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 820         64-bit templates. Drop Disp<N>.
 821         * i386-tlb.h: Re-generate.
 822
 823 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 826         and 256-bit templates.
 827         * i386-tlb.h: Re-generate.
 828
 829 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 830
 831         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 832         * i386-tlb.h: Re-generate.
 833
 834 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 837         Drop NoAVX.
 838         * i386-tlb.h: Re-generate.
 839
 840 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 841
 842         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 843         * i386-tlb.h: Re-generate.
 844
 845 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 846
 847         * i386-gen.c (opcode_modifiers): Delete FloatD.
 848         * i386-opc.h (FloatD): Delete.
 849         (struct i386_opcode_modifier): Delete floatd.
 850         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 851         FloatD by D.
 852         * i386-tlb.h: Re-generate.
 853
 854 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 857
 858 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 859
 860         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 861         * i386-tlb.h: Re-generate.
 862
 863 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 864
 865         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 866         forms.
 867         * i386-tlb.h: Re-generate.
 868
 869 2018-03-07  Alan Modra  <amodra@gmail.com>
 870
 871         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 872         bfd_arch_rs6000.
 873         * disassemble.h (print_insn_rs6000): Delete.
 874         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 875         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 876         (print_insn_rs6000): Delete.
 877
 878 2018-03-03  Alan Modra  <amodra@gmail.com>
 879
 880         * sysdep.h (opcodes_error_handler): Define.
 881         (_bfd_error_handler): Declare.
 882         * Makefile.am: Remove stray #.
 883         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 884         EDIT" comment.
 885         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 886         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 887         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 888         opcodes_error_handler to print errors.  Standardize error messages.
 889         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 890         and include opintl.h.
 891         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 892         * i386-gen.c: Standardize error messages.
 893         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 894         * Makefile.in: Regenerate.
 895         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 896         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 897         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 898         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 899         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 900         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 901         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 902         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 903         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 904         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 905         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 906         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 907         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 908
 909 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 910
 911         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 912         vpsub[bwdq] instructions.
 913         * i386-tbl.h: Regenerated.
 914
 915 2018-03-01  Alan Modra  <amodra@gmail.com>
 916
 917         * configure.ac (ALL_LINGUAS): Sort.
 918         * configure: Regenerate.
 919
 920 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 921
 922         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 923         macro by assignements.
 924
 925 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 926
 927         PR gas/22871
 928         * i386-gen.c (opcode_modifiers): Add Optimize.
 929         * i386-opc.h (Optimize): New enum.
 930         (i386_opcode_modifier): Add optimize.
 931         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 932         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 933         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 934         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 935         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 936         vpxord and vpxorq.
 937         * i386-tbl.h: Regenerated.
 938
 939 2018-02-26  Alan Modra  <amodra@gmail.com>
 940
 941         * crx-dis.c (getregliststring): Allocate a large enough buffer
 942         to silence false positive gcc8 warning.
 943
 944 2018-02-22  Shea Levy <shea@shealevy.com>
 945
 946         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 947
 948 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 949
 950         * i386-opc.tbl: Add {rex},
 951         * i386-tbl.h: Regenerated.
 952
 953 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 954
 955         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 956         (mips16_opcodes): Replace `M' with `m' for "restore".
 957
 958 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 959
 960         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 961
 962 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 963
 964         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 965         variable to `function_index'.
 966
 967 2018-02-13  Nick Clifton  <nickc@redhat.com>
 968
 969         PR 22823
 970         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 971         about truncation of printing.
 972
 973 2018-02-12  Henry Wong <henry@stuffedcow.net>
 974
 975         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 976
 977 2018-02-05  Nick Clifton  <nickc@redhat.com>
 978
 979         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 980
 981 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 982
 983         * i386-dis.c (enum): Add pconfig.
 984         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 985         (cpu_flags): Add CpuPCONFIG.
 986         * i386-opc.h (enum): Add CpuPCONFIG.
 987         (i386_cpu_flags): Add cpupconfig.
 988         * i386-opc.tbl: Add PCONFIG instruction.
 989         * i386-init.h: Regenerate.
 990         * i386-tbl.h: Likewise.
 991
 992 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 993
 994         * i386-dis.c (enum): Add PREFIX_0F09.
 995         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 996         (cpu_flags): Add CpuWBNOINVD.
 997         * i386-opc.h (enum): Add CpuWBNOINVD.
 998         (i386_cpu_flags): Add cpuwbnoinvd.
 999         * i386-opc.tbl: Add WBNOINVD instruction.
1000         * i386-init.h: Regenerate.
1001         * i386-tbl.h: Likewise.
1002
1003 2018-01-17  Jim Wilson  <jimw@sifive.com>
1004
1005         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1006
1007 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1008
1009         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1010         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1011         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1012         (cpu_flags): Add CpuIBT, CpuSHSTK.
1013         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1014         (i386_cpu_flags): Add cpuibt, cpushstk.
1015         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1016         * i386-init.h: Regenerate.
1017         * i386-tbl.h: Likewise.
1018
1019 2018-01-16  Nick Clifton  <nickc@redhat.com>
1020
1021         * po/pt_BR.po: Updated Brazilian Portugese translation.
1022         * po/de.po: Updated German translation.
1023
1024 2018-01-15  Jim Wilson  <jimw@sifive.com>
1025
1026         * riscv-opc.c (match_c_nop): New.
1027         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1028
1029 2018-01-15  Nick Clifton  <nickc@redhat.com>
1030
1031         * po/uk.po: Updated Ukranian translation.
1032
1033 2018-01-13  Nick Clifton  <nickc@redhat.com>
1034
1035         * po/opcodes.pot: Regenerated.
1036
1037 2018-01-13  Nick Clifton  <nickc@redhat.com>
1038
1039         * configure: Regenerate.
1040
1041 2018-01-13  Nick Clifton  <nickc@redhat.com>
1042
1043         2.30 branch created.
1044
1045 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1046
1047         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1048         * i386-tbl.h: Regenerate.
1049
1050 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1051
1052         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1053         * i386-tbl.h: Re-generate.
1054
1055 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1056
1057         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1058         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1059         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1060         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1061         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1062         Disp8MemShift of AVX512VL forms.
1063         * i386-tbl.h: Re-generate.
1064
1065 2018-01-09  Jim Wilson  <jimw@sifive.com>
1066
1067         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1068         then the hi_addr value is zero.
1069
1070 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1071
1072         * arm-dis.c (arm_opcodes): Add csdb.
1073         (thumb32_opcodes): Add csdb.
1074
1075 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1076
1077         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1078         * aarch64-asm-2.c: Regenerate.
1079         * aarch64-dis-2.c: Regenerate.
1080         * aarch64-opc-2.c: Regenerate.
1081
1082 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1083
1084         PR gas/22681
1085         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1086         Remove AVX512 vmovd with 64-bit operands.
1087         * i386-tbl.h: Regenerated.
1088
1089 2018-01-05  Jim Wilson  <jimw@sifive.com>
1090
1091         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1092         jalr.
1093
1094 2018-01-03  Alan Modra  <amodra@gmail.com>
1095
1096         Update year range in copyright notice of all files.
1097
1098 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1099
1100         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1101         and OPERAND_TYPE_REGZMM entries.
1102
1103 For older changes see ChangeLog-2017
1104 \f
1105 Copyright (C) 2018 Free Software Foundation, Inc.
1106
1107 Copying and distribution of this file, with or without modification,
1108 are permitted in any medium without royalty provided the copyright
1109 notice and this notice are preserved.
1110
1111 Local Variables:
1112 mode: change-log
1113 left-margin: 8
1114 fill-column: 74
1115 version-control: never
1116 End: