opcodes/ChangeLog

   1 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
   2
   3         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
   4         `reg_xys'.
   5         (lea_reg_xys): Likewise.
   6         (print_insn_loop_primitive): Rename `reg' local variable to
   7         `reg_dxy'.
   8
   9 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
  10
  11         PR binutils/23242
  12         * aarch64-tbl.h (ldarh): Fix disassembly mask.
  13
  14 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
  15
  16         PR binutils/23369
  17         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
  18         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
  19
  20 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
  21
  22         PR tdep/8282
  23         * mips-dis.c (mips_option_arg_t): New enumeration.
  24         (mips_options): New variable.
  25         (disassembler_options_mips): New function.
  26         (print_mips_disassembler_options): Reimplement in terms of
  27         `disassembler_options_mips'.
  28         * arm-dis.c (disassembler_options_arm): Adapt to using the
  29         `disasm_options_and_args_t' structure.
  30         * ppc-dis.c (disassembler_options_powerpc): Likewise.
  31         * s390-dis.c (disassembler_options_s390): Likewise.
  32
  33 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  34
  35         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
  36         expected result.
  37         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
  38         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
  39         * testsuite/ld-arm/tls-longplt.d: Likewise.
  40
  41 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
  42
  43         PR binutils/23192
  44         * aarch64-asm-2.c: Regenerate.
  45         * aarch64-dis-2.c: Likewise.
  46         * aarch64-opc-2.c: Likewise.
  47         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
  48         * aarch64-opc.c (operand_general_constraint_met_p,
  49         aarch64_print_operand): Likewise.
  50         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
  51         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
  52         fmlal2, fmlsl2.
  53         (AARCH64_OPERANDS): Add Em2.
  54
  55 2018-06-26  Nick Clifton  <nickc@redhat.com>
  56
  57         * po/uk.po: Updated Ukranian translation.
  58         * po/de.po: Updated German translation.
  59         * po/pt_BR.po: Updated Brazilian Portuguese translation.
  60
  61 2018-06-26  Nick Clifton  <nickc@redhat.com>
  62
  63         * nfp-dis.c: Fix spelling mistake.
  64
  65 2018-06-24  Nick Clifton  <nickc@redhat.com>
  66
  67         * configure: Regenerate.
  68         * po/opcodes.pot: Regenerate.
  69
  70 2018-06-24  Nick Clifton  <nickc@redhat.com>
  71
  72         2.31 branch created.
  73
  74 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
  75
  76         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
  77         * aarch64-asm-2.c: Regenerate.
  78         * aarch64-dis-2.c: Likewise.
  79
  80 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
  81
  82         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
  83         `-M ginv' option description.
  84
  85 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
  86
  87         PR gas/23305
  88         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
  89         la and lla.
  90
  91 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
  92
  93         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
  94         * configure.ac: Remove AC_PREREQ.
  95         * Makefile.in: Re-generate.
  96         * aclocal.m4: Re-generate.
  97         * configure: Re-generate.
  98
  99 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 100
 101         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 102         mips64r6 descriptors.
 103         (parse_mips_ase_option): Handle -Mginv option.
 104         (print_mips_disassembler_options): Document -Mginv.
 105         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 106         (GINV): New macro.
 107         (mips_opcodes): Define ginvi and ginvt.
 108
 109 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 110             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 111
 112         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 113         * mips-opc.c (CRC, CRC64): New macros.
 114         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 115         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 116         crc32cd for CRC64.
 117
 118 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 119
 120         PR 20319
 121         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 122         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 123
 124 2018-06-06  Alan Modra  <amodra@gmail.com>
 125
 126         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 127         setjmp.  Move init for some other vars later too.
 128
 129 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 130
 131         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 132         (dis_private): Add new fields for property section tracking.
 133         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 134         (xtensa_instruction_fits): New functions.
 135         (fetch_data): Bump minimal fetch size to 4.
 136         (print_insn_xtensa): Make struct dis_private static.
 137         Load and prepare property table on section change.
 138         Don't disassemble literals. Don't disassemble instructions that
 139         cross property table boundaries.
 140
 141 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 142
 143         * configure: Regenerated.
 144
 145 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 146
 147         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 148         * i386-tbl.h: Re-generate.
 149
 150 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-opc.tbl (sldt, str): Add NoRex64.
 153         * i386-tbl.h: Re-generate.
 154
 155 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-opc.tbl (invpcid): Add Oword.
 158         * i386-tbl.h: Re-generate.
 159
 160 2018-06-01  Alan Modra  <amodra@gmail.com>
 161
 162         * sysdep.h (_bfd_error_handler): Don't declare.
 163         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 164         * rl78-decode.opc: Likewise.
 165         * msp430-decode.c: Regenerate.
 166         * rl78-decode.c: Regenerate.
 167
 168 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 169
 170         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 171         * i386-init.h : Regenerated.
 172
 173 2018-05-25  Alan Modra  <amodra@gmail.com>
 174
 175         * Makefile.in: Regenerate.
 176         * po/POTFILES.in: Regenerate.
 177
 178 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 179
 180         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 181         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 182         (insert_bab, extract_bab, insert_btab, extract_btab,
 183         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 184         (BAT, BBA VBA RBS XB6S): Delete macros.
 185         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 186         (BB, BD, RBX, XC6): Update for new macros.
 187         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 188         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 189         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 190         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 191
 192 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 193
 194         * Makefile.am: Add support for s12z architecture.
 195         * configure.ac: Likewise.
 196         * disassemble.c: Likewise.
 197         * disassemble.h: Likewise.
 198         * Makefile.in: Regenerate.
 199         * configure: Regenerate.
 200         * s12z-dis.c: New file.
 201         * s12z.h: New file.
 202
 203 2018-05-18  Alan Modra  <amodra@gmail.com>
 204
 205         * nfp-dis.c: Don't #include libbfd.h.
 206         (init_nfp3200_priv): Use bfd_get_section_contents.
 207         (nit_nfp6000_mecsr_sec): Likewise.
 208
 209 2018-05-17  Nick Clifton  <nickc@redhat.com>
 210
 211         * po/zh_CN.po: Updated simplified Chinese translation.
 212
 213 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 214
 215         PR binutils/23109
 216         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 217         * aarch64-dis-2.c: Regenerate.
 218
 219 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 220
 221         PR binutils/21446
 222         * aarch64-asm.c (opintl.h): Include.
 223         (aarch64_ins_sysreg): Enforce read/write constraints.
 224         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 225         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 226         (F_REG_READ, F_REG_WRITE): New.
 227         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 228         AARCH64_OPND_SYSREG.
 229         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 230         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 231         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 232         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 233         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 234         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 235         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 236         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 237         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 238         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 239         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 240         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 241         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 242         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 243         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 244         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 245         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 246
 247 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 248
 249         PR binutils/21446
 250         * aarch64-dis.c (no_notes: New.
 251         (parse_aarch64_dis_option): Support notes.
 252         (aarch64_decode_insn, print_operands): Likewise.
 253         (print_aarch64_disassembler_options): Document notes.
 254         * aarch64-opc.c (aarch64_print_operand): Support notes.
 255
 256 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 257
 258         PR binutils/21446
 259         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 260         and take error struct.
 261         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 262         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 263         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 264         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 265         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 266         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 267         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 268         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 269         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 270         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 271         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 272         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 273         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 274         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 275         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 276         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 277         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 278         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 279         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 280         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 281         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 282         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 283         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 284         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 285         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 286         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 287         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 288         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 289         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 290         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 291         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 292         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 293         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 294         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 295         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 296         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 297         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 298         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 299         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 300         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 301         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 302         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 303         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 304         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 305         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 306         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 307         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 308         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 309         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 310         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 311         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 312         (determine_disassembling_preference, aarch64_decode_insn,
 313         print_insn_aarch64_word, print_insn_data): Take errors struct.
 314         (print_insn_aarch64): Use errors.
 315         * aarch64-asm-2.c: Regenerate.
 316         * aarch64-dis-2.c: Regenerate.
 317         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 318         boolean in aarch64_insert_operan.
 319         (print_operand_extractor): Likewise.
 320         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 321
 322 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 323
 324         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 325
 326 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 329
 330 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 331
 332         * cr16-opc.c (cr16_instruction): Comment typo fix.
 333         * hppa-dis.c (print_insn_hppa): Likewise.
 334
 335 2018-05-08  Jim Wilson  <jimw@sifive.com>
 336
 337         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 338         (match_c_slli64, match_srxi_as_c_srxi): New.
 339         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 340         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 341         <c.slli, c.srli, c.srai>: Use match_s_slli.
 342         <c.slli64, c.srli64, c.srai64>: New.
 343
 344 2018-05-08  Alan Modra  <amodra@gmail.com>
 345
 346         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 347         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 348         partition opcode space for index lookup.
 349
 350 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 351
 352         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 353         <insn_length>: ...with this.  Update usage.
 354         Remove duplicate call to *info->memory_error_func.
 355
 356 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 357             H.J. Lu  <hongjiu.lu@intel.com>
 358
 359         * i386-dis.c (Gva): New.
 360         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 361         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 362         (prefix_table): New instructions (see prefix above).
 363         (mod_table): New instructions (see prefix above).
 364         (OP_G): Handle va_mode.
 365         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 366         CPU_MOVDIR64B_FLAGS.
 367         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 368         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 369         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 370         * i386-opc.tbl: Add movidir{i,64b}.
 371         * i386-init.h: Regenerated.
 372         * i386-tbl.h: Likewise.
 373
 374 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 375
 376         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 377         AddrPrefixOpReg.
 378         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 379         (AddrPrefixOpReg): This.
 380         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 381         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 382
 383 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 384
 385         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 386         (vle_num_opcodes): Likewise.
 387         (spe2_num_opcodes): Likewise.
 388         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 389         initialization loop.
 390         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 391         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 392         only once.
 393
 394 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 395
 396         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 397
 398 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 399
 400         Makefile.am: Added nfp-dis.c.
 401         configure.ac: Added bfd_nfp_arch.
 402         disassemble.h: Added print_insn_nfp prototype.
 403         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 404         nfp-dis.c: New, for NFP support.
 405         po/POTFILES.in: Added nfp-dis.c to the list.
 406         Makefile.in: Regenerate.
 407         configure: Regenerate.
 408
 409 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 410
 411         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 412         templates into their base ones.
 413         * i386-tlb.h: Re-generate.
 414
 415 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 418         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 419         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 420         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 421         * i386-init.h: Re-generate.
 422
 423 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 426         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 427         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 428         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 429         comment.
 430         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 431         and CpuRegMask.
 432         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 433         CpuRegMask: Delete.
 434         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 435         cpuregzmm, and cpuregmask.
 436         * i386-init.h: Re-generate.
 437         * i386-tbl.h: Re-generate.
 438
 439 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 440
 441         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 442         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 443         * i386-init.h: Re-generate.
 444
 445 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-gen.c (VexImmExt): Delete.
 448         * i386-opc.h (VexImmExt, veximmext): Delete.
 449         * i386-opc.tbl: Drop all VexImmExt uses.
 450         * i386-tlb.h: Re-generate.
 451
 452 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 455         register-only forms.
 456         * i386-tlb.h: Re-generate.
 457
 458 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 459
 460         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 461
 462 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 463
 464         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 465         PREFIX_0F1C.
 466         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 467         (cpu_flags): Add CpuCLDEMOTE.
 468         * i386-init.h: Regenerate.
 469         * i386-opc.h (enum): Add CpuCLDEMOTE,
 470         (i386_cpu_flags): Add cpucldemote.
 471         * i386-opc.tbl: Add cldemote.
 472         * i386-tbl.h: Regenerate.
 473
 474 2018-04-16  Alan Modra  <amodra@gmail.com>
 475
 476         * Makefile.am: Remove sh5 and sh64 support.
 477         * configure.ac: Likewise.
 478         * disassemble.c: Likewise.
 479         * disassemble.h: Likewise.
 480         * sh-dis.c: Likewise.
 481         * sh64-dis.c: Delete.
 482         * sh64-opc.c: Delete.
 483         * sh64-opc.h: Delete.
 484         * Makefile.in: Regenerate.
 485         * configure: Regenerate.
 486         * po/POTFILES.in: Regenerate.
 487
 488 2018-04-16  Alan Modra  <amodra@gmail.com>
 489
 490         * Makefile.am: Remove w65 support.
 491         * configure.ac: Likewise.
 492         * disassemble.c: Likewise.
 493         * disassemble.h: Likewise.
 494         * w65-dis.c: Delete.
 495         * w65-opc.h: Delete.
 496         * Makefile.in: Regenerate.
 497         * configure: Regenerate.
 498         * po/POTFILES.in: Regenerate.
 499
 500 2018-04-16  Alan Modra  <amodra@gmail.com>
 501
 502         * configure.ac: Remove we32k support.
 503         * configure: Regenerate.
 504
 505 2018-04-16  Alan Modra  <amodra@gmail.com>
 506
 507         * Makefile.am: Remove m88k support.
 508         * configure.ac: Likewise.
 509         * disassemble.c: Likewise.
 510         * disassemble.h: Likewise.
 511         * m88k-dis.c: Delete.
 512         * Makefile.in: Regenerate.
 513         * configure: Regenerate.
 514         * po/POTFILES.in: Regenerate.
 515
 516 2018-04-16  Alan Modra  <amodra@gmail.com>
 517
 518         * Makefile.am: Remove i370 support.
 519         * configure.ac: Likewise.
 520         * disassemble.c: Likewise.
 521         * disassemble.h: Likewise.
 522         * i370-dis.c: Delete.
 523         * i370-opc.c: Delete.
 524         * Makefile.in: Regenerate.
 525         * configure: Regenerate.
 526         * po/POTFILES.in: Regenerate.
 527
 528 2018-04-16  Alan Modra  <amodra@gmail.com>
 529
 530         * Makefile.am: Remove h8500 support.
 531         * configure.ac: Likewise.
 532         * disassemble.c: Likewise.
 533         * disassemble.h: Likewise.
 534         * h8500-dis.c: Delete.
 535         * h8500-opc.h: Delete.
 536         * Makefile.in: Regenerate.
 537         * configure: Regenerate.
 538         * po/POTFILES.in: Regenerate.
 539
 540 2018-04-16  Alan Modra  <amodra@gmail.com>
 541
 542         * configure.ac: Remove tahoe support.
 543         * configure: Regenerate.
 544
 545 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 546
 547         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 548         umwait.
 549         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 550         64-bit mode.
 551         * i386-tbl.h: Regenerated.
 552
 553 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 554
 555         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 556         PREFIX_MOD_1_0FAE_REG_6.
 557         (va_mode): New.
 558         (OP_E_register): Use va_mode.
 559         * i386-dis-evex.h (prefix_table):
 560         New instructions (see prefixes above).
 561         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 562         (cpu_flags): Likewise.
 563         * i386-opc.h (enum): Likewise.
 564         (i386_cpu_flags): Likewise.
 565         * i386-opc.tbl: Add umonitor, umwait, tpause.
 566         * i386-init.h: Regenerate.
 567         * i386-tbl.h: Likewise.
 568
 569 2018-04-11  Alan Modra  <amodra@gmail.com>
 570
 571         * opcodes/i860-dis.c: Delete.
 572         * opcodes/i960-dis.c: Delete.
 573         * Makefile.am: Remove i860 and i960 support.
 574         * configure.ac: Likewise.
 575         * disassemble.c: Likewise.
 576         * disassemble.h: Likewise.
 577         * Makefile.in: Regenerate.
 578         * configure: Regenerate.
 579         * po/POTFILES.in: Regenerate.
 580
 581 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         PR binutils/23025
 584         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 585         to 0.
 586         (print_insn): Clear vex instead of vex.evex.
 587
 588 2018-04-04  Nick Clifton  <nickc@redhat.com>
 589
 590         * po/es.po: Updated Spanish translation.
 591
 592 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-gen.c (opcode_modifiers): Delete VecESize.
 595         * i386-opc.h (VecESize): Delete.
 596         (struct i386_opcode_modifier): Delete vecesize.
 597         * i386-opc.tbl: Drop VecESize.
 598         * i386-tlb.h: Re-generate.
 599
 600 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 603         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 604         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 605         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 606         * i386-tlb.h: Re-generate.
 607
 608 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 611         Fold AVX512 forms
 612         * i386-tlb.h: Re-generate.
 613
 614 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 617         (vex_len_table): Drop Y for vcvt*2si.
 618         (putop): Replace plain 'Y' handling by abort().
 619
 620 2018-03-28  Nick Clifton  <nickc@redhat.com>
 621
 622         PR 22988
 623         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 624         instructions with only a base address register.
 625         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 626         handle AARHC64_OPND_SVE_ADDR_R.
 627         (aarch64_print_operand): Likewise.
 628         * aarch64-asm-2.c: Regenerate.
 629         * aarch64_dis-2.c: Regenerate.
 630         * aarch64-opc-2.c: Regenerate.
 631
 632 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-opc.tbl: Drop VecESize from register only insn forms and
 635         memory forms not allowing broadcast.
 636         * i386-tlb.h: Re-generate.
 637
 638 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 641         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 642         sha256*): Drop Disp<N>.
 643
 644 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 645
 646         * i386-dis.c (EbndS, bnd_swap_mode): New.
 647         (prefix_table): Use EbndS.
 648         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 649         * i386-opc.tbl (bndmov): Move misplaced Load.
 650         * i386-tlb.h: Re-generate.
 651
 652 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 655         templates allowing memory operands and folded ones for register
 656         only flavors.
 657         * i386-tlb.h: Re-generate.
 658
 659 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 662         256-bit templates. Drop redundant leftover Disp<N>.
 663         * i386-tlb.h: Re-generate.
 664
 665 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 666
 667         * riscv-opc.c (riscv_insn_types): New.
 668
 669 2018-03-13  Nick Clifton  <nickc@redhat.com>
 670
 671         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 672
 673 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 674
 675         * i386-opc.tbl: Add Optimize to clr.
 676         * i386-tbl.h: Regenerated.
 677
 678 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 679
 680         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 681         * i386-opc.h (OldGcc): Removed.
 682         (i386_opcode_modifier): Remove oldgcc.
 683         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 684         instructions for old (<= 2.8.1) versions of gcc.
 685         * i386-tbl.h: Regenerated.
 686
 687 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-opc.h (EVEXDYN): New.
 690         * i386-opc.tbl: Fold various AVX512VL templates.
 691         * i386-tlb.h: Re-generate.
 692
 693 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 694
 695         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 696         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 697         vpexpandd, vpexpandq): Fold AFX512VF templates.
 698         * i386-tlb.h: Re-generate.
 699
 700 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 703         Fold 128- and 256-bit VEX-encoded templates.
 704         * i386-tlb.h: Re-generate.
 705
 706 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 709         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 710         vpexpandd, vpexpandq): Fold AVX512F templates.
 711         * i386-tlb.h: Re-generate.
 712
 713 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 714
 715         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 716         64-bit templates. Drop Disp<N>.
 717         * i386-tlb.h: Re-generate.
 718
 719 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 720
 721         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 722         and 256-bit templates.
 723         * i386-tlb.h: Re-generate.
 724
 725 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 728         * i386-tlb.h: Re-generate.
 729
 730 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 733         Drop NoAVX.
 734         * i386-tlb.h: Re-generate.
 735
 736 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 739         * i386-tlb.h: Re-generate.
 740
 741 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-gen.c (opcode_modifiers): Delete FloatD.
 744         * i386-opc.h (FloatD): Delete.
 745         (struct i386_opcode_modifier): Delete floatd.
 746         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 747         FloatD by D.
 748         * i386-tlb.h: Re-generate.
 749
 750 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 751
 752         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 753
 754 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 757         * i386-tlb.h: Re-generate.
 758
 759 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 760
 761         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 762         forms.
 763         * i386-tlb.h: Re-generate.
 764
 765 2018-03-07  Alan Modra  <amodra@gmail.com>
 766
 767         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 768         bfd_arch_rs6000.
 769         * disassemble.h (print_insn_rs6000): Delete.
 770         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 771         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 772         (print_insn_rs6000): Delete.
 773
 774 2018-03-03  Alan Modra  <amodra@gmail.com>
 775
 776         * sysdep.h (opcodes_error_handler): Define.
 777         (_bfd_error_handler): Declare.
 778         * Makefile.am: Remove stray #.
 779         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 780         EDIT" comment.
 781         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 782         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 783         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 784         opcodes_error_handler to print errors.  Standardize error messages.
 785         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 786         and include opintl.h.
 787         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 788         * i386-gen.c: Standardize error messages.
 789         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 790         * Makefile.in: Regenerate.
 791         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 792         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 793         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 794         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 795         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 796         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 797         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 798         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 799         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 800         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 801         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 802         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 803         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 804
 805 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 806
 807         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 808         vpsub[bwdq] instructions.
 809         * i386-tbl.h: Regenerated.
 810
 811 2018-03-01  Alan Modra  <amodra@gmail.com>
 812
 813         * configure.ac (ALL_LINGUAS): Sort.
 814         * configure: Regenerate.
 815
 816 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 817
 818         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 819         macro by assignements.
 820
 821 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 822
 823         PR gas/22871
 824         * i386-gen.c (opcode_modifiers): Add Optimize.
 825         * i386-opc.h (Optimize): New enum.
 826         (i386_opcode_modifier): Add optimize.
 827         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 828         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 829         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 830         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 831         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 832         vpxord and vpxorq.
 833         * i386-tbl.h: Regenerated.
 834
 835 2018-02-26  Alan Modra  <amodra@gmail.com>
 836
 837         * crx-dis.c (getregliststring): Allocate a large enough buffer
 838         to silence false positive gcc8 warning.
 839
 840 2018-02-22  Shea Levy <shea@shealevy.com>
 841
 842         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 843
 844 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 845
 846         * i386-opc.tbl: Add {rex},
 847         * i386-tbl.h: Regenerated.
 848
 849 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 850
 851         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 852         (mips16_opcodes): Replace `M' with `m' for "restore".
 853
 854 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 855
 856         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 857
 858 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 859
 860         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 861         variable to `function_index'.
 862
 863 2018-02-13  Nick Clifton  <nickc@redhat.com>
 864
 865         PR 22823
 866         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 867         about truncation of printing.
 868
 869 2018-02-12  Henry Wong <henry@stuffedcow.net>
 870
 871         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 872
 873 2018-02-05  Nick Clifton  <nickc@redhat.com>
 874
 875         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 876
 877 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 878
 879         * i386-dis.c (enum): Add pconfig.
 880         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 881         (cpu_flags): Add CpuPCONFIG.
 882         * i386-opc.h (enum): Add CpuPCONFIG.
 883         (i386_cpu_flags): Add cpupconfig.
 884         * i386-opc.tbl: Add PCONFIG instruction.
 885         * i386-init.h: Regenerate.
 886         * i386-tbl.h: Likewise.
 887
 888 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 889
 890         * i386-dis.c (enum): Add PREFIX_0F09.
 891         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 892         (cpu_flags): Add CpuWBNOINVD.
 893         * i386-opc.h (enum): Add CpuWBNOINVD.
 894         (i386_cpu_flags): Add cpuwbnoinvd.
 895         * i386-opc.tbl: Add WBNOINVD instruction.
 896         * i386-init.h: Regenerate.
 897         * i386-tbl.h: Likewise.
 898
 899 2018-01-17  Jim Wilson  <jimw@sifive.com>
 900
 901         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 902
 903 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 904
 905         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 906         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 907         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 908         (cpu_flags): Add CpuIBT, CpuSHSTK.
 909         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 910         (i386_cpu_flags): Add cpuibt, cpushstk.
 911         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 912         * i386-init.h: Regenerate.
 913         * i386-tbl.h: Likewise.
 914
 915 2018-01-16  Nick Clifton  <nickc@redhat.com>
 916
 917         * po/pt_BR.po: Updated Brazilian Portugese translation.
 918         * po/de.po: Updated German translation.
 919
 920 2018-01-15  Jim Wilson  <jimw@sifive.com>
 921
 922         * riscv-opc.c (match_c_nop): New.
 923         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 924
 925 2018-01-15  Nick Clifton  <nickc@redhat.com>
 926
 927         * po/uk.po: Updated Ukranian translation.
 928
 929 2018-01-13  Nick Clifton  <nickc@redhat.com>
 930
 931         * po/opcodes.pot: Regenerated.
 932
 933 2018-01-13  Nick Clifton  <nickc@redhat.com>
 934
 935         * configure: Regenerate.
 936
 937 2018-01-13  Nick Clifton  <nickc@redhat.com>
 938
 939         2.30 branch created.
 940
 941 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 942
 943         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 944         * i386-tbl.h: Regenerate.
 945
 946 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 949         * i386-tbl.h: Re-generate.
 950
 951 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 952
 953         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 954         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 955         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 956         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 957         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 958         Disp8MemShift of AVX512VL forms.
 959         * i386-tbl.h: Re-generate.
 960
 961 2018-01-09  Jim Wilson  <jimw@sifive.com>
 962
 963         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 964         then the hi_addr value is zero.
 965
 966 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 967
 968         * arm-dis.c (arm_opcodes): Add csdb.
 969         (thumb32_opcodes): Add csdb.
 970
 971 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 972
 973         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 974         * aarch64-asm-2.c: Regenerate.
 975         * aarch64-dis-2.c: Regenerate.
 976         * aarch64-opc-2.c: Regenerate.
 977
 978 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 979
 980         PR gas/22681
 981         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 982         Remove AVX512 vmovd with 64-bit operands.
 983         * i386-tbl.h: Regenerated.
 984
 985 2018-01-05  Jim Wilson  <jimw@sifive.com>
 986
 987         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 988         jalr.
 989
 990 2018-01-03  Alan Modra  <amodra@gmail.com>
 991
 992         Update year range in copyright notice of all files.
 993
 994 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 997         and OPERAND_TYPE_REGZMM entries.
 998
 999 For older changes see ChangeLog-2017
1000 \f
1001 Copyright (C) 2018 Free Software Foundation, Inc.
1002
1003 Copying and distribution of this file, with or without modification,
1004 are permitted in any medium without royalty provided the copyright
1005 notice and this notice are preserved.
1006
1007 Local Variables:
1008 mode: change-log
1009 left-margin: 8
1010 fill-column: 74
1011 version-control: never
1012 End: