opcodes/ChangeLog

   1 2024-02-15 Will Hawkins  <hawkinsw@obs.cr>
   2
   3         * bpf-opc.c: Move callx into the v1 BPF CPU variant.
   4
   5 2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>
   6
   7         * arc-tbl.h (dbnz): Use "DBNZ" class.
   8         * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class.
   9
  10 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
  11
  12         * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and
  13         BPF_INSN_LDABSDW instructions.
  14
  15 2024-01-15  Nick Clifton  <nickc@redhat.com>
  16
  17         * configure: Regenerate.
  18         * po/opcodes.pot: Regenerate.
  19
  20 2024-01-15  Nick Clifton  <nickc@redhat.com>
  21
  22         * 2.42 branch point.
  23
  24 2023-11-15  Arsen Arsenović  <arsen@aarsen.me>
  25
  26         * aclocal.m4: Regenerate.
  27         * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
  28         temporary file to suppress xgettext checking charset names.
  29         * configure.ac (SHARED_LIBADD): Use LTLIBINTL rather than
  30         LIBINTL.
  31         * configure: Regenerate.
  32         * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
  33         temporary file, to suppress xgettext checking charset names.
  34
  35 2023-10-05  Neal frager  <neal.frager@amd.com>
  36
  37         * microblaze-opcm.h (struct op_code_struct): Tidy and remove
  38         redundant entries.
  39         * microblaze-opc.h (MAX_OPCODES): Increase to 300.
  40         (op_code_struct): Add address extension instructions.
  41
  42 2023-10-04  Neal frager  <neal.frager@amd.com>
  43
  44         * microblaze-opc.h (struct op_code_struct): Add hiberante
  45         and suspend entries.
  46         * microblaze-opcm.h (enum microblaze_instr): Add microblaze_sleep,
  47         hibernate, suspend entries.
  48
  49 2023-08-24  Tom Tromey  <tom@tromey.com>
  50
  51         * cgen.sh: Don't pass "-s" to cgen.
  52         * Makefile.in: Rebuild.
  53         * Makefile.am (GUILE): Simplify.
  54
  55 2023-07-31  Jose E. Marchesi  <jose.marchesi@oracle.com>
  56
  57         PR 30705
  58         * bpf-dis.c (print_insn_bpf): Check that info->section->owner is
  59         actually available before using it.
  60
  61 2023-07-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
  62
  63         * bpf-dis.c: Initialize asm_bpf_version to -1.
  64         (print_insn_bpf): Set BPF ISA version from the cpu version ELF
  65         header flags if no explicit version set in the command line.
  66         * disassemble.c (disassemble_init_for_target): Remove unused code.
  67
  68 2023-07-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  69
  70         * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
  71         register.
  72
  73 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
  74
  75         * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
  76         instructions.
  77
  78 2023-07-24  Jose E. Marchesi  <jose.marchesi@oracle.com>
  79
  80         * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
  81         instructions.
  82
  83 2023-07-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
  84
  85         * bpf-opc.c (bpf_opcodes): Add entry for jal.
  86
  87 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  88
  89         * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
  90         instructions.
  91
  92 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  93
  94         * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
  95         MOVS32{8,16,32}R instructions.  and MOVS32I instructions.
  96
  97 2023-07-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
  98
  99         * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
 100         * Makefile.in: Regenerate.
 101
 102 2023-07-03  Nick Clifton  <nickc@redhat.com>
 103
 104         * configure: Regenerate.
 105         * po/opcodes.pot: Regenerate.
 106
 107 2023-07-03  Nick Clifton  <nickc@redhat.com>
 108
 109         2.41 Branch Point.
 110
 111 2023-05-23  Nick Clifton  <nickc@redhat.com>
 112
 113         * po/sv.po: Updated translation.
 114
 115 2023-04-21  Tom Tromey  <tromey@adacore.com>
 116
 117         * i386-dis.c (OP_J): Check result of get16.
 118
 119 2023-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 120
 121         * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
 122         vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
 123         vsubs2h, and vsubs4h instructions.
 124
 125 2023-04-11  Nick Clifton  <nickc@redhat.com>
 126
 127         PR 30310
 128         * nfp-dis.c (init_nfp6000_priv): Check that the output section
 129         exists.
 130
 131 2023-03-15  Nick Clifton  <nickc@redhat.com>
 132
 133         PR 30231
 134         * mep-dis.c: Regenerate.
 135
 136 2023-03-15  Nick Clifton  <nickc@redhat.com>
 137
 138         PR 30230
 139         * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
 140
 141 2023-02-28  Richard Ball  <richard.ball@arm.com>
 142
 143         * aarch64-opc.c: Add MEC system registers.
 144
 145 2023-01-03  Nick Clifton  <nickc@redhat.com>
 146
 147         * po/de.po: Updated German translation.
 148         * po/ro.po: Updated Romainian translation.
 149         * po/uk.po: Updated Ukrainian translation.
 150
 151 2022-12-31  Nick Clifton  <nickc@redhat.com>
 152
 153         * 2.40 branch created.
 154
 155 2022-11-22  Shahab Vahedi  <shahab@synopsys.com>
 156
 157         * arc-regs.h: Change isa_config address to 0xc1.
 158         isa_config exists for ARC700 and ARCV2 and not ARCALL.
 159
 160 2022-10-31  Yoshinori Sato  <ysato@users.sourceforge.jp>
 161
 162         * rx-decode.opc: Switch arguments of the MVTACGU insn.
 163         * rx-decode.c: Regenerate.
 164
 165 2022-09-22  Yoshinori Sato  <ysato@users.sourceforge.jp>
 166
 167         * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
 168         Rm_BANK,Rn is always 1.
 169
 170 2022-07-21  Peter Bergner  <bergner@linux.ibm.com>
 171
 172         * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
 173         (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
 174         xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
 175         xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
 176         xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
 177         xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
 178         xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
 179
 180 2022-07-18  Claudiu Zissulescu  <claziss@synopsys.com>
 181
 182         * disassemble.c (disassemble_init_for_target): Set
 183         created_styled_output for ARC based targets.
 184         * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
 185         instead of fprintf_ftype throughout.
 186         (find_format): Likewise.
 187         (print_flags): Likewise.
 188         (print_insn_arc): Likewise.
 189
 190 2022-07-08  Nick Clifton  <nickc@redhat.com>
 191
 192         * 2.39 branch created.
 193
 194 2022-07-04  Marcus Nilsson  <brainbomb@gmail.com>
 195
 196         * disassemble.c: (disassemble_init_for_target): Set
 197         created_styled_output for AVR based targets.
 198         * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
 199         instead of fprintf_ftype throughout.
 200         (avr_operand): Pass in and fill disassembler_style when
 201         parsing operands.
 202
 203 2022-04-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 204
 205         * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
 206         table.
 207
 208 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
 209
 210         * configure.ac: Handle bfd_amdgcn_arch.
 211         * configure: Re-generate.
 212
 213 2022-03-06  Sagar Patel  <sagarmp@cs.unc.edu>
 214             Maciej W. Rozycki  <macro@orcam.me.uk>
 215
 216         * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
 217         for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
 218         * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
 219         "bnez" instructions.
 220
 221 2022-02-17  Nick Clifton  <nickc@redhat.com>
 222
 223         * po/sr.po: Updated Serbian translation.
 224
 225 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
 226
 227         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
 228         * microblaze-opc.h: Follow 'fsqrt' rename.
 229
 230 2022-01-24  Nick Clifton  <nickc@redhat.com>
 231
 232         * po/ro.po: Updated Romanian translation.
 233         * po/uk.po: Updated Ukranian translation.
 234
 235 2022-01-22  Nick Clifton  <nickc@redhat.com>
 236
 237         * configure: Regenerate.
 238         * po/opcodes.pot: Regenerate.
 239
 240 2022-01-22  Nick Clifton  <nickc@redhat.com>
 241
 242         * 2.38 release branch created.
 243
 244 2022-01-17  Nick Clifton  <nickc@redhat.com>
 245
 246         * Makefile.in: Regenerate.
 247         * po/opcodes.pot: Regenerate.
 248
 249 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
 250
 251         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
 252         in insn_type on branching instructions.
 253
 254 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
 255             Simon Cook  <simon.cook@embecosm.com>
 256
 257         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
 258         (riscv_options): New static global.
 259         (disassembler_options_riscv): New function.
 260         (print_riscv_disassembler_options): Rewrite to use
 261         disassembler_options_riscv.
 262
 263 2021-11-25  Nick Clifton  <nickc@redhat.com>
 264
 265         PR 28614
 266         * aarch64-asm.c: Replace assert(0) with real code.
 267         * aarch64-dis.c: Likewise.
 268         * aarch64-opc.c: Likewise.
 269
 270 2021-11-25  Nick Clifton  <nickc@redhat.com>
 271
 272         * po/fr.po; Updated French translation.
 273
 274 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
 275
 276         * Makefile.am: Remove obsolete comment.
 277         * configure.ac: Refer `libbfd.la' to link shared BFD library
 278         except for Cygwin.
 279         * Makefile.in: Regenerate.
 280         * configure: Regenerate.
 281
 282 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
 283
 284         * configure: Regenerate.
 285
 286 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
 287
 288         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
 289         on POWER5 and later.
 290
 291 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
 292
 293         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
 294         before an unknown instruction, '%d' is replaced with the
 295         instruction length.
 296
 297 2021-09-02  Nick Clifton  <nickc@redhat.com>
 298
 299         PR 28292
 300         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
 301         of BFD_RELOC_16.
 302
 303 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
 304
 305         * arc-regs.h (DEF): Fix the register numbers.
 306
 307 2021-08-10  Nick Clifton  <nickc@redhat.com>
 308
 309         * po/sr.po: Updated Serbian translation.
 310
 311 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
 312
 313         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
 314
 315 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
 316
 317         * s390-opc.txt: Add qpaci.
 318
 319 2021-07-03  Nick Clifton  <nickc@redhat.com>
 320
 321         * configure: Regenerate.
 322         * po/opcodes.pot: Regenerate.
 323
 324 2021-07-03  Nick Clifton  <nickc@redhat.com>
 325
 326         * 2.37 release branch created.
 327
 328 2021-07-02  Alan Modra  <amodra@gmail.com>
 329
 330         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 331         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 332         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 333         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 334         (nds32_keyword_gpr): Move declarations to..
 335         * nds32-asm.h: ..here, constifying to match definitions.
 336
 337 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 338
 339         * Makefile.am (GUILE): New variable.
 340         (CGEN): Use $(GUILE).
 341         * Makefile.in: Regenerate.
 342
 343 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 344
 345         * mep-asm.c (macros): Mark static & const.
 346         (lookup_macro): Change return & m to const.
 347         (expand_macro): Change mac to const.
 348         (expand_string): Change pmacro to const.
 349
 350 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 351
 352         * nds32-asm.c (operand_fields): Rename to ...
 353         (nds32_operand_fields): ... this.
 354         (keyword_gpr): Rename to ...
 355         (nds32_keyword_gpr): ... this.
 356         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 357         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 358         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 359         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 360         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 361         Mark static.
 362         (keywords): Rename to ...
 363         (nds32_keywords): ... this.
 364         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 365         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 366
 367 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 368
 369         * z80-dis.c (opc_ed): Make const.
 370         (pref_ed): Make p const.
 371
 372 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 373
 374         * microblaze-dis.c (get_field_special): Make op const.
 375         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 376         microblaze_opcodes.
 377         (print_insn_microblaze): Make op & pop const.
 378         (get_insn_microblaze): Make op const.  Rename opcodes to
 379         microblaze_opcodes.
 380         (microblaze_get_target_address): Likewise.
 381         * microblaze-opc.h (struct op_code_struct): Make const.
 382         Rename opcodes to microblaze_opcodes.
 383
 384 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 385
 386         * aarch64-gen.c (aarch64_opcode_table): Add const.
 387         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 388
 389 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 390
 391         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 392         available.
 393
 394 2021-06-22  Alan Modra  <amodra@gmail.com>
 395
 396         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 397         print separator for pcrel insns.
 398
 399 2021-06-19  Alan Modra  <amodra@gmail.com>
 400
 401         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 402
 403 2021-06-19  Alan Modra  <amodra@gmail.com>
 404
 405         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 406         entire buffer.
 407
 408 2021-06-17  Alan Modra  <amodra@gmail.com>
 409
 410         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 411         in table.
 412
 413 2021-06-03  Alan Modra  <amodra@gmail.com>
 414
 415         PR 1202
 416         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 417         Use unsigned int for inst.
 418
 419 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 420
 421         * arc-dis.c (arc_option_arg_t): New enumeration.
 422         (arc_options): New variable.
 423         (disassembler_options_arc): New function.
 424         (print_arc_disassembler_options): Reimplement in terms of
 425         "disassembler_options_arc".
 426
 427 2021-05-29  Alan Modra  <amodra@gmail.com>
 428
 429         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 430         Don't special case PPC_OPCODE_RAW.
 431         (lookup_prefix): Likewise.
 432         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 433         (print_insn_powerpc): ..update caller.
 434         * ppc-opc.c (EXT): Define.
 435         (powerpc_opcodes): Mark extended mnemonics with EXT.
 436         (prefix_opcodes, vle_opcodes): Likewise.
 437         (XISEL, XISEL_MASK): Add cr field and simplify.
 438         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 439         all isel variants to where the base mnemonic belongs.  Sort dstt,
 440         dststt and dssall.
 441
 442 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 443
 444         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 445         COP3 opcode instructions.
 446
 447 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 448
 449         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 450         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 451         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 452         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 453         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 454         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 455         "cop2", and "cop3" entries.
 456
 457 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 458
 459         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 460         entries and associated comments.
 461
 462 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 463
 464         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 465         of "c0".
 466
 467 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 468
 469         * mips-dis.c (mips_cp1_names_mips): New variable.
 470         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 471         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 472         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 473         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 474         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 475         "loongson2f".
 476
 477 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 478
 479         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 480         handling code over to...
 481         <OP_REG_CONTROL>: ... this new case.
 482         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 483         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 484         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 485         replacing the `G' operand code with `g'.  Update "cftc1" and
 486         "cftc2" entries replacing the `E' operand code with `y'.
 487         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 488         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 489         entries replacing the `G' operand code with `g'.
 490
 491 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 492
 493         * mips-dis.c (mips_cp0_names_r3900): New variable.
 494         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 495         for "r3900".
 496
 497 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 498
 499         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 500         and "mtthc2" to using the `G' rather than `g' operand code for
 501         the coprocessor control register referred.
 502
 503 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 504
 505         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 506         entries with each other.
 507
 508 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 509
 510         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 511
 512 2021-05-25  Alan Modra  <amodra@gmail.com>
 513
 514         * cris-desc.c: Regenerate.
 515         * cris-desc.h: Regenerate.
 516         * cris-opc.h: Regenerate.
 517         * po/POTFILES.in: Regenerate.
 518
 519 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 520
 521         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 522         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 523         (CGEN_CPUS): Add cris.
 524         (CRIS_DEPS): Define.
 525         (stamp-cris): New rule.
 526         * cgen.sh: Handle desc action.
 527         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 528         * Makefile.in, configure: Regenerate.
 529
 530 2021-05-18  Job Noorman  <mtvec@pm.me>
 531
 532         PR 27814
 533         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 534         the elf objects.
 535
 536 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 537
 538         * arm-dis.c (mve_opcodes): Fix disassembly of
 539         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 540         (is_mve_encoding_conflict): MVE vector loads should not match
 541         when P = W = 0.
 542         (is_mve_unpredictable): It's not unpredictable to use the same
 543         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 544
 545 2021-05-11  Nick Clifton  <nickc@redhat.com>
 546
 547         PR 27840
 548         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 549         the end of the code buffer.
 550
 551 2021-05-06  Stafford Horne  <shorne@gmail.com>
 552
 553         PR 21464
 554         * or1k-asm.c: Regenerate.
 555
 556 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 557
 558         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 559         info->insn_info_valid.
 560
 561 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 562
 563         * i386-opc.tbl (lea): Add Optimize.
 564         * opcodes/i386-tbl.h: Re-generate.
 565
 566 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 567
 568         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 569         of l32r fetch and display referenced literal value.
 570
 571 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 572
 573         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 574         to 4 for literal disassembly.
 575
 576 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 577
 578         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 579         for TLBI instruction.
 580
 581 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 582
 583         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 584         DC instruction.
 585
 586 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 587
 588         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 589         "qualifier".
 590         (convert_mov_to_movewide): Add initializer for "value".
 591
 592 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 593
 594         * aarch64-opc.c: Add RME system registers.
 595
 596 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 597
 598         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 599         "addi d,CV,z" to "c.mv d,CV".
 600
 601 2021-04-12  Alan Modra  <amodra@gmail.com>
 602
 603         * configure.ac (--enable-checking): Add support.
 604         * config.in: Regenerate.
 605         * configure: Regenerate.
 606
 607 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 608
 609         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 610         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 611
 612 2021-04-09  Alan Modra  <amodra@gmail.com>
 613
 614         * ppc-dis.c (struct dis_private): Add "special".
 615         (POWERPC_DIALECT): Delete.  Replace uses with..
 616         (private_data): ..this.  New inline function.
 617         (disassemble_init_powerpc): Init "special" names.
 618         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 619         field of prefix instructions.
 620         (bsearch_reloc, print_got_plt): New functions.
 621         (print_insn_powerpc): For pcrel instructions, print target address
 622         and symbol if known, and decode plt and got loads too.
 623
 624 2021-04-08  Alan Modra  <amodra@gmail.com>
 625
 626         PR 27684
 627         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 628
 629 2021-04-08  Alan Modra  <amodra@gmail.com>
 630
 631         PR 27676
 632         * ppc-opc.c (DCBT_EO): Move earlier.
 633         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 634         (powerpc_operands): Add THCT and THDS entries.
 635         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 636
 637 2021-04-06  Alan Modra  <amodra@gmail.com>
 638
 639         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 640         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 641         symbol_at_address_func.
 642
 643 2021-04-05  Alan Modra  <amodra@gmail.com>
 644
 645         * configure.ac: Don't check for limits.h, string.h, strings.h or
 646         stdlib.h.
 647         (AC_ISC_POSIX): Don't invoke.
 648         * sysdep.h: Include stdlib.h and string.h unconditionally.
 649         * i386-opc.h: Include limits.h unconditionally.
 650         * wasm32-dis.c: Likewise.
 651         * cgen-opc.c: Don't include alloca-conf.h.
 652         * config.in: Regenerate.
 653         * configure: Regenerate.
 654
 655 2021-04-01  Martin Liska  <mliska@suse.cz>
 656
 657         * arm-dis.c (strneq): Remove strneq and use startswith.
 658         * cr16-dis.c (print_insn_cr16): Likewise.
 659         * score-dis.c (streq): Likewise.
 660         (strneq): Likewise.
 661         * score7-dis.c (strneq): Likewise.
 662
 663 2021-04-01  Alan Modra  <amodra@gmail.com>
 664
 665         PR 27675
 666         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 667
 668 2021-03-31  Alan Modra  <amodra@gmail.com>
 669
 670         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 671         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 672         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 673         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 674         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 675         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 676         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 677         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 678         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 679         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 680         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 681         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 682         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 683         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 684         and TRUE with true throughout.
 685
 686 2021-03-31  Alan Modra  <amodra@gmail.com>
 687
 688         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 689         * aarch64-dis.h: Likewise.
 690         * aarch64-opc.c: Likewise.
 691         * avr-dis.c: Likewise.
 692         * csky-dis.c: Likewise.
 693         * nds32-asm.c: Likewise.
 694         * nds32-dis.c: Likewise.
 695         * nfp-dis.c: Likewise.
 696         * riscv-dis.c: Likewise.
 697         * s12z-dis.c: Likewise.
 698         * wasm32-dis.c: Likewise.
 699
 700 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 703         (i386_seg_prefixes): New.
 704         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 705         (i386_seg_prefixes): Declare.
 706
 707 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 708
 709         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 710
 711 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 714         * i386-reg.tbl (st): Move down.
 715         (st(0)): Delete. Extend comment.
 716         * i386-tbl.h: Re-generate.
 717
 718 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 719
 720         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 721         (cmpsd): Move next to cmps.
 722         (movsd): Move next to movs.
 723         (cmpxchg16b): Move to separate section.
 724         (fisttp, fisttpll): Likewise.
 725         (monitor, mwait): Likewise.
 726         * i386-tbl.h: Re-generate.
 727
 728 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 729
 730         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 731         (vpsadbw): Add C.
 732         * i386-tbl.h: Re-generate.
 733
 734 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 735
 736         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 737         pclmul, gfni): New templates. Use them wherever possible. Move
 738         SSE4.1 pextrw into respective section.
 739         * i386-tbl.h: Re-generate.
 740
 741 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 744         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 745         "length".
 746         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 747         Convert all of their uses to representation in opcode.
 748
 749 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 750
 751         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 752         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 753         value of None. Shrink operands to 3 bits.
 754
 755 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 756
 757         * i386-gen.c (process_i386_opcode_modifier): New parameter
 758         "space".
 759         (output_i386_opcode): New local variable "space". Adjust
 760         process_i386_opcode_modifier() invocation.
 761         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 762         invocation.
 763         * i386-tbl.h: Re-generate.
 764
 765 2021-03-29  Alan Modra  <amodra@gmail.com>
 766
 767         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 768         (fp_qualifier_p, get_data_pattern): Likewise.
 769         (aarch64_get_operand_modifier_from_value): Likewise.
 770         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 771         (operand_variant_qualifier_p): Likewise.
 772         (qualifier_value_in_range_constraint_p): Likewise.
 773         (aarch64_get_qualifier_esize): Likewise.
 774         (aarch64_get_qualifier_nelem): Likewise.
 775         (aarch64_get_qualifier_standard_value): Likewise.
 776         (get_lower_bound, get_upper_bound): Likewise.
 777         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 778         (aarch64_print_operand): Likewise.
 779         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 780         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 781         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 782         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 783         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 784         (print_insn_tic6x): Likewise.
 785
 786 2021-03-29  Alan Modra  <amodra@gmail.com>
 787
 788         * arc-dis.c (extract_operand_value): Correct NULL cast.
 789         * frv-opc.h: Regenerate.
 790
 791 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 792
 793         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 794         MMX form.
 795         * i386-tbl.h: Re-generate.
 796
 797 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 798
 799         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 800         immediate in br.n instruction.
 801
 802 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-dis.c (XMGatherD, VexGatherD): New.
 805         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 806         (print_insn): Check masking for S/G insns.
 807         (OP_E_memory): New local variable check_gather. Extend mandatory
 808         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 809         Extend check for disallowed 16-bit addressing.
 810         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 811         if()s to switch(). Check register conflicts for (VEX-encoded)
 812         gathers. Drop no longer reachable cases.
 813         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 814         vgatherdp*.
 815
 816 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 817
 818         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 819         zeroing-masking without masking.
 820
 821 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 822
 823         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 824         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 825         single-operand forms as deprecated.
 826         * i386-tbl.h: Re-generate.
 827
 828 2021-03-25  Alan Modra  <amodra@gmail.com>
 829
 830         PR 27647
 831         * ppc-opc.c (XLOCB_MASK): Delete.
 832         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 833         XLBH_MASK.
 834         (powerpc_opcodes): Accept a BH field on all extended forms of
 835         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 836
 837 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-gen.c (output_i386_opcode): Drop processing of
 840         opcode_length. Calculate length from base_opcode. Adjust prefix
 841         encoding determination.
 842         (process_i386_opcodes): Drop output of fake opcode_length.
 843         * i386-opc.h (struct insn_template): Drop opcode_length field.
 844         * i386-opc.tbl: Drop opcode length field from all templates.
 845         * i386-tbl.h: Re-generate.
 846
 847 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 848
 849         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 850         parameter "prefix". Drop local variable "regular_encoding".
 851         Record prefix setting / check for consistency.
 852         (output_i386_opcode): Parse opcode_length and base_opcode
 853         earlier. Derive prefix encoding. Drop no longer applicable
 854         consistency checking. Adjust process_i386_opcode_modifier()
 855         invocation.
 856         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 857         invocation.
 858         * i386-tbl.h: Re-generate.
 859
 860 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 861
 862         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 863         check.
 864         * i386-opc.h (Prefix_*): Move #define-s.
 865         * i386-opc.tbl: Move pseudo prefix enumerator values to
 866         extension opcode field. Introduce pseudopfx template.
 867         * i386-tbl.h: Re-generate.
 868
 869 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 870
 871         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 872         comment.
 873         * i386-tbl.h: Re-generate.
 874
 875 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 876
 877         * i386-opc.h (struct insn_template): Move cpu_flags field past
 878         opcode_modifier one.
 879         * i386-tbl.h: Re-generate.
 880
 881 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 884         * i386-opc.h (OpcodeSpace): New enumerator.
 885         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 886         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 887         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 888         (struct i386_opcode_modifier): New field opcodespace. Shrink
 889         opcodeprefix field.
 890         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 891         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 892         OpcodePrefix uses.
 893         * i386-tbl.h: Re-generate.
 894
 895 2021-03-22  Martin Liska  <mliska@suse.cz>
 896
 897         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 898         * arc-dis.c (parse_option): Likewise.
 899         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 900         * cris-dis.c (print_with_operands): Likewise.
 901         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 902         * i386-dis.c (print_insn): Likewise.
 903         * ia64-gen.c (fetch_insn_class): Likewise.
 904         (parse_resource_users): Likewise.
 905         (in_iclass): Likewise.
 906         (lookup_specifier): Likewise.
 907         (insert_opcode_dependencies): Likewise.
 908         * mips-dis.c (parse_mips_ase_option): Likewise.
 909         (parse_mips_dis_option): Likewise.
 910         * s390-dis.c (disassemble_init_s390): Likewise.
 911         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 912
 913 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 914
 915         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 916
 917 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 918
 919         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 920         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 921
 922 2021-03-12  Alan Modra  <amodra@gmail.com>
 923
 924         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 925
 926 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 927
 928         * i386-dis.c (OP_XMM): Re-order checks.
 929
 930 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-dis.c (putop): Drop need_vex check when also checking
 933         vex.evex.
 934         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 935         checking vex.b.
 936
 937 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 938
 939         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 940         checks. Move case label past broadcast check.
 941
 942 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 943
 944         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 945         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 946         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 947         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 948         EVEX_W_0F38C7_M_0_L_2): Delete.
 949         (REG_EVEX_0F38C7_M_0_L_2): New.
 950         (intel_operand_size): Handle VEX and EVEX the same for
 951         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 952         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 953         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 954         vex_vsib_q_w_d_mode uses.
 955         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 956         0F38A1, and 0F38A3 entries.
 957         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 958         entry.
 959         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 960         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 961         0F38A3 entries.
 962
 963 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 964
 965         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 966         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 967         MOD_VEX_0FXOP_09_12): Rename to ...
 968         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 969         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 970         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 971         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 972         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 973         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 974         (reg_table): Adjust comments.
 975         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 976         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 977         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 978         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 979         (vex_len_table): Adjust opcode 0A_12 entry.
 980         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 981         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 982         (rm_table): Move hreset entry.
 983
 984 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 985
 986         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 987         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 988         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 989         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 990         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 991         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 992         (get_valid_dis386): Also handle 512-bit vector length when
 993         vectoring into vex_len_table[].
 994         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 995         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 996         entries.
 997         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 998         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 999         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
1000         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
1001         entries.
1002
1003 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1004
1005         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
1006         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
1007         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
1008         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
1009         entries.
1010         * i386-dis-evex-len.h (evex_len_table): Likewise.
1011         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
1012
1013 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1014
1015         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
1016         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
1017         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
1018         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
1019         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
1020         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
1021         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
1022         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
1023         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1024         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1025         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1026         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
1027         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
1028         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
1029         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
1030         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
1031         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
1032         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
1033         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
1034         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1035         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
1036         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
1037         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1038         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
1039         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1040         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
1041         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
1042         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
1043         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
1044         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
1045         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
1046         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
1047         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
1048         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
1049         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
1050         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
1051         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
1052         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
1053         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
1054         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
1055         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
1056         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
1057         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
1058         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
1059         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
1060         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
1061         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
1062         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
1063         EVEX_W_0F3A43_L_n): New.
1064         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
1065         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
1066         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
1067         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
1068         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
1069         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
1070         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
1071         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
1072         0F385B, 0F38C6, and 0F38C7 entries.
1073         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
1074         0F38C6 and 0F38C7.
1075         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
1076         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
1077         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
1078         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
1079
1080 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1081
1082         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
1083         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
1084         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
1085         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
1086         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
1087         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
1088         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
1089         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
1090         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1091         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1092         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1093         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1094         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1095         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1096         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1097         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1098         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1099         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1100         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1101         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1102         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1103         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1104         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1105         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1106         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1107         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1108         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1109         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1110         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1111         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1112         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1113         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1114         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1115         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1116         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1117         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1118         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1119         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1120         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1121         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1122         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1123         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1124         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1125         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1126         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1127         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1128         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1129         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1130         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1131         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1132         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1133         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1134         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1135         VEX_W_0F99_P_2_LEN_0): Delete.
1136         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1137         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1138         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1139         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1140         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1141         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1142         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1143         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1144         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1145         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1146         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1147         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1148         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1149         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1150         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1151         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1152         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1153         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1154         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1155         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1156         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1157         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1158         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1159         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1160         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1161         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1162         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1163         (prefix_table): No longer link to vex_len_table[] for opcodes
1164         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1165         0F92, 0F93, 0F98, and 0F99.
1166         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1167         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1168         0F98, and 0F99.
1169         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1170         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1171         0F98, and 0F99.
1172         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1173         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1174         0F98, and 0F99.
1175         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1176         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1177         0F98, and 0F99.
1178
1179 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1180
1181         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1182         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1183         REG_VEX_0F73_M_0 respectively.
1184         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1185         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1186         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1187         MOD_VEX_0F73_REG_7): Delete.
1188         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1189         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1190         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1191         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1192         PREFIX_VEX_0F3AF0_L_0 respectively.
1193         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1194         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1195         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1196         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1197         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1198         VEX_LEN_0F38F7): New.
1199         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1200         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1201         0F72, and 0F73. No longer link to vex_len_table[] for opcode
1202         0F38F3.
1203         (prefix_table): No longer link to vex_len_table[] for opcodes
1204         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1205         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1206         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1207         0F38F6, 0F38F7, and 0F3AF0.
1208         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1209         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1210         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1211         0F73.
1212
1213 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1214
1215         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1216         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1217         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1218         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1219         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1220         (MOD_0F71, MOD_0F72, MOD_0F73): New.
1221         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1222         73.
1223         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1224         0F72, and 0F73.
1225         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1226         0F73.
1227
1228 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1229
1230         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1231         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1232         (reg_table): Don't link to mod_table[] where not needed. Add
1233         PREFIX_IGNORED to nop entries.
1234         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1235         (mod_table): Add nop entries next to prefetch ones. Drop
1236         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1237         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1238         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1239         PREFIX_OPCODE from endbr* entries.
1240         (get_valid_dis386): Also consider entry's name when zapping
1241         vindex.
1242         (print_insn): Handle PREFIX_IGNORED.
1243
1244 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1245
1246         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1247         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1248         element.
1249         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1250         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1251         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1252         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1253         (struct i386_opcode_modifier): Delete notrackprefixok,
1254         islockable, hleprefixok, and repprefixok fields. Add prefixok
1255         field.
1256         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1257         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1258         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1259         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1260         Replace HLEPrefixOk.
1261         * opcodes/i386-tbl.h: Re-generate.
1262
1263 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1264
1265         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1266         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1267         64-bit form.
1268         * opcodes/i386-tbl.h: Re-generate.
1269
1270 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1271
1272         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1273         for {} instead of {0}. Don't look for '0'.
1274         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1275         size specifiers.
1276
1277 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1278
1279         PR 27158
1280         * riscv-dis.c (print_insn_args): Updated encoding macros.
1281         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1282         (match_c_addi16sp): Updated encoding macros.
1283         (match_c_lui): Likewise.
1284         (match_c_lui_with_hint): Likewise.
1285         (match_c_addi4spn): Likewise.
1286         (match_c_slli): Likewise.
1287         (match_slli_as_c_slli): Likewise.
1288         (match_c_slli64): Likewise.
1289         (match_srxi_as_c_srxi): Likewise.
1290         (riscv_insn_types): Added .insn css/cl/cs.
1291
1292 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1293
1294         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1295         (default_priv_spec): Updated type to riscv_spec_class.
1296         (parse_riscv_dis_option): Updated.
1297         * riscv-opc.c: Moved stuff and make the file tidy.
1298
1299 2021-02-17  Alan Modra  <amodra@gmail.com>
1300
1301         * wasm32-dis.c: Include limits.h.
1302         (CHAR_BIT): Provide backup define.
1303         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1304         Correct signed overflow checking.
1305
1306 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1307
1308         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1309         * i386-tbl.h: Re-generate.
1310
1311 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1312
1313         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1314         Oword.
1315         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1316
1317 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1318
1319         * s390-mkopc.c (main): Accept arch14 as cpu string.
1320         * s390-opc.txt: Add new arch14 instructions.
1321
1322 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1323
1324         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1325         favour of LIBINTL.
1326         * configure: Regenerated.
1327
1328 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1329
1330         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1331         * tic54x-opc.c (regs): Rename to ...
1332         (tic54x_regs): ... this.
1333         (mmregs): Rename to ...
1334         (tic54x_mmregs): ... this.
1335         (condition_codes): Rename to ...
1336         (tic54x_condition_codes): ... this.
1337         (cc2_codes): Rename to ...
1338         (tic54x_cc2_codes): ... this.
1339         (cc3_codes): Rename to ...
1340         (tic54x_cc3_codes): ... this.
1341         (status_bits): Rename to ...
1342         (tic54x_status_bits): ... this.
1343         (misc_symbols): Rename to ...
1344         (tic54x_misc_symbols): ... this.
1345
1346 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1347
1348         * riscv-opc.c (MASK_RVB_IMM): Removed.
1349         (riscv_opcodes): Removed zb* instructions.
1350         (riscv_ext_version_table): Removed versions for zb*.
1351
1352 2021-01-26  Alan Modra  <amodra@gmail.com>
1353
1354         * i386-gen.c (parse_template): Ensure entire template_instance
1355         is initialised.
1356
1357 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1358
1359         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1360         (riscv_fpr_names_abi): Likewise.
1361         (riscv_opcodes): Likewise.
1362         (riscv_insn_types): Likewise.
1363
1364 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1365
1366         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1367
1368 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1369
1370         * riscv-dis.c: Comments tidy and improvement.
1371         * riscv-opc.c: Likewise.
1372
1373 2021-01-13  Alan Modra  <amodra@gmail.com>
1374
1375         * Makefile.in: Regenerate.
1376
1377 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1378
1379         PR binutils/26792
1380         * configure.ac: Use GNU_MAKE_JOBSERVER.
1381         * aclocal.m4: Regenerated.
1382         * configure: Likewise.
1383
1384 2021-01-12  Nick Clifton  <nickc@redhat.com>
1385
1386         * po/sr.po: Updated Serbian translation.
1387
1388 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1389
1390         PR ld/27173
1391         * configure: Regenerated.
1392
1393 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1394
1395         * aarch64-asm-2.c: Regenerate.
1396         * aarch64-dis-2.c: Likewise.
1397         * aarch64-opc-2.c: Likewise.
1398         * aarch64-opc.c (aarch64_print_operand):
1399         Delete handling of AARCH64_OPND_CSRE_CSR.
1400         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1401         (CSRE): Likewise.
1402         (_CSRE_INSN): Likewise.
1403         (aarch64_opcode_table): Delete csr.
1404
1405 2021-01-11  Nick Clifton  <nickc@redhat.com>
1406
1407         * po/de.po: Updated German translation.
1408         * po/fr.po: Updated French translation.
1409         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1410         * po/sv.po: Updated Swedish translation.
1411         * po/uk.po: Updated Ukranian translation.
1412
1413 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1414
1415         * configure: Regenerated.
1416
1417 2021-01-09  Nick Clifton  <nickc@redhat.com>
1418
1419         * configure: Regenerate.
1420         * po/opcodes.pot: Regenerate.
1421
1422 2021-01-09  Nick Clifton  <nickc@redhat.com>
1423
1424         * 2.36 release branch crated.
1425
1426 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1427
1428         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1429         (DW, (XRC_MASK): Define.
1430         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1431
1432 2021-01-09  Alan Modra  <amodra@gmail.com>
1433
1434         * configure: Regenerate.
1435
1436 2021-01-08  Nick Clifton  <nickc@redhat.com>
1437
1438         * po/sv.po: Updated Swedish translation.
1439
1440 2021-01-08  Nick Clifton  <nickc@redhat.com>
1441
1442         PR 27129
1443         * aarch64-dis.c (determine_disassembling_preference): Move call to
1444         aarch64_match_operands_constraint outside of the assertion.
1445         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1446         Replace with a return of FALSE.
1447
1448         PR 27139
1449         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1450         core system register.
1451
1452 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1453
1454         * configure: Regenerate.
1455
1456 2021-01-07  Nick Clifton  <nickc@redhat.com>
1457
1458         * po/fr.po: Updated French translation.
1459
1460 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1461
1462         * m68k-opc.c (chkl): Change minimum architecture requirement to
1463         m68020.
1464
1465 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1466
1467         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1468
1469 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1470             Jim Wilson  <jimw@sifive.com>
1471             Andrew Waterman  <andrew@sifive.com>
1472             Maxim Blinov  <maxim.blinov@embecosm.com>
1473             Kito Cheng  <kito.cheng@sifive.com>
1474             Nelson Chu  <nelson.chu@sifive.com>
1475
1476         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1477         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1478
1479 2021-01-01  Alan Modra  <amodra@gmail.com>
1480
1481         Update year range in copyright notice of all files.
1482
1483 For older changes see ChangeLog-2020
1484 \f
1485 Copyright (C) 2021-2024 Free Software Foundation, Inc.
1486
1487 Copying and distribution of this file, with or without modification,
1488 are permitted in any medium without royalty provided the copyright
1489 notice and this notice are preserved.
1490
1491 Local Variables:
1492 mode: change-log
1493 left-margin: 8
1494 fill-column: 74
1495 version-control: never
1496 End: