opcodes/ChangeLog

   1 2022-02-14  Sergei Trofimovich  <siarheit@google.com>
   2
   3         * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
   4         * microblaze-opc.h: Follow 'fsqrt' rename.
   5
   6 2022-01-24  Nick Clifton  <nickc@redhat.com>
   7
   8         * po/ro.po: Updated Romanian translation.
   9         * po/uk.po: Updated Ukranian translation.
  10
  11 2022-01-22  Nick Clifton  <nickc@redhat.com>
  12
  13         * configure: Regenerate.
  14         * po/opcodes.pot: Regenerate.
  15
  16 2022-01-22  Nick Clifton  <nickc@redhat.com>
  17
  18         * 2.38 release branch created.
  19
  20 2022-01-17  Nick Clifton  <nickc@redhat.com>
  21
  22         * Makefile.in: Regenerate.
  23         * po/opcodes.pot: Regenerate.
  24
  25 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
  26
  27         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
  28         in insn_type on branching instructions.
  29
  30 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  31             Simon Cook  <simon.cook@embecosm.com>
  32
  33         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  34         (riscv_options): New static global.
  35         (disassembler_options_riscv): New function.
  36         (print_riscv_disassembler_options): Rewrite to use
  37         disassembler_options_riscv.
  38
  39 2021-11-25  Nick Clifton  <nickc@redhat.com>
  40
  41         PR 28614
  42         * aarch64-asm.c: Replace assert(0) with real code.
  43         * aarch64-dis.c: Likewise.
  44         * aarch64-opc.c: Likewise.
  45
  46 2021-11-25  Nick Clifton  <nickc@redhat.com>
  47
  48         * po/fr.po; Updated French translation.
  49
  50 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  51
  52         * Makefile.am: Remove obsolete comment.
  53         * configure.ac: Refer `libbfd.la' to link shared BFD library
  54         except for Cygwin.
  55         * Makefile.in: Regenerate.
  56         * configure: Regenerate.
  57
  58 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  59
  60         * configure: Regenerate.
  61
  62 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  63
  64         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  65         on POWER5 and later.
  66
  67 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  68
  69         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  70         before an unknown instruction, '%d' is replaced with the
  71         instruction length.
  72
  73 2021-09-02  Nick Clifton  <nickc@redhat.com>
  74
  75         PR 28292
  76         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  77         of BFD_RELOC_16.
  78
  79 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  80
  81         * arc-regs.h (DEF): Fix the register numbers.
  82
  83 2021-08-10  Nick Clifton  <nickc@redhat.com>
  84
  85         * po/sr.po: Updated Serbian translation.
  86
  87 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  88
  89         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  90
  91 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  92
  93         * s390-opc.txt: Add qpaci.
  94
  95 2021-07-03  Nick Clifton  <nickc@redhat.com>
  96
  97         * configure: Regenerate.
  98         * po/opcodes.pot: Regenerate.
  99
 100 2021-07-03  Nick Clifton  <nickc@redhat.com>
 101
 102         * 2.37 release branch created.
 103
 104 2021-07-02  Alan Modra  <amodra@gmail.com>
 105
 106         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
 107         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
 108         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
 109         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
 110         (nds32_keyword_gpr): Move declarations to..
 111         * nds32-asm.h: ..here, constifying to match definitions.
 112
 113 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 114
 115         * Makefile.am (GUILE): New variable.
 116         (CGEN): Use $(GUILE).
 117         * Makefile.in: Regenerate.
 118
 119 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 120
 121         * mep-asm.c (macros): Mark static & const.
 122         (lookup_macro): Change return & m to const.
 123         (expand_macro): Change mac to const.
 124         (expand_string): Change pmacro to const.
 125
 126 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 127
 128         * nds32-asm.c (operand_fields): Rename to ...
 129         (nds32_operand_fields): ... this.
 130         (keyword_gpr): Rename to ...
 131         (nds32_keyword_gpr): ... this.
 132         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 133         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 134         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 135         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 136         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 137         Mark static.
 138         (keywords): Rename to ...
 139         (nds32_keywords): ... this.
 140         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 141         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 142
 143 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 144
 145         * z80-dis.c (opc_ed): Make const.
 146         (pref_ed): Make p const.
 147
 148 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 149
 150         * microblaze-dis.c (get_field_special): Make op const.
 151         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 152         microblaze_opcodes.
 153         (print_insn_microblaze): Make op & pop const.
 154         (get_insn_microblaze): Make op const.  Rename opcodes to
 155         microblaze_opcodes.
 156         (microblaze_get_target_address): Likewise.
 157         * microblaze-opc.h (struct op_code_struct): Make const.
 158         Rename opcodes to microblaze_opcodes.
 159
 160 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 161
 162         * aarch64-gen.c (aarch64_opcode_table): Add const.
 163         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 164
 165 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 166
 167         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 168         available.
 169
 170 2021-06-22  Alan Modra  <amodra@gmail.com>
 171
 172         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 173         print separator for pcrel insns.
 174
 175 2021-06-19  Alan Modra  <amodra@gmail.com>
 176
 177         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 178
 179 2021-06-19  Alan Modra  <amodra@gmail.com>
 180
 181         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 182         entire buffer.
 183
 184 2021-06-17  Alan Modra  <amodra@gmail.com>
 185
 186         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 187         in table.
 188
 189 2021-06-03  Alan Modra  <amodra@gmail.com>
 190
 191         PR 1202
 192         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 193         Use unsigned int for inst.
 194
 195 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 196
 197         * arc-dis.c (arc_option_arg_t): New enumeration.
 198         (arc_options): New variable.
 199         (disassembler_options_arc): New function.
 200         (print_arc_disassembler_options): Reimplement in terms of
 201         "disassembler_options_arc".
 202
 203 2021-05-29  Alan Modra  <amodra@gmail.com>
 204
 205         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 206         Don't special case PPC_OPCODE_RAW.
 207         (lookup_prefix): Likewise.
 208         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 209         (print_insn_powerpc): ..update caller.
 210         * ppc-opc.c (EXT): Define.
 211         (powerpc_opcodes): Mark extended mnemonics with EXT.
 212         (prefix_opcodes, vle_opcodes): Likewise.
 213         (XISEL, XISEL_MASK): Add cr field and simplify.
 214         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 215         all isel variants to where the base mnemonic belongs.  Sort dstt,
 216         dststt and dssall.
 217
 218 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 219
 220         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 221         COP3 opcode instructions.
 222
 223 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 224
 225         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 226         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 227         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 228         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 229         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 230         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 231         "cop2", and "cop3" entries.
 232
 233 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 234
 235         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 236         entries and associated comments.
 237
 238 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 239
 240         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 241         of "c0".
 242
 243 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 244
 245         * mips-dis.c (mips_cp1_names_mips): New variable.
 246         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 247         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 248         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 249         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 250         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 251         "loongson2f".
 252
 253 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 254
 255         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 256         handling code over to...
 257         <OP_REG_CONTROL>: ... this new case.
 258         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 259         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 260         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 261         replacing the `G' operand code with `g'.  Update "cftc1" and
 262         "cftc2" entries replacing the `E' operand code with `y'.
 263         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 264         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 265         entries replacing the `G' operand code with `g'.
 266
 267 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 268
 269         * mips-dis.c (mips_cp0_names_r3900): New variable.
 270         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 271         for "r3900".
 272
 273 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 274
 275         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 276         and "mtthc2" to using the `G' rather than `g' operand code for
 277         the coprocessor control register referred.
 278
 279 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 280
 281         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 282         entries with each other.
 283
 284 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 285
 286         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 287
 288 2021-05-25  Alan Modra  <amodra@gmail.com>
 289
 290         * cris-desc.c: Regenerate.
 291         * cris-desc.h: Regenerate.
 292         * cris-opc.h: Regenerate.
 293         * po/POTFILES.in: Regenerate.
 294
 295 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 296
 297         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 298         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 299         (CGEN_CPUS): Add cris.
 300         (CRIS_DEPS): Define.
 301         (stamp-cris): New rule.
 302         * cgen.sh: Handle desc action.
 303         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 304         * Makefile.in, configure: Regenerate.
 305
 306 2021-05-18  Job Noorman  <mtvec@pm.me>
 307
 308         PR 27814
 309         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 310         the elf objects.
 311
 312 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 313
 314         * arm-dis.c (mve_opcodes): Fix disassembly of
 315         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 316         (is_mve_encoding_conflict): MVE vector loads should not match
 317         when P = W = 0.
 318         (is_mve_unpredictable): It's not unpredictable to use the same
 319         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 320
 321 2021-05-11  Nick Clifton  <nickc@redhat.com>
 322
 323         PR 27840
 324         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 325         the end of the code buffer.
 326
 327 2021-05-06  Stafford Horne  <shorne@gmail.com>
 328
 329         PR 21464
 330         * or1k-asm.c: Regenerate.
 331
 332 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 333
 334         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 335         info->insn_info_valid.
 336
 337 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-opc.tbl (lea): Add Optimize.
 340         * opcodes/i386-tbl.h: Re-generate.
 341
 342 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 343
 344         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 345         of l32r fetch and display referenced literal value.
 346
 347 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 348
 349         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 350         to 4 for literal disassembly.
 351
 352 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 353
 354         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 355         for TLBI instruction.
 356
 357 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 358
 359         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 360         DC instruction.
 361
 362 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 363
 364         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 365         "qualifier".
 366         (convert_mov_to_movewide): Add initializer for "value".
 367
 368 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 369
 370         * aarch64-opc.c: Add RME system registers.
 371
 372 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 373
 374         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 375         "addi d,CV,z" to "c.mv d,CV".
 376
 377 2021-04-12  Alan Modra  <amodra@gmail.com>
 378
 379         * configure.ac (--enable-checking): Add support.
 380         * config.in: Regenerate.
 381         * configure: Regenerate.
 382
 383 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 384
 385         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 386         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 387
 388 2021-04-09  Alan Modra  <amodra@gmail.com>
 389
 390         * ppc-dis.c (struct dis_private): Add "special".
 391         (POWERPC_DIALECT): Delete.  Replace uses with..
 392         (private_data): ..this.  New inline function.
 393         (disassemble_init_powerpc): Init "special" names.
 394         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 395         field of prefix instructions.
 396         (bsearch_reloc, print_got_plt): New functions.
 397         (print_insn_powerpc): For pcrel instructions, print target address
 398         and symbol if known, and decode plt and got loads too.
 399
 400 2021-04-08  Alan Modra  <amodra@gmail.com>
 401
 402         PR 27684
 403         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 404
 405 2021-04-08  Alan Modra  <amodra@gmail.com>
 406
 407         PR 27676
 408         * ppc-opc.c (DCBT_EO): Move earlier.
 409         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 410         (powerpc_operands): Add THCT and THDS entries.
 411         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 412
 413 2021-04-06  Alan Modra  <amodra@gmail.com>
 414
 415         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 416         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 417         symbol_at_address_func.
 418
 419 2021-04-05  Alan Modra  <amodra@gmail.com>
 420
 421         * configure.ac: Don't check for limits.h, string.h, strings.h or
 422         stdlib.h.
 423         (AC_ISC_POSIX): Don't invoke.
 424         * sysdep.h: Include stdlib.h and string.h unconditionally.
 425         * i386-opc.h: Include limits.h unconditionally.
 426         * wasm32-dis.c: Likewise.
 427         * cgen-opc.c: Don't include alloca-conf.h.
 428         * config.in: Regenerate.
 429         * configure: Regenerate.
 430
 431 2021-04-01  Martin Liska  <mliska@suse.cz>
 432
 433         * arm-dis.c (strneq): Remove strneq and use startswith.
 434         * cr16-dis.c (print_insn_cr16): Likewise.
 435         * score-dis.c (streq): Likewise.
 436         (strneq): Likewise.
 437         * score7-dis.c (strneq): Likewise.
 438
 439 2021-04-01  Alan Modra  <amodra@gmail.com>
 440
 441         PR 27675
 442         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 443
 444 2021-03-31  Alan Modra  <amodra@gmail.com>
 445
 446         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 447         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 448         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 449         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 450         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 451         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 452         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 453         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 454         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 455         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 456         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 457         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 458         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 459         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 460         and TRUE with true throughout.
 461
 462 2021-03-31  Alan Modra  <amodra@gmail.com>
 463
 464         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 465         * aarch64-dis.h: Likewise.
 466         * aarch64-opc.c: Likewise.
 467         * avr-dis.c: Likewise.
 468         * csky-dis.c: Likewise.
 469         * nds32-asm.c: Likewise.
 470         * nds32-dis.c: Likewise.
 471         * nfp-dis.c: Likewise.
 472         * riscv-dis.c: Likewise.
 473         * s12z-dis.c: Likewise.
 474         * wasm32-dis.c: Likewise.
 475
 476 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 479         (i386_seg_prefixes): New.
 480         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 481         (i386_seg_prefixes): Declare.
 482
 483 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 484
 485         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 486
 487 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 488
 489         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 490         * i386-reg.tbl (st): Move down.
 491         (st(0)): Delete. Extend comment.
 492         * i386-tbl.h: Re-generate.
 493
 494 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 495
 496         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 497         (cmpsd): Move next to cmps.
 498         (movsd): Move next to movs.
 499         (cmpxchg16b): Move to separate section.
 500         (fisttp, fisttpll): Likewise.
 501         (monitor, mwait): Likewise.
 502         * i386-tbl.h: Re-generate.
 503
 504 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 507         (vpsadbw): Add C.
 508         * i386-tbl.h: Re-generate.
 509
 510 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 513         pclmul, gfni): New templates. Use them wherever possible. Move
 514         SSE4.1 pextrw into respective section.
 515         * i386-tbl.h: Re-generate.
 516
 517 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 520         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 521         "length".
 522         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 523         Convert all of their uses to representation in opcode.
 524
 525 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 526
 527         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 528         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 529         value of None. Shrink operands to 3 bits.
 530
 531 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 532
 533         * i386-gen.c (process_i386_opcode_modifier): New parameter
 534         "space".
 535         (output_i386_opcode): New local variable "space". Adjust
 536         process_i386_opcode_modifier() invocation.
 537         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 538         invocation.
 539         * i386-tbl.h: Re-generate.
 540
 541 2021-03-29  Alan Modra  <amodra@gmail.com>
 542
 543         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 544         (fp_qualifier_p, get_data_pattern): Likewise.
 545         (aarch64_get_operand_modifier_from_value): Likewise.
 546         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 547         (operand_variant_qualifier_p): Likewise.
 548         (qualifier_value_in_range_constraint_p): Likewise.
 549         (aarch64_get_qualifier_esize): Likewise.
 550         (aarch64_get_qualifier_nelem): Likewise.
 551         (aarch64_get_qualifier_standard_value): Likewise.
 552         (get_lower_bound, get_upper_bound): Likewise.
 553         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 554         (aarch64_print_operand): Likewise.
 555         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 556         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 557         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 558         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 559         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 560         (print_insn_tic6x): Likewise.
 561
 562 2021-03-29  Alan Modra  <amodra@gmail.com>
 563
 564         * arc-dis.c (extract_operand_value): Correct NULL cast.
 565         * frv-opc.h: Regenerate.
 566
 567 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 568
 569         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 570         MMX form.
 571         * i386-tbl.h: Re-generate.
 572
 573 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 574
 575         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 576         immediate in br.n instruction.
 577
 578 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-dis.c (XMGatherD, VexGatherD): New.
 581         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 582         (print_insn): Check masking for S/G insns.
 583         (OP_E_memory): New local variable check_gather. Extend mandatory
 584         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 585         Extend check for disallowed 16-bit addressing.
 586         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 587         if()s to switch(). Check register conflicts for (VEX-encoded)
 588         gathers. Drop no longer reachable cases.
 589         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 590         vgatherdp*.
 591
 592 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 595         zeroing-masking without masking.
 596
 597 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 598
 599         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 600         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 601         single-operand forms as deprecated.
 602         * i386-tbl.h: Re-generate.
 603
 604 2021-03-25  Alan Modra  <amodra@gmail.com>
 605
 606         PR 27647
 607         * ppc-opc.c (XLOCB_MASK): Delete.
 608         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 609         XLBH_MASK.
 610         (powerpc_opcodes): Accept a BH field on all extended forms of
 611         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 612
 613 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-gen.c (output_i386_opcode): Drop processing of
 616         opcode_length. Calculate length from base_opcode. Adjust prefix
 617         encoding determination.
 618         (process_i386_opcodes): Drop output of fake opcode_length.
 619         * i386-opc.h (struct insn_template): Drop opcode_length field.
 620         * i386-opc.tbl: Drop opcode length field from all templates.
 621         * i386-tbl.h: Re-generate.
 622
 623 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 624
 625         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 626         parameter "prefix". Drop local variable "regular_encoding".
 627         Record prefix setting / check for consistency.
 628         (output_i386_opcode): Parse opcode_length and base_opcode
 629         earlier. Derive prefix encoding. Drop no longer applicable
 630         consistency checking. Adjust process_i386_opcode_modifier()
 631         invocation.
 632         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 633         invocation.
 634         * i386-tbl.h: Re-generate.
 635
 636 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 637
 638         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 639         check.
 640         * i386-opc.h (Prefix_*): Move #define-s.
 641         * i386-opc.tbl: Move pseudo prefix enumerator values to
 642         extension opcode field. Introduce pseudopfx template.
 643         * i386-tbl.h: Re-generate.
 644
 645 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 646
 647         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 648         comment.
 649         * i386-tbl.h: Re-generate.
 650
 651 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-opc.h (struct insn_template): Move cpu_flags field past
 654         opcode_modifier one.
 655         * i386-tbl.h: Re-generate.
 656
 657 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 660         * i386-opc.h (OpcodeSpace): New enumerator.
 661         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 662         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 663         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 664         (struct i386_opcode_modifier): New field opcodespace. Shrink
 665         opcodeprefix field.
 666         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 667         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 668         OpcodePrefix uses.
 669         * i386-tbl.h: Re-generate.
 670
 671 2021-03-22  Martin Liska  <mliska@suse.cz>
 672
 673         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 674         * arc-dis.c (parse_option): Likewise.
 675         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 676         * cris-dis.c (print_with_operands): Likewise.
 677         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 678         * i386-dis.c (print_insn): Likewise.
 679         * ia64-gen.c (fetch_insn_class): Likewise.
 680         (parse_resource_users): Likewise.
 681         (in_iclass): Likewise.
 682         (lookup_specifier): Likewise.
 683         (insert_opcode_dependencies): Likewise.
 684         * mips-dis.c (parse_mips_ase_option): Likewise.
 685         (parse_mips_dis_option): Likewise.
 686         * s390-dis.c (disassemble_init_s390): Likewise.
 687         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 688
 689 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 690
 691         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 692
 693 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 694
 695         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 696         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 697
 698 2021-03-12  Alan Modra  <amodra@gmail.com>
 699
 700         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 701
 702 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 703
 704         * i386-dis.c (OP_XMM): Re-order checks.
 705
 706 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-dis.c (putop): Drop need_vex check when also checking
 709         vex.evex.
 710         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 711         checking vex.b.
 712
 713 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 714
 715         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 716         checks. Move case label past broadcast check.
 717
 718 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 719
 720         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 721         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 722         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 723         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 724         EVEX_W_0F38C7_M_0_L_2): Delete.
 725         (REG_EVEX_0F38C7_M_0_L_2): New.
 726         (intel_operand_size): Handle VEX and EVEX the same for
 727         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 728         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 729         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 730         vex_vsib_q_w_d_mode uses.
 731         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 732         0F38A1, and 0F38A3 entries.
 733         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 734         entry.
 735         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 736         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 737         0F38A3 entries.
 738
 739 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 740
 741         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 742         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 743         MOD_VEX_0FXOP_09_12): Rename to ...
 744         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 745         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 746         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 747         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 748         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 749         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 750         (reg_table): Adjust comments.
 751         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 752         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 753         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 754         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 755         (vex_len_table): Adjust opcode 0A_12 entry.
 756         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 757         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 758         (rm_table): Move hreset entry.
 759
 760 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 761
 762         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 763         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 764         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 765         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 766         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 767         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 768         (get_valid_dis386): Also handle 512-bit vector length when
 769         vectoring into vex_len_table[].
 770         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 771         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 772         entries.
 773         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 774         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 775         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 776         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 777         entries.
 778
 779 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 780
 781         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 782         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 783         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 784         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 785         entries.
 786         * i386-dis-evex-len.h (evex_len_table): Likewise.
 787         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 788
 789 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 790
 791         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 792         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 793         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 794         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 795         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 796         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 797         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 798         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 799         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 800         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 801         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 802         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 803         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 804         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 805         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 806         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 807         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 808         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 809         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 810         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 811         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 812         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 813         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 814         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 815         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 816         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 817         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 818         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 819         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 820         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 821         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 822         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 823         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 824         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 825         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 826         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 827         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 828         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 829         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 830         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 831         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 832         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 833         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 834         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 835         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 836         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 837         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 838         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 839         EVEX_W_0F3A43_L_n): New.
 840         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 841         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 842         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 843         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 844         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 845         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 846         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 847         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 848         0F385B, 0F38C6, and 0F38C7 entries.
 849         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 850         0F38C6 and 0F38C7.
 851         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 852         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 853         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 854         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 855
 856 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 857
 858         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 859         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 860         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 861         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 862         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 863         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 864         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 865         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 866         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 867         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 868         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 869         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 870         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 871         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 872         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 873         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 874         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 875         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 876         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 877         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 878         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 879         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 880         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 881         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 882         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 883         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 884         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 885         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 886         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 887         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 888         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 889         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 890         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 891         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 892         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 893         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 894         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 895         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 896         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 897         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 898         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 899         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 900         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 901         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 902         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 903         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 904         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 905         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 906         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 907         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 908         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 909         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 910         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 911         VEX_W_0F99_P_2_LEN_0): Delete.
 912         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 913         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 914         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 915         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 916         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 917         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 918         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 919         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 920         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 921         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 922         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 923         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 924         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 925         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 926         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 927         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 928         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 929         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 930         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 931         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 932         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 933         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 934         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 935         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 936         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 937         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 938         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 939         (prefix_table): No longer link to vex_len_table[] for opcodes
 940         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 941         0F92, 0F93, 0F98, and 0F99.
 942         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 943         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 944         0F98, and 0F99.
 945         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 946         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 947         0F98, and 0F99.
 948         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 949         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 950         0F98, and 0F99.
 951         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 952         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 953         0F98, and 0F99.
 954
 955 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 956
 957         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 958         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 959         REG_VEX_0F73_M_0 respectively.
 960         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 961         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 962         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 963         MOD_VEX_0F73_REG_7): Delete.
 964         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 965         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 966         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 967         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 968         PREFIX_VEX_0F3AF0_L_0 respectively.
 969         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 970         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 971         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 972         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 973         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 974         VEX_LEN_0F38F7): New.
 975         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 976         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 977         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 978         0F38F3.
 979         (prefix_table): No longer link to vex_len_table[] for opcodes
 980         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 981         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 982         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 983         0F38F6, 0F38F7, and 0F3AF0.
 984         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 985         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 986         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 987         0F73.
 988
 989 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 990
 991         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 992         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 993         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 994         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 995         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 996         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 997         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 998         73.
 999         (reg_table): No longer link to mod_table[] for opcodes 0F71,
1000         0F72, and 0F73.
1001         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1002         0F73.
1003
1004 2021-03-10  Jan Beulich  <jbeulich@suse.com>
1005
1006         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1007         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1008         (reg_table): Don't link to mod_table[] where not needed. Add
1009         PREFIX_IGNORED to nop entries.
1010         (prefix_table): Replace PREFIX_OPCODE in nop entries.
1011         (mod_table): Add nop entries next to prefetch ones. Drop
1012         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1013         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1014         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1015         PREFIX_OPCODE from endbr* entries.
1016         (get_valid_dis386): Also consider entry's name when zapping
1017         vindex.
1018         (print_insn): Handle PREFIX_IGNORED.
1019
1020 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1021
1022         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1023         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1024         element.
1025         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1026         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1027         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1028         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1029         (struct i386_opcode_modifier): Delete notrackprefixok,
1030         islockable, hleprefixok, and repprefixok fields. Add prefixok
1031         field.
1032         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1033         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1034         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1035         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1036         Replace HLEPrefixOk.
1037         * opcodes/i386-tbl.h: Re-generate.
1038
1039 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1040
1041         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1042         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1043         64-bit form.
1044         * opcodes/i386-tbl.h: Re-generate.
1045
1046 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1047
1048         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1049         for {} instead of {0}. Don't look for '0'.
1050         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1051         size specifiers.
1052
1053 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1054
1055         PR 27158
1056         * riscv-dis.c (print_insn_args): Updated encoding macros.
1057         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1058         (match_c_addi16sp): Updated encoding macros.
1059         (match_c_lui): Likewise.
1060         (match_c_lui_with_hint): Likewise.
1061         (match_c_addi4spn): Likewise.
1062         (match_c_slli): Likewise.
1063         (match_slli_as_c_slli): Likewise.
1064         (match_c_slli64): Likewise.
1065         (match_srxi_as_c_srxi): Likewise.
1066         (riscv_insn_types): Added .insn css/cl/cs.
1067
1068 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1069
1070         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1071         (default_priv_spec): Updated type to riscv_spec_class.
1072         (parse_riscv_dis_option): Updated.
1073         * riscv-opc.c: Moved stuff and make the file tidy.
1074
1075 2021-02-17  Alan Modra  <amodra@gmail.com>
1076
1077         * wasm32-dis.c: Include limits.h.
1078         (CHAR_BIT): Provide backup define.
1079         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1080         Correct signed overflow checking.
1081
1082 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1083
1084         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1085         * i386-tbl.h: Re-generate.
1086
1087 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1088
1089         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1090         Oword.
1091         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1092
1093 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1094
1095         * s390-mkopc.c (main): Accept arch14 as cpu string.
1096         * s390-opc.txt: Add new arch14 instructions.
1097
1098 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1099
1100         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1101         favour of LIBINTL.
1102         * configure: Regenerated.
1103
1104 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1105
1106         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1107         * tic54x-opc.c (regs): Rename to ...
1108         (tic54x_regs): ... this.
1109         (mmregs): Rename to ...
1110         (tic54x_mmregs): ... this.
1111         (condition_codes): Rename to ...
1112         (tic54x_condition_codes): ... this.
1113         (cc2_codes): Rename to ...
1114         (tic54x_cc2_codes): ... this.
1115         (cc3_codes): Rename to ...
1116         (tic54x_cc3_codes): ... this.
1117         (status_bits): Rename to ...
1118         (tic54x_status_bits): ... this.
1119         (misc_symbols): Rename to ...
1120         (tic54x_misc_symbols): ... this.
1121
1122 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1123
1124         * riscv-opc.c (MASK_RVB_IMM): Removed.
1125         (riscv_opcodes): Removed zb* instructions.
1126         (riscv_ext_version_table): Removed versions for zb*.
1127
1128 2021-01-26  Alan Modra  <amodra@gmail.com>
1129
1130         * i386-gen.c (parse_template): Ensure entire template_instance
1131         is initialised.
1132
1133 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1134
1135         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1136         (riscv_fpr_names_abi): Likewise.
1137         (riscv_opcodes): Likewise.
1138         (riscv_insn_types): Likewise.
1139
1140 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1141
1142         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1143
1144 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1145
1146         * riscv-dis.c: Comments tidy and improvement.
1147         * riscv-opc.c: Likewise.
1148
1149 2021-01-13  Alan Modra  <amodra@gmail.com>
1150
1151         * Makefile.in: Regenerate.
1152
1153 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1154
1155         PR binutils/26792
1156         * configure.ac: Use GNU_MAKE_JOBSERVER.
1157         * aclocal.m4: Regenerated.
1158         * configure: Likewise.
1159
1160 2021-01-12  Nick Clifton  <nickc@redhat.com>
1161
1162         * po/sr.po: Updated Serbian translation.
1163
1164 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1165
1166         PR ld/27173
1167         * configure: Regenerated.
1168
1169 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1170
1171         * aarch64-asm-2.c: Regenerate.
1172         * aarch64-dis-2.c: Likewise.
1173         * aarch64-opc-2.c: Likewise.
1174         * aarch64-opc.c (aarch64_print_operand):
1175         Delete handling of AARCH64_OPND_CSRE_CSR.
1176         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1177         (CSRE): Likewise.
1178         (_CSRE_INSN): Likewise.
1179         (aarch64_opcode_table): Delete csr.
1180
1181 2021-01-11  Nick Clifton  <nickc@redhat.com>
1182
1183         * po/de.po: Updated German translation.
1184         * po/fr.po: Updated French translation.
1185         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1186         * po/sv.po: Updated Swedish translation.
1187         * po/uk.po: Updated Ukranian translation.
1188
1189 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1190
1191         * configure: Regenerated.
1192
1193 2021-01-09  Nick Clifton  <nickc@redhat.com>
1194
1195         * configure: Regenerate.
1196         * po/opcodes.pot: Regenerate.
1197
1198 2021-01-09  Nick Clifton  <nickc@redhat.com>
1199
1200         * 2.36 release branch crated.
1201
1202 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1203
1204         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1205         (DW, (XRC_MASK): Define.
1206         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1207
1208 2021-01-09  Alan Modra  <amodra@gmail.com>
1209
1210         * configure: Regenerate.
1211
1212 2021-01-08  Nick Clifton  <nickc@redhat.com>
1213
1214         * po/sv.po: Updated Swedish translation.
1215
1216 2021-01-08  Nick Clifton  <nickc@redhat.com>
1217
1218         PR 27129
1219         * aarch64-dis.c (determine_disassembling_preference): Move call to
1220         aarch64_match_operands_constraint outside of the assertion.
1221         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1222         Replace with a return of FALSE.
1223
1224         PR 27139
1225         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1226         core system register.
1227
1228 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1229
1230         * configure: Regenerate.
1231
1232 2021-01-07  Nick Clifton  <nickc@redhat.com>
1233
1234         * po/fr.po: Updated French translation.
1235
1236 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1237
1238         * m68k-opc.c (chkl): Change minimum architecture requirement to
1239         m68020.
1240
1241 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1242
1243         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1244
1245 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1246             Jim Wilson  <jimw@sifive.com>
1247             Andrew Waterman  <andrew@sifive.com>
1248             Maxim Blinov  <maxim.blinov@embecosm.com>
1249             Kito Cheng  <kito.cheng@sifive.com>
1250             Nelson Chu  <nelson.chu@sifive.com>
1251
1252         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1253         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1254
1255 2021-01-01  Alan Modra  <amodra@gmail.com>
1256
1257         Update year range in copyright notice of all files.
1258
1259 For older changes see ChangeLog-2020
1260 \f
1261 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1262
1263 Copying and distribution of this file, with or without modification,
1264 are permitted in any medium without royalty provided the copyright
1265 notice and this notice are preserved.
1266
1267 Local Variables:
1268 mode: change-log
1269 left-margin: 8
1270 fill-column: 74
1271 version-control: never
1272 End: