opcodes/ChangeLog

   1 2022-01-22  Nick Clifton  <nickc@redhat.com>
   2
   3         * 2.38 release branch created.
   4
   5 2022-01-17  Nick Clifton  <nickc@redhat.com>
   6
   7         * Makefile.in: Regenerate.
   8         * po/opcodes.pot: Regenerate.
   9
  10 2021-12-02  Marcus Nilsson  <brainbomb@gmail.com>
  11
  12         * avr-dis.c (avr_operand); Pass in disassemble_info and fill
  13         in insn_type on branching instructions.
  14
  15 2021-11-25  Andrew Burgess  <aburgess@redhat.com>
  16             Simon Cook  <simon.cook@embecosm.com>
  17
  18         * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
  19         (riscv_options): New static global.
  20         (disassembler_options_riscv): New function.
  21         (print_riscv_disassembler_options): Rewrite to use
  22         disassembler_options_riscv.
  23
  24 2021-11-25  Nick Clifton  <nickc@redhat.com>
  25
  26         PR 28614
  27         * aarch64-asm.c: Replace assert(0) with real code.
  28         * aarch64-dis.c: Likewise.
  29         * aarch64-opc.c: Likewise.
  30
  31 2021-11-25  Nick Clifton  <nickc@redhat.com>
  32
  33         * po/fr.po; Updated French translation.
  34
  35 2021-10-27  Maciej W. Rozycki  <macro@embecosm.com>
  36
  37         * Makefile.am: Remove obsolete comment.
  38         * configure.ac: Refer `libbfd.la' to link shared BFD library
  39         except for Cygwin.
  40         * Makefile.in: Regenerate.
  41         * configure: Regenerate.
  42
  43 2021-09-27  Nick Alcock  <nick.alcock@oracle.com>
  44
  45         * configure: Regenerate.
  46
  47 2021-09-25  Peter Bergner  <bergner@linux.ibm.com>
  48
  49         * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
  50         on POWER5 and later.
  51
  52 2021-09-20  Andrew Burgess  <andrew.burgess@embecosm.com>
  53
  54         * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
  55         before an unknown instruction, '%d' is replaced with the
  56         instruction length.
  57
  58 2021-09-02  Nick Clifton  <nickc@redhat.com>
  59
  60         PR 28292
  61         * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
  62         of BFD_RELOC_16.
  63
  64 2021-08-17  Shahab Vahedi <shahab@synopsys.com>
  65
  66         * arc-regs.h (DEF): Fix the register numbers.
  67
  68 2021-08-10  Nick Clifton  <nickc@redhat.com>
  69
  70         * po/sr.po: Updated Serbian translation.
  71
  72 2021-07-26  Chenghua Xu  <xuchenghua@loongson.cn>
  73
  74         * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
  75
  76 2021-06-07  Andreas Krebbel  <krebbel@linux.ibm.com>
  77
  78         * s390-opc.txt: Add qpaci.
  79
  80 2021-07-03  Nick Clifton  <nickc@redhat.com>
  81
  82         * configure: Regenerate.
  83         * po/opcodes.pot: Regenerate.
  84
  85 2021-07-03  Nick Clifton  <nickc@redhat.com>
  86
  87         * 2.37 release branch created.
  88
  89 2021-07-02  Alan Modra  <amodra@gmail.com>
  90
  91         * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
  92         (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
  93         (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
  94         (nds32_opcodes, nds32_operand_fields, nds32_keywords),
  95         (nds32_keyword_gpr): Move declarations to..
  96         * nds32-asm.h: ..here, constifying to match definitions.
  97
  98 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
  99
 100         * Makefile.am (GUILE): New variable.
 101         (CGEN): Use $(GUILE).
 102         * Makefile.in: Regenerate.
 103
 104 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 105
 106         * mep-asm.c (macros): Mark static & const.
 107         (lookup_macro): Change return & m to const.
 108         (expand_macro): Change mac to const.
 109         (expand_string): Change pmacro to const.
 110
 111 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 112
 113         * nds32-asm.c (operand_fields): Rename to ...
 114         (nds32_operand_fields): ... this.
 115         (keyword_gpr): Rename to ...
 116         (nds32_keyword_gpr): ... this.
 117         (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
 118         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
 119         keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
 120         keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
 121         keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
 122         Mark static.
 123         (keywords): Rename to ...
 124         (nds32_keywords): ... this.
 125         * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
 126         keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
 127
 128 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 129
 130         * z80-dis.c (opc_ed): Make const.
 131         (pref_ed): Make p const.
 132
 133 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 134
 135         * microblaze-dis.c (get_field_special): Make op const.
 136         (read_insn_microblaze): Make opr & op const.  Rename opcodes to
 137         microblaze_opcodes.
 138         (print_insn_microblaze): Make op & pop const.
 139         (get_insn_microblaze): Make op const.  Rename opcodes to
 140         microblaze_opcodes.
 141         (microblaze_get_target_address): Likewise.
 142         * microblaze-opc.h (struct op_code_struct): Make const.
 143         Rename opcodes to microblaze_opcodes.
 144
 145 2021-07-01  Mike Frysinger  <vapier@gentoo.org>
 146
 147         * aarch64-gen.c (aarch64_opcode_table): Add const.
 148         * aarch64-tbl.h (aarch64_opcode_table): Likewise.
 149
 150 2021-06-22  Andrew Burgess  <andrew.burgess@embecosm.com>
 151
 152         * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
 153         available.
 154
 155 2021-06-22  Alan Modra  <amodra@gmail.com>
 156
 157         * pj-dis.c (print_insn_pj): Don't print trailing tab.  Do
 158         print separator for pcrel insns.
 159
 160 2021-06-19  Alan Modra  <amodra@gmail.com>
 161
 162         * vax-dis.c (print_insn_vax): Avoid pointer overflow.
 163
 164 2021-06-19  Alan Modra  <amodra@gmail.com>
 165
 166         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
 167         entire buffer.
 168
 169 2021-06-17  Alan Modra  <amodra@gmail.com>
 170
 171         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
 172         in table.
 173
 174 2021-06-03  Alan Modra  <amodra@gmail.com>
 175
 176         PR 1202
 177         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
 178         Use unsigned int for inst.
 179
 180 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
 181
 182         * arc-dis.c (arc_option_arg_t): New enumeration.
 183         (arc_options): New variable.
 184         (disassembler_options_arc): New function.
 185         (print_arc_disassembler_options): Reimplement in terms of
 186         "disassembler_options_arc".
 187
 188 2021-05-29  Alan Modra  <amodra@gmail.com>
 189
 190         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
 191         Don't special case PPC_OPCODE_RAW.
 192         (lookup_prefix): Likewise.
 193         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
 194         (print_insn_powerpc): ..update caller.
 195         * ppc-opc.c (EXT): Define.
 196         (powerpc_opcodes): Mark extended mnemonics with EXT.
 197         (prefix_opcodes, vle_opcodes): Likewise.
 198         (XISEL, XISEL_MASK): Add cr field and simplify.
 199         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
 200         all isel variants to where the base mnemonic belongs.  Sort dstt,
 201         dststt and dssall.
 202
 203 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 204
 205         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
 206         COP3 opcode instructions.
 207
 208 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 209
 210         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
 211         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
 212         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
 213         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
 214         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
 215         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
 216         "cop2", and "cop3" entries.
 217
 218 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 219
 220         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
 221         entries and associated comments.
 222
 223 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 224
 225         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
 226         of "c0".
 227
 228 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 229
 230         * mips-dis.c (mips_cp1_names_mips): New variable.
 231         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
 232         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
 233         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
 234         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
 235         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
 236         "loongson2f".
 237
 238 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 239
 240         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
 241         handling code over to...
 242         <OP_REG_CONTROL>: ... this new case.
 243         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
 244         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
 245         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
 246         replacing the `G' operand code with `g'.  Update "cftc1" and
 247         "cftc2" entries replacing the `E' operand code with `y'.
 248         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
 249         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
 250         entries replacing the `G' operand code with `g'.
 251
 252 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 253
 254         * mips-dis.c (mips_cp0_names_r3900): New variable.
 255         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
 256         for "r3900".
 257
 258 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 259
 260         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
 261         and "mtthc2" to using the `G' rather than `g' operand code for
 262         the coprocessor control register referred.
 263
 264 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 265
 266         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 267         entries with each other.
 268
 269 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 270
 271         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 272
 273 2021-05-25  Alan Modra  <amodra@gmail.com>
 274
 275         * cris-desc.c: Regenerate.
 276         * cris-desc.h: Regenerate.
 277         * cris-opc.h: Regenerate.
 278         * po/POTFILES.in: Regenerate.
 279
 280 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 281
 282         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 283         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 284         (CGEN_CPUS): Add cris.
 285         (CRIS_DEPS): Define.
 286         (stamp-cris): New rule.
 287         * cgen.sh: Handle desc action.
 288         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 289         * Makefile.in, configure: Regenerate.
 290
 291 2021-05-18  Job Noorman  <mtvec@pm.me>
 292
 293         PR 27814
 294         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 295         the elf objects.
 296
 297 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 298
 299         * arm-dis.c (mve_opcodes): Fix disassembly of
 300         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 301         (is_mve_encoding_conflict): MVE vector loads should not match
 302         when P = W = 0.
 303         (is_mve_unpredictable): It's not unpredictable to use the same
 304         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 305
 306 2021-05-11  Nick Clifton  <nickc@redhat.com>
 307
 308         PR 27840
 309         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 310         the end of the code buffer.
 311
 312 2021-05-06  Stafford Horne  <shorne@gmail.com>
 313
 314         PR 21464
 315         * or1k-asm.c: Regenerate.
 316
 317 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 318
 319         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 320         info->insn_info_valid.
 321
 322 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-opc.tbl (lea): Add Optimize.
 325         * opcodes/i386-tbl.h: Re-generate.
 326
 327 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 328
 329         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 330         of l32r fetch and display referenced literal value.
 331
 332 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 333
 334         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 335         to 4 for literal disassembly.
 336
 337 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 338
 339         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 340         for TLBI instruction.
 341
 342 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 343
 344         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 345         DC instruction.
 346
 347 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 348
 349         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 350         "qualifier".
 351         (convert_mov_to_movewide): Add initializer for "value".
 352
 353 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 354
 355         * aarch64-opc.c: Add RME system registers.
 356
 357 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 358
 359         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 360         "addi d,CV,z" to "c.mv d,CV".
 361
 362 2021-04-12  Alan Modra  <amodra@gmail.com>
 363
 364         * configure.ac (--enable-checking): Add support.
 365         * config.in: Regenerate.
 366         * configure: Regenerate.
 367
 368 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 369
 370         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 371         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 372
 373 2021-04-09  Alan Modra  <amodra@gmail.com>
 374
 375         * ppc-dis.c (struct dis_private): Add "special".
 376         (POWERPC_DIALECT): Delete.  Replace uses with..
 377         (private_data): ..this.  New inline function.
 378         (disassemble_init_powerpc): Init "special" names.
 379         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 380         field of prefix instructions.
 381         (bsearch_reloc, print_got_plt): New functions.
 382         (print_insn_powerpc): For pcrel instructions, print target address
 383         and symbol if known, and decode plt and got loads too.
 384
 385 2021-04-08  Alan Modra  <amodra@gmail.com>
 386
 387         PR 27684
 388         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 389
 390 2021-04-08  Alan Modra  <amodra@gmail.com>
 391
 392         PR 27676
 393         * ppc-opc.c (DCBT_EO): Move earlier.
 394         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 395         (powerpc_operands): Add THCT and THDS entries.
 396         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 397
 398 2021-04-06  Alan Modra  <amodra@gmail.com>
 399
 400         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 401         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 402         symbol_at_address_func.
 403
 404 2021-04-05  Alan Modra  <amodra@gmail.com>
 405
 406         * configure.ac: Don't check for limits.h, string.h, strings.h or
 407         stdlib.h.
 408         (AC_ISC_POSIX): Don't invoke.
 409         * sysdep.h: Include stdlib.h and string.h unconditionally.
 410         * i386-opc.h: Include limits.h unconditionally.
 411         * wasm32-dis.c: Likewise.
 412         * cgen-opc.c: Don't include alloca-conf.h.
 413         * config.in: Regenerate.
 414         * configure: Regenerate.
 415
 416 2021-04-01  Martin Liska  <mliska@suse.cz>
 417
 418         * arm-dis.c (strneq): Remove strneq and use startswith.
 419         * cr16-dis.c (print_insn_cr16): Likewise.
 420         * score-dis.c (streq): Likewise.
 421         (strneq): Likewise.
 422         * score7-dis.c (strneq): Likewise.
 423
 424 2021-04-01  Alan Modra  <amodra@gmail.com>
 425
 426         PR 27675
 427         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 428
 429 2021-03-31  Alan Modra  <amodra@gmail.com>
 430
 431         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 432         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 433         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 434         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 435         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 436         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 437         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 438         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 439         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 440         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 441         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 442         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 443         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 444         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 445         and TRUE with true throughout.
 446
 447 2021-03-31  Alan Modra  <amodra@gmail.com>
 448
 449         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 450         * aarch64-dis.h: Likewise.
 451         * aarch64-opc.c: Likewise.
 452         * avr-dis.c: Likewise.
 453         * csky-dis.c: Likewise.
 454         * nds32-asm.c: Likewise.
 455         * nds32-dis.c: Likewise.
 456         * nfp-dis.c: Likewise.
 457         * riscv-dis.c: Likewise.
 458         * s12z-dis.c: Likewise.
 459         * wasm32-dis.c: Likewise.
 460
 461 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 462
 463         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 464         (i386_seg_prefixes): New.
 465         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 466         (i386_seg_prefixes): Declare.
 467
 468 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 471
 472 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 473
 474         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 475         * i386-reg.tbl (st): Move down.
 476         (st(0)): Delete. Extend comment.
 477         * i386-tbl.h: Re-generate.
 478
 479 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 482         (cmpsd): Move next to cmps.
 483         (movsd): Move next to movs.
 484         (cmpxchg16b): Move to separate section.
 485         (fisttp, fisttpll): Likewise.
 486         (monitor, mwait): Likewise.
 487         * i386-tbl.h: Re-generate.
 488
 489 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 492         (vpsadbw): Add C.
 493         * i386-tbl.h: Re-generate.
 494
 495 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 498         pclmul, gfni): New templates. Use them wherever possible. Move
 499         SSE4.1 pextrw into respective section.
 500         * i386-tbl.h: Re-generate.
 501
 502 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 503
 504         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 505         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 506         "length".
 507         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 508         Convert all of their uses to representation in opcode.
 509
 510 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 513         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 514         value of None. Shrink operands to 3 bits.
 515
 516 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 517
 518         * i386-gen.c (process_i386_opcode_modifier): New parameter
 519         "space".
 520         (output_i386_opcode): New local variable "space". Adjust
 521         process_i386_opcode_modifier() invocation.
 522         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 523         invocation.
 524         * i386-tbl.h: Re-generate.
 525
 526 2021-03-29  Alan Modra  <amodra@gmail.com>
 527
 528         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 529         (fp_qualifier_p, get_data_pattern): Likewise.
 530         (aarch64_get_operand_modifier_from_value): Likewise.
 531         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 532         (operand_variant_qualifier_p): Likewise.
 533         (qualifier_value_in_range_constraint_p): Likewise.
 534         (aarch64_get_qualifier_esize): Likewise.
 535         (aarch64_get_qualifier_nelem): Likewise.
 536         (aarch64_get_qualifier_standard_value): Likewise.
 537         (get_lower_bound, get_upper_bound): Likewise.
 538         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 539         (aarch64_print_operand): Likewise.
 540         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 541         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 542         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 543         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 544         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 545         (print_insn_tic6x): Likewise.
 546
 547 2021-03-29  Alan Modra  <amodra@gmail.com>
 548
 549         * arc-dis.c (extract_operand_value): Correct NULL cast.
 550         * frv-opc.h: Regenerate.
 551
 552 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 553
 554         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 555         MMX form.
 556         * i386-tbl.h: Re-generate.
 557
 558 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 559
 560         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 561         immediate in br.n instruction.
 562
 563 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 564
 565         * i386-dis.c (XMGatherD, VexGatherD): New.
 566         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 567         (print_insn): Check masking for S/G insns.
 568         (OP_E_memory): New local variable check_gather. Extend mandatory
 569         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 570         Extend check for disallowed 16-bit addressing.
 571         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 572         if()s to switch(). Check register conflicts for (VEX-encoded)
 573         gathers. Drop no longer reachable cases.
 574         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 575         vgatherdp*.
 576
 577 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 578
 579         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 580         zeroing-masking without masking.
 581
 582 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 585         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 586         single-operand forms as deprecated.
 587         * i386-tbl.h: Re-generate.
 588
 589 2021-03-25  Alan Modra  <amodra@gmail.com>
 590
 591         PR 27647
 592         * ppc-opc.c (XLOCB_MASK): Delete.
 593         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 594         XLBH_MASK.
 595         (powerpc_opcodes): Accept a BH field on all extended forms of
 596         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 597
 598 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-gen.c (output_i386_opcode): Drop processing of
 601         opcode_length. Calculate length from base_opcode. Adjust prefix
 602         encoding determination.
 603         (process_i386_opcodes): Drop output of fake opcode_length.
 604         * i386-opc.h (struct insn_template): Drop opcode_length field.
 605         * i386-opc.tbl: Drop opcode length field from all templates.
 606         * i386-tbl.h: Re-generate.
 607
 608 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 609
 610         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 611         parameter "prefix". Drop local variable "regular_encoding".
 612         Record prefix setting / check for consistency.
 613         (output_i386_opcode): Parse opcode_length and base_opcode
 614         earlier. Derive prefix encoding. Drop no longer applicable
 615         consistency checking. Adjust process_i386_opcode_modifier()
 616         invocation.
 617         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 618         invocation.
 619         * i386-tbl.h: Re-generate.
 620
 621 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 624         check.
 625         * i386-opc.h (Prefix_*): Move #define-s.
 626         * i386-opc.tbl: Move pseudo prefix enumerator values to
 627         extension opcode field. Introduce pseudopfx template.
 628         * i386-tbl.h: Re-generate.
 629
 630 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 631
 632         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 633         comment.
 634         * i386-tbl.h: Re-generate.
 635
 636 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 637
 638         * i386-opc.h (struct insn_template): Move cpu_flags field past
 639         opcode_modifier one.
 640         * i386-tbl.h: Re-generate.
 641
 642 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 643
 644         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 645         * i386-opc.h (OpcodeSpace): New enumerator.
 646         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 647         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 648         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 649         (struct i386_opcode_modifier): New field opcodespace. Shrink
 650         opcodeprefix field.
 651         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 652         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 653         OpcodePrefix uses.
 654         * i386-tbl.h: Re-generate.
 655
 656 2021-03-22  Martin Liska  <mliska@suse.cz>
 657
 658         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 659         * arc-dis.c (parse_option): Likewise.
 660         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 661         * cris-dis.c (print_with_operands): Likewise.
 662         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 663         * i386-dis.c (print_insn): Likewise.
 664         * ia64-gen.c (fetch_insn_class): Likewise.
 665         (parse_resource_users): Likewise.
 666         (in_iclass): Likewise.
 667         (lookup_specifier): Likewise.
 668         (insert_opcode_dependencies): Likewise.
 669         * mips-dis.c (parse_mips_ase_option): Likewise.
 670         (parse_mips_dis_option): Likewise.
 671         * s390-dis.c (disassemble_init_s390): Likewise.
 672         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 673
 674 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 675
 676         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 677
 678 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 679
 680         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 681         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 682
 683 2021-03-12  Alan Modra  <amodra@gmail.com>
 684
 685         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 686
 687 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-dis.c (OP_XMM): Re-order checks.
 690
 691 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-dis.c (putop): Drop need_vex check when also checking
 694         vex.evex.
 695         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 696         checking vex.b.
 697
 698 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 699
 700         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 701         checks. Move case label past broadcast check.
 702
 703 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 704
 705         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 706         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 707         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 708         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 709         EVEX_W_0F38C7_M_0_L_2): Delete.
 710         (REG_EVEX_0F38C7_M_0_L_2): New.
 711         (intel_operand_size): Handle VEX and EVEX the same for
 712         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 713         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 714         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 715         vex_vsib_q_w_d_mode uses.
 716         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 717         0F38A1, and 0F38A3 entries.
 718         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 719         entry.
 720         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 721         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 722         0F38A3 entries.
 723
 724 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 725
 726         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 727         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 728         MOD_VEX_0FXOP_09_12): Rename to ...
 729         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 730         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 731         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 732         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 733         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 734         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 735         (reg_table): Adjust comments.
 736         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 737         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 738         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 739         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 740         (vex_len_table): Adjust opcode 0A_12 entry.
 741         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 742         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 743         (rm_table): Move hreset entry.
 744
 745 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 746
 747         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 748         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 749         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 750         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 751         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 752         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 753         (get_valid_dis386): Also handle 512-bit vector length when
 754         vectoring into vex_len_table[].
 755         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 756         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 757         entries.
 758         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 759         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 760         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 761         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 762         entries.
 763
 764 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 765
 766         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 767         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 768         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 769         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 770         entries.
 771         * i386-dis-evex-len.h (evex_len_table): Likewise.
 772         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 773
 774 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 775
 776         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 777         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 778         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 779         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 780         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 781         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 782         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 783         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 784         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 785         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 786         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 787         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 788         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 789         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 790         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 791         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 792         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 793         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 794         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 795         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 796         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 797         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 798         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 799         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 800         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 801         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 802         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 803         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 804         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 805         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 806         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 807         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 808         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 809         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 810         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 811         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 812         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 813         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 814         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 815         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 816         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 817         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 818         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 819         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 820         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 821         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 822         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 823         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 824         EVEX_W_0F3A43_L_n): New.
 825         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 826         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 827         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 828         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 829         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 830         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 831         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 832         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 833         0F385B, 0F38C6, and 0F38C7 entries.
 834         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 835         0F38C6 and 0F38C7.
 836         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 837         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 838         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 839         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 840
 841 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 842
 843         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 844         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 845         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 846         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 847         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 848         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 849         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 850         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 851         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 852         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 853         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 854         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 855         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 856         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 857         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 858         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 859         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 860         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 861         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 862         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 863         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 864         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 865         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 866         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 867         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 868         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 869         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 870         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 871         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 872         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 873         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 874         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 875         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 876         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 877         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 878         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 879         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 880         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 881         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 882         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 883         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 884         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 885         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 886         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 887         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 888         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 889         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 890         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 891         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 892         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 893         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 894         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 895         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 896         VEX_W_0F99_P_2_LEN_0): Delete.
 897         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 898         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 899         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 900         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 901         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 902         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 903         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 904         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 905         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 906         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 907         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 908         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 909         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 910         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 911         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 912         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 913         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 914         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 915         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 916         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 917         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 918         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 919         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 920         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 921         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 922         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 923         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 924         (prefix_table): No longer link to vex_len_table[] for opcodes
 925         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 926         0F92, 0F93, 0F98, and 0F99.
 927         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 928         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 929         0F98, and 0F99.
 930         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 931         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 932         0F98, and 0F99.
 933         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 934         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 935         0F98, and 0F99.
 936         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 937         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 938         0F98, and 0F99.
 939
 940 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 941
 942         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 943         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 944         REG_VEX_0F73_M_0 respectively.
 945         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 946         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 947         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 948         MOD_VEX_0F73_REG_7): Delete.
 949         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 950         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 951         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 952         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 953         PREFIX_VEX_0F3AF0_L_0 respectively.
 954         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 955         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 956         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 957         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 958         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 959         VEX_LEN_0F38F7): New.
 960         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 961         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 962         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 963         0F38F3.
 964         (prefix_table): No longer link to vex_len_table[] for opcodes
 965         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 966         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 967         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 968         0F38F6, 0F38F7, and 0F3AF0.
 969         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 970         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 971         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 972         0F73.
 973
 974 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 975
 976         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 977         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 978         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 979         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 980         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 981         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 982         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 983         73.
 984         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 985         0F72, and 0F73.
 986         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 987         0F73.
 988
 989 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 990
 991         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 992         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 993         (reg_table): Don't link to mod_table[] where not needed. Add
 994         PREFIX_IGNORED to nop entries.
 995         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 996         (mod_table): Add nop entries next to prefetch ones. Drop
 997         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 998         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 999         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1000         PREFIX_OPCODE from endbr* entries.
1001         (get_valid_dis386): Also consider entry's name when zapping
1002         vindex.
1003         (print_insn): Handle PREFIX_IGNORED.
1004
1005 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1006
1007         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1008         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1009         element.
1010         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1011         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1012         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1013         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1014         (struct i386_opcode_modifier): Delete notrackprefixok,
1015         islockable, hleprefixok, and repprefixok fields. Add prefixok
1016         field.
1017         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1018         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1019         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1020         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1021         Replace HLEPrefixOk.
1022         * opcodes/i386-tbl.h: Re-generate.
1023
1024 2021-03-09  Jan Beulich  <jbeulich@suse.com>
1025
1026         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1027         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1028         64-bit form.
1029         * opcodes/i386-tbl.h: Re-generate.
1030
1031 2021-03-03  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1034         for {} instead of {0}. Don't look for '0'.
1035         * i386-opc.tbl: Drop operand count field. Drop redundant operand
1036         size specifiers.
1037
1038 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
1039
1040         PR 27158
1041         * riscv-dis.c (print_insn_args): Updated encoding macros.
1042         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1043         (match_c_addi16sp): Updated encoding macros.
1044         (match_c_lui): Likewise.
1045         (match_c_lui_with_hint): Likewise.
1046         (match_c_addi4spn): Likewise.
1047         (match_c_slli): Likewise.
1048         (match_slli_as_c_slli): Likewise.
1049         (match_c_slli64): Likewise.
1050         (match_srxi_as_c_srxi): Likewise.
1051         (riscv_insn_types): Added .insn css/cl/cs.
1052
1053 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
1054
1055         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1056         (default_priv_spec): Updated type to riscv_spec_class.
1057         (parse_riscv_dis_option): Updated.
1058         * riscv-opc.c: Moved stuff and make the file tidy.
1059
1060 2021-02-17  Alan Modra  <amodra@gmail.com>
1061
1062         * wasm32-dis.c: Include limits.h.
1063         (CHAR_BIT): Provide backup define.
1064         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1065         Correct signed overflow checking.
1066
1067 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1068
1069         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1070         * i386-tbl.h: Re-generate.
1071
1072 2021-02-16  Jan Beulich  <jbeulich@suse.com>
1073
1074         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1075         Oword.
1076         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1077
1078 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
1079
1080         * s390-mkopc.c (main): Accept arch14 as cpu string.
1081         * s390-opc.txt: Add new arch14 instructions.
1082
1083 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
1084
1085         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1086         favour of LIBINTL.
1087         * configure: Regenerated.
1088
1089 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
1090
1091         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1092         * tic54x-opc.c (regs): Rename to ...
1093         (tic54x_regs): ... this.
1094         (mmregs): Rename to ...
1095         (tic54x_mmregs): ... this.
1096         (condition_codes): Rename to ...
1097         (tic54x_condition_codes): ... this.
1098         (cc2_codes): Rename to ...
1099         (tic54x_cc2_codes): ... this.
1100         (cc3_codes): Rename to ...
1101         (tic54x_cc3_codes): ... this.
1102         (status_bits): Rename to ...
1103         (tic54x_status_bits): ... this.
1104         (misc_symbols): Rename to ...
1105         (tic54x_misc_symbols): ... this.
1106
1107 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
1108
1109         * riscv-opc.c (MASK_RVB_IMM): Removed.
1110         (riscv_opcodes): Removed zb* instructions.
1111         (riscv_ext_version_table): Removed versions for zb*.
1112
1113 2021-01-26  Alan Modra  <amodra@gmail.com>
1114
1115         * i386-gen.c (parse_template): Ensure entire template_instance
1116         is initialised.
1117
1118 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1119
1120         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1121         (riscv_fpr_names_abi): Likewise.
1122         (riscv_opcodes): Likewise.
1123         (riscv_insn_types): Likewise.
1124
1125 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1126
1127         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1128
1129 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
1130
1131         * riscv-dis.c: Comments tidy and improvement.
1132         * riscv-opc.c: Likewise.
1133
1134 2021-01-13  Alan Modra  <amodra@gmail.com>
1135
1136         * Makefile.in: Regenerate.
1137
1138 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
1139
1140         PR binutils/26792
1141         * configure.ac: Use GNU_MAKE_JOBSERVER.
1142         * aclocal.m4: Regenerated.
1143         * configure: Likewise.
1144
1145 2021-01-12  Nick Clifton  <nickc@redhat.com>
1146
1147         * po/sr.po: Updated Serbian translation.
1148
1149 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
1150
1151         PR ld/27173
1152         * configure: Regenerated.
1153
1154 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
1155
1156         * aarch64-asm-2.c: Regenerate.
1157         * aarch64-dis-2.c: Likewise.
1158         * aarch64-opc-2.c: Likewise.
1159         * aarch64-opc.c (aarch64_print_operand):
1160         Delete handling of AARCH64_OPND_CSRE_CSR.
1161         * aarch64-tbl.h (aarch64_feature_csre): Delete.
1162         (CSRE): Likewise.
1163         (_CSRE_INSN): Likewise.
1164         (aarch64_opcode_table): Delete csr.
1165
1166 2021-01-11  Nick Clifton  <nickc@redhat.com>
1167
1168         * po/de.po: Updated German translation.
1169         * po/fr.po: Updated French translation.
1170         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1171         * po/sv.po: Updated Swedish translation.
1172         * po/uk.po: Updated Ukranian translation.
1173
1174 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1175
1176         * configure: Regenerated.
1177
1178 2021-01-09  Nick Clifton  <nickc@redhat.com>
1179
1180         * configure: Regenerate.
1181         * po/opcodes.pot: Regenerate.
1182
1183 2021-01-09  Nick Clifton  <nickc@redhat.com>
1184
1185         * 2.36 release branch crated.
1186
1187 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1188
1189         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1190         (DW, (XRC_MASK): Define.
1191         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1192
1193 2021-01-09  Alan Modra  <amodra@gmail.com>
1194
1195         * configure: Regenerate.
1196
1197 2021-01-08  Nick Clifton  <nickc@redhat.com>
1198
1199         * po/sv.po: Updated Swedish translation.
1200
1201 2021-01-08  Nick Clifton  <nickc@redhat.com>
1202
1203         PR 27129
1204         * aarch64-dis.c (determine_disassembling_preference): Move call to
1205         aarch64_match_operands_constraint outside of the assertion.
1206         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1207         Replace with a return of FALSE.
1208
1209         PR 27139
1210         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1211         core system register.
1212
1213 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1214
1215         * configure: Regenerate.
1216
1217 2021-01-07  Nick Clifton  <nickc@redhat.com>
1218
1219         * po/fr.po: Updated French translation.
1220
1221 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1222
1223         * m68k-opc.c (chkl): Change minimum architecture requirement to
1224         m68020.
1225
1226 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1227
1228         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1229
1230 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1231             Jim Wilson  <jimw@sifive.com>
1232             Andrew Waterman  <andrew@sifive.com>
1233             Maxim Blinov  <maxim.blinov@embecosm.com>
1234             Kito Cheng  <kito.cheng@sifive.com>
1235             Nelson Chu  <nelson.chu@sifive.com>
1236
1237         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1238         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1239
1240 2021-01-01  Alan Modra  <amodra@gmail.com>
1241
1242         Update year range in copyright notice of all files.
1243
1244 For older changes see ChangeLog-2020
1245 \f
1246 Copyright (C) 2021-2022 Free Software Foundation, Inc.
1247
1248 Copying and distribution of this file, with or without modification,
1249 are permitted in any medium without royalty provided the copyright
1250 notice and this notice are preserved.
1251
1252 Local Variables:
1253 mode: change-log
1254 left-margin: 8
1255 fill-column: 74
1256 version-control: never
1257 End: