opcodes/ChangeLog

   1 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
   2
   3         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
   4         (print_insn_): Handle instruction endian.
   5         * bpf-dis.c: Regenerate.
   6         * bpf-desc.c: Regenerate.
   7         * epiphany-dis.c: Likewise.
   8         * epiphany-desc.c: Likewise.
   9         * fr30-dis.c: Likewise.
  10         * fr30-desc.c: Likewise.
  11         * frv-dis.c: Likewise.
  12         * frv-desc.c: Likewise.
  13         * ip2k-dis.c: Likewise.
  14         * ip2k-desc.c: Likewise.
  15         * iq2000-dis.c: Likewise.
  16         * iq2000-desc.c: Likewise.
  17         * lm32-dis.c: Likewise.
  18         * lm32-desc.c: Likewise.
  19         * m32c-dis.c: Likewise.
  20         * m32c-desc.c: Likewise.
  21         * m32r-dis.c: Likewise.
  22         * m32r-desc.c: Likewise.
  23         * mep-dis.c: Likewise.
  24         * mep-desc.c: Likewise.
  25         * mt-dis.c: Likewise.
  26         * mt-desc.c: Likewise.
  27         * or1k-dis.c: Likewise.
  28         * or1k-desc.c: Likewise.
  29         * xc16x-dis.c: Likewise.
  30         * xc16x-desc.c: Likewise.
  31         * xstormy16-dis.c: Likewise.
  32         * xstormy16-desc.c: Likewise.
  33
  34 2020-06-03  Nick Clifton  <nickc@redhat.com>
  35
  36         * po/sr.po: Updated Serbian translation.
  37
  38 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
  39
  40         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
  41         (riscv_get_priv_spec_class): Likewise.
  42
  43 2020-06-01  Alan Modra  <amodra@gmail.com>
  44
  45         * bpf-desc.c: Regenerate.
  46
  47 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
  48             David Faust <david.faust@oracle.com>
  49
  50         * bpf-desc.c: Regenerate.
  51         * bpf-opc.h: Likewise.
  52         * bpf-opc.c: Likewise.
  53         * bpf-dis.c: Likewise.
  54
  55 2020-05-28  Alan Modra  <amodra@gmail.com>
  56
  57         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
  58         values.
  59
  60 2020-05-28  Alan Modra  <amodra@gmail.com>
  61
  62         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
  63         immediates.
  64         (print_insn_ns32k): Revert last change.
  65
  66 2020-05-28  Nick Clifton  <nickc@redhat.com>
  67
  68         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
  69         static.
  70
  71 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
  72
  73         Fix extraction of signed constants in nios2 disassembler (again).
  74
  75         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
  76         extractions of signed fields.
  77
  78 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
  79
  80         * s390-opc.txt: Relocate vector load/store instructions with
  81         additional alignment parameter and change architecture level
  82         constraint from z14 to z13.
  83
  84 2020-05-21  Alan Modra  <amodra@gmail.com>
  85
  86         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
  87         * sparc-dis.c: Likewise.
  88         * tic4x-dis.c: Likewise.
  89         * xtensa-dis.c: Likewise.
  90         * bpf-desc.c: Regenerate.
  91         * epiphany-desc.c: Regenerate.
  92         * fr30-desc.c: Regenerate.
  93         * frv-desc.c: Regenerate.
  94         * ip2k-desc.c: Regenerate.
  95         * iq2000-desc.c: Regenerate.
  96         * lm32-desc.c: Regenerate.
  97         * m32c-desc.c: Regenerate.
  98         * m32r-desc.c: Regenerate.
  99         * mep-asm.c: Regenerate.
 100         * mep-desc.c: Regenerate.
 101         * mt-desc.c: Regenerate.
 102         * or1k-desc.c: Regenerate.
 103         * xc16x-desc.c: Regenerate.
 104         * xstormy16-desc.c: Regenerate.
 105
 106 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 107
 108         * riscv-opc.c (riscv_ext_version_table): The table used to store
 109         all information about the supported spec and the corresponding ISA
 110         versions.  Currently, only Zicsr is supported to verify the
 111         correctness of Z sub extension settings.  Others will be supported
 112         in the future patches.
 113         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 114         classes and the corresponding strings.
 115         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 116         spec class by giving a ISA spec string.
 117         * riscv-opc.c (struct priv_spec_t): New structure.
 118         (struct priv_spec_t priv_specs): List for all supported privilege spec
 119         classes and the corresponding strings.
 120         (riscv_get_priv_spec_class): New function.  Get the corresponding
 121         privilege spec class by giving a spec string.
 122         (riscv_get_priv_spec_name): New function.  Get the corresponding
 123         privilege spec string by giving a CSR version class.
 124         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 125         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 126         according to the chosen version.  Build a hash table riscv_csr_hash to
 127         store the valid CSR for the chosen pirv verison.  Dump the direct
 128         CSR address rather than it's name if it is invalid.
 129         (parse_riscv_dis_option_without_args): New function.  Parse the options
 130         without arguments.
 131         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 132         parse the options without arguments first, and then handle the options
 133         with arguments.  Add the new option -Mpriv-spec, which has argument.
 134         * riscv-dis.c (print_riscv_disassembler_options): Add description
 135         about the new OBJDUMP option.
 136
 137 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 138
 139         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 140         WC values on POWER10 sync, dcbf  and wait instructions.
 141         (insert_pl, extract_pl): New functions.
 142         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 143         (LS3): New , 3-bit L for sync.
 144         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 145         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 146         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 147         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 148         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 149         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 150         <wait>: Enable PL operand on POWER10.
 151         <dcbf>: Enable L3OPT operand on POWER10.
 152         <sync>: Enable SC2 operand on POWER10.
 153
 154 2020-05-19  Stafford Horne  <shorne@gmail.com>
 155
 156         PR 25184
 157         * or1k-asm.c: Regenerate.
 158         * or1k-desc.c: Regenerate.
 159         * or1k-desc.h: Regenerate.
 160         * or1k-dis.c: Regenerate.
 161         * or1k-ibld.c: Regenerate.
 162         * or1k-opc.c: Regenerate.
 163         * or1k-opc.h: Regenerate.
 164         * or1k-opinst.c: Regenerate.
 165
 166 2020-05-11  Alan Modra  <amodra@gmail.com>
 167
 168         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 169         xsmaxcqp, xsmincqp.
 170
 171 2020-05-11  Alan Modra  <amodra@gmail.com>
 172
 173         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 174         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 175
 176 2020-05-11  Alan Modra  <amodra@gmail.com>
 177
 178         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 179
 180 2020-05-11  Alan Modra  <amodra@gmail.com>
 181
 182         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 183         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 184
 185 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 186
 187         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 188         mnemonics.
 189
 190 2020-05-11  Alan Modra  <amodra@gmail.com>
 191
 192         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 193         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 194         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 195         (prefix_opcodes): Add xxeval.
 196
 197 2020-05-11  Alan Modra  <amodra@gmail.com>
 198
 199         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 200         xxgenpcvwm, xxgenpcvdm.
 201
 202 2020-05-11  Alan Modra  <amodra@gmail.com>
 203
 204         * ppc-opc.c (MP, VXVAM_MASK): Define.
 205         (VXVAPS_MASK): Use VXVA_MASK.
 206         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 207         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 208         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 209         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 210
 211 2020-05-11  Alan Modra  <amodra@gmail.com>
 212             Peter Bergner  <bergner@linux.ibm.com>
 213
 214         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 215         New functions.
 216         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 217         YMSK2, XA6a, XA6ap, XB6a entries.
 218         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 219         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 220         (PPCVSX4): Define.
 221         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 222         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 223         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 224         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 225         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 226         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 227         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 228         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 229         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 230         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 231         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 232         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 233         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 234         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 235
 236 2020-05-11  Alan Modra  <amodra@gmail.com>
 237
 238         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 239         (insert_xts, extract_xts): New functions.
 240         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 241         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 242         (VXRC_MASK, VXSH_MASK): Define.
 243         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 244         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 245         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 246         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 247         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 248         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 249         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 250
 251 2020-05-11  Alan Modra  <amodra@gmail.com>
 252
 253         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 254         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 255         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 256         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 257         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 258
 259 2020-05-11  Alan Modra  <amodra@gmail.com>
 260
 261         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 262         (XTP, DQXP, DQXP_MASK): Define.
 263         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 264         (prefix_opcodes): Add plxvp and pstxvp.
 265
 266 2020-05-11  Alan Modra  <amodra@gmail.com>
 267
 268         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 269         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 270         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 271
 272 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 273
 274         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 275
 276 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 277
 278         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 279         (L1OPT): Define.
 280         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 281
 282 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 283
 284         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 285
 286 2020-05-11  Alan Modra  <amodra@gmail.com>
 287
 288         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 289
 290 2020-05-11  Alan Modra  <amodra@gmail.com>
 291
 292         * ppc-dis.c (ppc_opts): Add "power10" entry.
 293         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 294         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 295
 296 2020-05-11  Nick Clifton  <nickc@redhat.com>
 297
 298         * po/fr.po: Updated French translation.
 299
 300 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 301
 302         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 303         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 304         (operand_general_constraint_met_p): validate
 305         AARCH64_OPND_UNDEFINED.
 306         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 307         for FLD_imm16_2.
 308         * aarch64-asm-2.c: Regenerated.
 309         * aarch64-dis-2.c: Regenerated.
 310         * aarch64-opc-2.c: Regenerated.
 311
 312 2020-04-29  Nick Clifton  <nickc@redhat.com>
 313
 314         PR 22699
 315         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 316         and SETRC insns.
 317
 318 2020-04-29  Nick Clifton  <nickc@redhat.com>
 319
 320         * po/sv.po: Updated Swedish translation.
 321
 322 2020-04-29  Nick Clifton  <nickc@redhat.com>
 323
 324         PR 22699
 325         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 326         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 327         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 328         IMM0_8U case.
 329
 330 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 331
 332         PR 25848
 333         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 334         cmpi only on m68020up and cpu32.
 335
 336 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 337
 338         * aarch64-asm.c (aarch64_ins_none): New.
 339         * aarch64-asm.h (ins_none): New declaration.
 340         * aarch64-dis.c (aarch64_ext_none): New.
 341         * aarch64-dis.h (ext_none): New declaration.
 342         * aarch64-opc.c (aarch64_print_operand): Update case for
 343         AARCH64_OPND_BARRIER_PSB.
 344         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 345         (AARCH64_OPERANDS): Update inserter/extracter for
 346         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 347         * aarch64-asm-2.c: Regenerated.
 348         * aarch64-dis-2.c: Regenerated.
 349         * aarch64-opc-2.c: Regenerated.
 350
 351 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 352
 353         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 354         (aarch64_feature_ras, RAS): Likewise.
 355         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 356         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 357         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 358         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 359         * aarch64-asm-2.c: Regenerated.
 360         * aarch64-dis-2.c: Regenerated.
 361         * aarch64-opc-2.c: Regenerated.
 362
 363 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 364
 365         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 366         (print_insn_neon): Support disassembly of conditional
 367         instructions.
 368
 369 2020-02-16  David Faust  <david.faust@oracle.com>
 370
 371         * bpf-desc.c: Regenerate.
 372         * bpf-desc.h: Likewise.
 373         * bpf-opc.c: Regenerate.
 374         * bpf-opc.h: Likewise.
 375
 376 2020-04-07  Lili Cui  <lili.cui@intel.com>
 377
 378         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 379         (prefix_table): New instructions (see prefixes above).
 380         (rm_table): Likewise
 381         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 382         CPU_ANY_TSXLDTRK_FLAGS.
 383         (cpu_flags): Add CpuTSXLDTRK.
 384         * i386-opc.h (enum): Add CpuTSXLDTRK.
 385         (i386_cpu_flags): Add cputsxldtrk.
 386         * i386-opc.tbl: Add XSUSPLDTRK insns.
 387         * i386-init.h: Regenerate.
 388         * i386-tbl.h: Likewise.
 389
 390 2020-04-02  Lili Cui  <lili.cui@intel.com>
 391
 392         * i386-dis.c (prefix_table): New instructions serialize.
 393         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 394         CPU_ANY_SERIALIZE_FLAGS.
 395         (cpu_flags): Add CpuSERIALIZE.
 396         * i386-opc.h (enum): Add CpuSERIALIZE.
 397         (i386_cpu_flags): Add cpuserialize.
 398         * i386-opc.tbl: Add SERIALIZE insns.
 399         * i386-init.h: Regenerate.
 400         * i386-tbl.h: Likewise.
 401
 402 2020-03-26  Alan Modra  <amodra@gmail.com>
 403
 404         * disassemble.h (opcodes_assert): Declare.
 405         (OPCODES_ASSERT): Define.
 406         * disassemble.c: Don't include assert.h.  Include opintl.h.
 407         (opcodes_assert): New function.
 408         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 409         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 410         calculate maxlen.  Omit insn decoding when insn length exceeds
 411         maxlen.  Exit from nibble loop when looking for E, before
 412         accessing next data byte.  Move processing of E outside loop.
 413         Replace tests of maxlen in loop with assertions.
 414
 415 2020-03-26  Alan Modra  <amodra@gmail.com>
 416
 417         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 418
 419 2020-03-25  Alan Modra  <amodra@gmail.com>
 420
 421         * z80-dis.c (suffix): Init mybuf.
 422
 423 2020-03-22  Alan Modra  <amodra@gmail.com>
 424
 425         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 426         successflly read from section.
 427
 428 2020-03-22  Alan Modra  <amodra@gmail.com>
 429
 430         * arc-dis.c (find_format): Use ISO C string concatenation rather
 431         than line continuation within a string.  Don't access needs_limm
 432         before testing opcode != NULL.
 433
 434 2020-03-22  Alan Modra  <amodra@gmail.com>
 435
 436         * ns32k-dis.c (print_insn_arg): Update comment.
 437         (print_insn_ns32k): Reduce size of index_offset array, and
 438         initialize, passing -1 to print_insn_arg for args that are not
 439         an index.  Don't exit arg loop early.  Abort on bad arg number.
 440
 441 2020-03-22  Alan Modra  <amodra@gmail.com>
 442
 443         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 444         * s12z-opc.c: Formatting.
 445         (operands_f): Return an int.
 446         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 447         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 448         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 449         (exg_sex_discrim): Likewise.
 450         (create_immediate_operand, create_bitfield_operand),
 451         (create_register_operand_with_size, create_register_all_operand),
 452         (create_register_all16_operand, create_simple_memory_operand),
 453         (create_memory_operand, create_memory_auto_operand): Don't
 454         segfault on malloc failure.
 455         (z_ext24_decode): Return an int status, negative on fail, zero
 456         on success.
 457         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 458         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 459         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 460         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 461         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 462         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 463         (loop_primitive_decode, shift_decode, psh_pul_decode),
 464         (bit_field_decode): Similarly.
 465         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 466         to return value, update callers.
 467         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 468         Don't segfault on NULL operand.
 469         (decode_operation): Return OP_INVALID on first fail.
 470         (decode_s12z): Check all reads, returning -1 on fail.
 471
 472 2020-03-20  Alan Modra  <amodra@gmail.com>
 473
 474         * metag-dis.c (print_insn_metag): Don't ignore status from
 475         read_memory_func.
 476
 477 2020-03-20  Alan Modra  <amodra@gmail.com>
 478
 479         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 480         Initialize parts of buffer not written when handling a possible
 481         2-byte insn at end of section.  Don't attempt decoding of such
 482         an insn by the 4-byte machinery.
 483
 484 2020-03-20  Alan Modra  <amodra@gmail.com>
 485
 486         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 487         partially filled buffer.  Prevent lookup of 4-byte insns when
 488         only VLE 2-byte insns are possible due to section size.  Print
 489         ".word" rather than ".long" for 2-byte leftovers.
 490
 491 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 492
 493         PR 25641
 494         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 495
 496 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 497
 498         * i386-dis.c (X86_64_0D): Rename to ...
 499         (X86_64_0E): ... this.
 500
 501 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 502
 503         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 504         * Makefile.in: Regenerated.
 505
 506 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 509         3-operand pseudos.
 510         * i386-tbl.h: Re-generate.
 511
 512 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 515         vprot*, vpsha*, and vpshl*.
 516         * i386-tbl.h: Re-generate.
 517
 518 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 521         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 522         * i386-tbl.h: Re-generate.
 523
 524 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 527         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 528         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 529         * i386-tbl.h: Re-generate.
 530
 531 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 532
 533         * i386-gen.c (struct template_arg, struct template_instance,
 534         struct template_param, struct template, templates,
 535         parse_template, expand_templates): New.
 536         (process_i386_opcodes): Various local variables moved to
 537         expand_templates. Call parse_template and expand_templates.
 538         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 539         * i386-tbl.h: Re-generate.
 540
 541 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 544         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 545         register and memory source templates. Replace VexW= by VexW*
 546         where applicable.
 547         * i386-tbl.h: Re-generate.
 548
 549 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 552         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 553         * i386-tbl.h: Re-generate.
 554
 555 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 556
 557         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 558         * i386-tbl.h: Re-generate.
 559
 560 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 561
 562         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 563         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 564         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 565         VexW0 on SSE2AVX variants.
 566         (vmovq): Drop NoRex64 from XMM/XMM variants.
 567         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 568         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 569         applicable use VexW0.
 570         * i386-tbl.h: Re-generate.
 571
 572 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 573
 574         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 575         * i386-opc.h (Rex64): Delete.
 576         (struct i386_opcode_modifier): Remove rex64 field.
 577         * i386-opc.tbl (crc32): Drop Rex64.
 578         Replace Rex64 with Size64 everywhere else.
 579         * i386-tbl.h: Re-generate.
 580
 581 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 582
 583         * i386-dis.c (OP_E_memory): Exclude recording of used address
 584         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 585         addressed memory operands for MPX insns.
 586
 587 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 588
 589         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 590         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 591         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 592         (ptwrite): Split into non-64-bit and 64-bit forms.
 593         * i386-tbl.h: Re-generate.
 594
 595 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 596
 597         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 598         template.
 599         * i386-tbl.h: Re-generate.
 600
 601 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 602
 603         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 604         (prefix_table): Move vmmcall here. Add vmgexit.
 605         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 606         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 607         (cpu_flags): Add CpuSEV_ES entry.
 608         * i386-opc.h (CpuSEV_ES): New.
 609         (union i386_cpu_flags): Add cpusev_es field.
 610         * i386-opc.tbl (vmgexit): New.
 611         * i386-init.h, i386-tbl.h: Re-generate.
 612
 613 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 614
 615         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 616         with MnemonicSize.
 617         * i386-opc.h (IGNORESIZE): New.
 618         (DEFAULTSIZE): Likewise.
 619         (IgnoreSize): Removed.
 620         (DefaultSize): Likewise.
 621         (MnemonicSize): New.
 622         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 623         mnemonicsize.
 624         * i386-opc.tbl (IgnoreSize): New.
 625         (DefaultSize): Likewise.
 626         * i386-tbl.h: Regenerated.
 627
 628 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 629
 630         PR 25627
 631         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 632         instructions.
 633
 634 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         PR gas/25622
 637         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 638         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 639         * i386-tbl.h: Regenerated.
 640
 641 2020-02-26  Alan Modra  <amodra@gmail.com>
 642
 643         * aarch64-asm.c: Indent labels correctly.
 644         * aarch64-dis.c: Likewise.
 645         * aarch64-gen.c: Likewise.
 646         * aarch64-opc.c: Likewise.
 647         * alpha-dis.c: Likewise.
 648         * i386-dis.c: Likewise.
 649         * nds32-asm.c: Likewise.
 650         * nfp-dis.c: Likewise.
 651         * visium-dis.c: Likewise.
 652
 653 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 654
 655         * arc-regs.h (int_vector_base): Make it available for all ARC
 656         CPUs.
 657
 658 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 659
 660         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 661         changed.
 662
 663 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 664
 665         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 666         c.mv/c.li if rs1 is zero.
 667
 668 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 671         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 672         CPU_POPCNT_FLAGS.
 673         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 674         * i386-opc.h (CpuABM): Removed.
 675         (CpuPOPCNT): New.
 676         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 677         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 678         popcnt.  Remove CpuABM from lzcnt.
 679         * i386-init.h: Regenerated.
 680         * i386-tbl.h: Likewise.
 681
 682 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 683
 684         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 685         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 686         VexW1 instead of open-coding them.
 687         * i386-tbl.h: Re-generate.
 688
 689 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-opc.tbl (AddrPrefixOpReg): Define.
 692         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 693         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 694         templates. Drop NoRex64.
 695         * i386-tbl.h: Re-generate.
 696
 697 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 698
 699         PR gas/6518
 700         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 701         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 702         into Intel syntax instance (with Unpsecified) and AT&T one
 703         (without).
 704         (vcvtneps2bf16): Likewise, along with folding the two so far
 705         separate ones.
 706         * i386-tbl.h: Re-generate.
 707
 708 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 709
 710         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 711         CPU_ANY_SSE4A_FLAGS.
 712
 713 2020-02-17  Alan Modra  <amodra@gmail.com>
 714
 715         * i386-gen.c (cpu_flag_init): Correct last change.
 716
 717 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 718
 719         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 720         CPU_ANY_SSE4_FLAGS.
 721
 722 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 723
 724         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 725         (movzx): Likewise.
 726
 727 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 728
 729         PR gas/25438
 730         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 731         destination for Cpu64-only variant.
 732         (movzx): Fold patterns.
 733         * i386-tbl.h: Re-generate.
 734
 735 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 736
 737         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 738         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 739         CPU_ANY_SSE4_FLAGS entry.
 740         * i386-init.h: Re-generate.
 741
 742 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 745         with Unspecified, making the present one AT&T syntax only.
 746         * i386-tbl.h: Re-generate.
 747
 748 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 751         * i386-tbl.h: Re-generate.
 752
 753 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 754
 755         PR gas/24546
 756         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 757         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 758         Amd64 and Intel64 templates.
 759         (call, jmp): Likewise for far indirect variants. Dro
 760         Unspecified.
 761         * i386-tbl.h: Re-generate.
 762
 763 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 764
 765         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 766         * i386-opc.h (ShortForm): Delete.
 767         (struct i386_opcode_modifier): Remove shortform field.
 768         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 769         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 770         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 771         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 772         Drop ShortForm.
 773         * i386-tbl.h: Re-generate.
 774
 775 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 778         fucompi): Drop ShortForm from operand-less templates.
 779         * i386-tbl.h: Re-generate.
 780
 781 2020-02-11  Alan Modra  <amodra@gmail.com>
 782
 783         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 784         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 785         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 786         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 787         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 788
 789 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 790
 791         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 792         (cde_opcodes): Add VCX* instructions.
 793
 794 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 795             Matthew Malcomson  <matthew.malcomson@arm.com>
 796
 797         * arm-dis.c (struct cdeopcode32): New.
 798         (CDE_OPCODE): New macro.
 799         (cde_opcodes): New disassembly table.
 800         (regnames): New option to table.
 801         (cde_coprocs): New global variable.
 802         (print_insn_cde): New
 803         (print_insn_thumb32): Use print_insn_cde.
 804         (parse_arm_disassembler_options): Parse coprocN args.
 805
 806 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 807
 808         PR gas/25516
 809         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 810         with ISA64.
 811         * i386-opc.h (AMD64): Removed.
 812         (Intel64): Likewose.
 813         (AMD64): New.
 814         (INTEL64): Likewise.
 815         (INTEL64ONLY): Likewise.
 816         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 817         * i386-opc.tbl (Amd64): New.
 818         (Intel64): Likewise.
 819         (Intel64Only): Likewise.
 820         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 821         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 822         * i386-tbl.h: Regenerated.
 823
 824 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 825
 826         PR 25469
 827         * z80-dis.c: Add support for GBZ80 opcodes.
 828
 829 2020-02-04  Alan Modra  <amodra@gmail.com>
 830
 831         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 832
 833 2020-02-03  Alan Modra  <amodra@gmail.com>
 834
 835         * m32c-ibld.c: Regenerate.
 836
 837 2020-02-01  Alan Modra  <amodra@gmail.com>
 838
 839         * frv-ibld.c: Regenerate.
 840
 841 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 842
 843         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 844         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 845         (OP_E_memory): Replace xmm_mdq_mode case label by
 846         vex_scalar_w_dq_mode one.
 847         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 848
 849 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 850
 851         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 852         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 853         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 854         (intel_operand_size): Drop vex_w_dq_mode case label.
 855
 856 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 857
 858         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 859         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 860
 861 2020-01-30  Alan Modra  <amodra@gmail.com>
 862
 863         * m32c-ibld.c: Regenerate.
 864
 865 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 866
 867         * bpf-opc.c: Regenerate.
 868
 869 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 870
 871         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 872         (dis386): Use them to replace C2/C3 table entries.
 873         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 874         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 875         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 876         * i386-tbl.h: Re-generate.
 877
 878 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 881         forms.
 882         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 883         DefaultSize.
 884         * i386-tbl.h: Re-generate.
 885
 886 2020-01-30  Alan Modra  <amodra@gmail.com>
 887
 888         * tic4x-dis.c (tic4x_dp): Make unsigned.
 889
 890 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 891             Jan Beulich  <jbeulich@suse.com>
 892
 893         PR binutils/25445
 894         * i386-dis.c (MOVSXD_Fixup): New function.
 895         (movsxd_mode): New enum.
 896         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 897         (intel_operand_size): Handle movsxd_mode.
 898         (OP_E_register): Likewise.
 899         (OP_G): Likewise.
 900         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 901         register on movsxd.  Add movsxd with 16-bit destination register
 902         for AMD64 and Intel64 ISAs.
 903         * i386-tbl.h: Regenerated.
 904
 905 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 906
 907         PR 25403
 908         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 909         * aarch64-asm-2.c: Regenerate
 910         * aarch64-dis-2.c: Likewise.
 911         * aarch64-opc-2.c: Likewise.
 912
 913 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-opc.tbl (sysret): Drop DefaultSize.
 916         * i386-tbl.h: Re-generate.
 917
 918 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 921         Dword.
 922         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 923         * i386-tbl.h: Re-generate.
 924
 925 2020-01-20  Nick Clifton  <nickc@redhat.com>
 926
 927         * po/de.po: Updated German translation.
 928         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 929         * po/uk.po: Updated Ukranian translation.
 930
 931 2020-01-20  Alan Modra  <amodra@gmail.com>
 932
 933         * hppa-dis.c (fput_const): Remove useless cast.
 934
 935 2020-01-20  Alan Modra  <amodra@gmail.com>
 936
 937         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 938
 939 2020-01-18  Nick Clifton  <nickc@redhat.com>
 940
 941         * configure: Regenerate.
 942         * po/opcodes.pot: Regenerate.
 943
 944 2020-01-18  Nick Clifton  <nickc@redhat.com>
 945
 946         Binutils 2.34 branch created.
 947
 948 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 949
 950         * opintl.h: Fix spelling error (seperate).
 951
 952 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 953
 954         * i386-opc.tbl: Add {vex} pseudo prefix.
 955         * i386-tbl.h: Regenerated.
 956
 957 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 958
 959         PR 25376
 960         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 961         (neon_opcodes): Likewise.
 962         (select_arm_features): Make sure we enable MVE bits when selecting
 963         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 964         any architecture.
 965
 966 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 967
 968         * i386-opc.tbl: Drop stale comment from XOP section.
 969
 970 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 973         (extractps): Add VexWIG to SSE2AVX forms.
 974         * i386-tbl.h: Re-generate.
 975
 976 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 979         Size64 from and use VexW1 on SSE2AVX forms.
 980         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 981         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 982         * i386-tbl.h: Re-generate.
 983
 984 2020-01-15  Alan Modra  <amodra@gmail.com>
 985
 986         * tic4x-dis.c (tic4x_version): Make unsigned long.
 987         (optab, optab_special, registernames): New file scope vars.
 988         (tic4x_print_register): Set up registernames rather than
 989         malloc'd registertable.
 990         (tic4x_disassemble): Delete optable and optable_special.  Use
 991         optab and optab_special instead.  Throw away old optab,
 992         optab_special and registernames when info->mach changes.
 993
 994 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 995
 996         PR 25377
 997         * z80-dis.c (suffix): Use .db instruction to generate double
 998         prefix.
 999
1000 2020-01-14  Alan Modra  <amodra@gmail.com>
1001
1002         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1003         values to unsigned before shifting.
1004
1005 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1006
1007         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1008         flow instructions.
1009         (print_insn_thumb16, print_insn_thumb32): Likewise.
1010         (print_insn): Initialize the insn info.
1011         * i386-dis.c (print_insn): Initialize the insn info fields, and
1012         detect jumps.
1013
1014 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1015
1016         * arc-opc.c (C_NE): Make it required.
1017
1018 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1019
1020         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1021         reserved register name.
1022
1023 2020-01-13  Alan Modra  <amodra@gmail.com>
1024
1025         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1026         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1027
1028 2020-01-13  Alan Modra  <amodra@gmail.com>
1029
1030         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1031         result of wasm_read_leb128 in a uint64_t and check that bits
1032         are not lost when copying to other locals.  Use uint32_t for
1033         most locals.  Use PRId64 when printing int64_t.
1034
1035 2020-01-13  Alan Modra  <amodra@gmail.com>
1036
1037         * score-dis.c: Formatting.
1038         * score7-dis.c: Formatting.
1039
1040 2020-01-13  Alan Modra  <amodra@gmail.com>
1041
1042         * score-dis.c (print_insn_score48): Use unsigned variables for
1043         unsigned values.  Don't left shift negative values.
1044         (print_insn_score32): Likewise.
1045         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1046
1047 2020-01-13  Alan Modra  <amodra@gmail.com>
1048
1049         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1050
1051 2020-01-13  Alan Modra  <amodra@gmail.com>
1052
1053         * fr30-ibld.c: Regenerate.
1054
1055 2020-01-13  Alan Modra  <amodra@gmail.com>
1056
1057         * xgate-dis.c (print_insn): Don't left shift signed value.
1058         (ripBits): Formatting, use 1u.
1059
1060 2020-01-10  Alan Modra  <amodra@gmail.com>
1061
1062         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1063         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1064
1065 2020-01-10  Alan Modra  <amodra@gmail.com>
1066
1067         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1068         and XRREG value earlier to avoid a shift with negative exponent.
1069         * m10200-dis.c (disassemble): Similarly.
1070
1071 2020-01-09  Nick Clifton  <nickc@redhat.com>
1072
1073         PR 25224
1074         * z80-dis.c (ld_ii_ii): Use correct cast.
1075
1076 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1077
1078         PR 25224
1079         * z80-dis.c (ld_ii_ii): Use character constant when checking
1080         opcode byte value.
1081
1082 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1083
1084         * i386-dis.c (SEP_Fixup): New.
1085         (SEP): Define.
1086         (dis386_twobyte): Use it for sysenter/sysexit.
1087         (enum x86_64_isa): Change amd64 enumerator to value 1.
1088         (OP_J): Compare isa64 against intel64 instead of amd64.
1089         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1090         forms.
1091         * i386-tbl.h: Re-generate.
1092
1093 2020-01-08  Alan Modra  <amodra@gmail.com>
1094
1095         * z8k-dis.c: Include libiberty.h
1096         (instr_data_s): Make max_fetched unsigned.
1097         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1098         Don't exceed byte_info bounds.
1099         (output_instr): Make num_bytes unsigned.
1100         (unpack_instr): Likewise for nibl_count and loop.
1101         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1102         idx unsigned.
1103         * z8k-opc.h: Regenerate.
1104
1105 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1106
1107         * arc-tbl.h (llock): Use 'LLOCK' as class.
1108         (llockd): Likewise.
1109         (scond): Use 'SCOND' as class.
1110         (scondd): Likewise.
1111         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1112         (scondd): Likewise.
1113
1114 2020-01-06  Alan Modra  <amodra@gmail.com>
1115
1116         * m32c-ibld.c: Regenerate.
1117
1118 2020-01-06  Alan Modra  <amodra@gmail.com>
1119
1120         PR 25344
1121         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1122         Peek at next byte to prevent recursion on repeated prefix bytes.
1123         Ensure uninitialised "mybuf" is not accessed.
1124         (print_insn_z80): Don't zero n_fetch and n_used here,..
1125         (print_insn_z80_buf): ..do it here instead.
1126
1127 2020-01-04  Alan Modra  <amodra@gmail.com>
1128
1129         * m32r-ibld.c: Regenerate.
1130
1131 2020-01-04  Alan Modra  <amodra@gmail.com>
1132
1133         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1134
1135 2020-01-04  Alan Modra  <amodra@gmail.com>
1136
1137         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1138
1139 2020-01-04  Alan Modra  <amodra@gmail.com>
1140
1141         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1142
1143 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1144
1145         * aarch64-tbl.h (aarch64_opcode_table): Use
1146         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1147
1148 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1149
1150         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1151         forms of SUDOT and USDOT.
1152
1153 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1154
1155         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1156         uzip{1,2}.
1157         * opcodes/aarch64-dis-2.c: Re-generate.
1158
1159 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1160
1161         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1162         FMMLA encoding.
1163         * opcodes/aarch64-dis-2.c: Re-generate.
1164
1165 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1166
1167         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1168
1169 2020-01-01  Alan Modra  <amodra@gmail.com>
1170
1171         Update year range in copyright notice of all files.
1172
1173 For older changes see ChangeLog-2019
1174 \f
1175 Copyright (C) 2020 Free Software Foundation, Inc.
1176
1177 Copying and distribution of this file, with or without modification,
1178 are permitted in any medium without royalty provided the copyright
1179 notice and this notice are preserved.
1180
1181 Local Variables:
1182 mode: change-log
1183 left-margin: 8
1184 fill-column: 74
1185 version-control: never
1186 End: