opcodes/ChangeLog

   1 2021-03-10  Jan Beulich  <jbeulich@suse.com>
   2
   3         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
   4         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
   5         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
   6         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
   7         EVEX_W_0F38C7_M_0_L_2): Delete.
   8         (REG_EVEX_0F38C7_M_0_L_2): New.
   9         (intel_operand_size): Handle VEX and EVEX the same for
  10         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
  11         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
  12         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
  13         vex_vsib_q_w_d_mode uses.
  14         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
  15         0F38A1, and 0F38A3 entries.
  16         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
  17         entry.
  18         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
  19         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
  20         0F38A3 entries.
  21
  22 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  23
  24         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
  25         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
  26         MOD_VEX_0FXOP_09_12): Rename to ...
  27         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
  28         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
  29         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
  30         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
  31         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
  32         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
  33         (reg_table): Adjust comments.
  34         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
  35         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
  36         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
  37         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
  38         (vex_len_table): Adjust opcode 0A_12 entry.
  39         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
  40         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
  41         (rm_table): Move hreset entry.
  42
  43 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  44
  45         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
  46         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
  47         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
  48         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
  49         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
  50         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
  51         (get_valid_dis386): Also handle 512-bit vector length when
  52         vectoring into vex_len_table[].
  53         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
  54         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
  55         entries.
  56         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
  57         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
  58         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
  59         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
  60         entries.
  61
  62 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  63
  64         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
  65         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
  66         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
  67         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
  68         entries.
  69         * i386-dis-evex-len.h (evex_len_table): Likewise.
  70         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
  71
  72 2021-03-10  Jan Beulich  <jbeulich@suse.com>
  73
  74         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
  75         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
  76         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
  77         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
  78         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
  79         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
  80         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
  81         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
  82         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
  83         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
  84         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
  85         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
  86         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
  87         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
  88         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
  89         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
  90         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
  91         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
  92         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
  93         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
  94         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
  95         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
  96         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
  97         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
  98         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
  99         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 100         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 101         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 102         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 103         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 104         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 105         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 106         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 107         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 108         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 109         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 110         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 111         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 112         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 113         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 114         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 115         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 116         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 117         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 118         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 119         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 120         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 121         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 122         EVEX_W_0F3A43_L_n): New.
 123         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 124         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 125         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 126         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 127         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 128         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 129         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 130         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 131         0F385B, 0F38C6, and 0F38C7 entries.
 132         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 133         0F38C6 and 0F38C7.
 134         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 135         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 136         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 137         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 138
 139 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 140
 141         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 142         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 143         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 144         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 145         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 146         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 147         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 148         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 149         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 150         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 151         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 152         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 153         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 154         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 155         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 156         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 157         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 158         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 159         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 160         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 161         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 162         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 163         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 164         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 165         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 166         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 167         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 168         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 169         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 170         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 171         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 172         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 173         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 174         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 175         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 176         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 177         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 178         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 179         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 180         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 181         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 182         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 183         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 184         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 185         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 186         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 187         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 188         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 189         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 190         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 191         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 192         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 193         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 194         VEX_W_0F99_P_2_LEN_0): Delete.
 195         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 196         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 197         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 198         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 199         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 200         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 201         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 202         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 203         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 204         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 205         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 206         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 207         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 208         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 209         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 210         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 211         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 212         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 213         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 214         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 215         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 216         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 217         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 218         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 219         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 220         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 221         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 222         (prefix_table): No longer link to vex_len_table[] for opcodes
 223         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 224         0F92, 0F93, 0F98, and 0F99.
 225         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 226         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 227         0F98, and 0F99.
 228         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 229         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 230         0F98, and 0F99.
 231         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 232         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 233         0F98, and 0F99.
 234         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 235         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 236         0F98, and 0F99.
 237
 238 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 239
 240         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 241         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 242         REG_VEX_0F73_M_0 respectively.
 243         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 244         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 245         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 246         MOD_VEX_0F73_REG_7): Delete.
 247         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 248         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 249         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 250         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 251         PREFIX_VEX_0F3AF0_L_0 respectively.
 252         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 253         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 254         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 255         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 256         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 257         VEX_LEN_0F38F7): New.
 258         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 259         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 260         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 261         0F38F3.
 262         (prefix_table): No longer link to vex_len_table[] for opcodes
 263         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 264         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 265         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 266         0F38F6, 0F38F7, and 0F3AF0.
 267         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 268         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 269         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 270         0F73.
 271
 272 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 273
 274         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 275         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 276         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 277         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 278         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 279         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 280         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 281         73.
 282         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 283         0F72, and 0F73.
 284         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 285         0F73.
 286
 287 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 288
 289         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 290         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 291         (reg_table): Don't link to mod_table[] where not needed. Add
 292         PREFIX_IGNORED to nop entries.
 293         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 294         (mod_table): Add nop entries next to prefetch ones. Drop
 295         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 296         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 297         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 298         PREFIX_OPCODE from endbr* entries.
 299         (get_valid_dis386): Also consider entry's name when zapping
 300         vindex.
 301         (print_insn): Handle PREFIX_IGNORED.
 302
 303 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 304
 305         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 306         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 307         element.
 308         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 309         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 310         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 311         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 312         (struct i386_opcode_modifier): Delete notrackprefixok,
 313         islockable, hleprefixok, and repprefixok fields. Add prefixok
 314         field.
 315         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 316         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 317         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 318         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 319         Replace HLEPrefixOk.
 320         * opcodes/i386-tbl.h: Re-generate.
 321
 322 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 323
 324         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 325         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 326         64-bit form.
 327         * opcodes/i386-tbl.h: Re-generate.
 328
 329 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 332         for {} instead of {0}. Don't look for '0'.
 333         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 334         size specifiers.
 335
 336 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 337
 338         PR 27158
 339         * riscv-dis.c (print_insn_args): Updated encoding macros.
 340         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 341         (match_c_addi16sp): Updated encoding macros.
 342         (match_c_lui): Likewise.
 343         (match_c_lui_with_hint): Likewise.
 344         (match_c_addi4spn): Likewise.
 345         (match_c_slli): Likewise.
 346         (match_slli_as_c_slli): Likewise.
 347         (match_c_slli64): Likewise.
 348         (match_srxi_as_c_srxi): Likewise.
 349         (riscv_insn_types): Added .insn css/cl/cs.
 350
 351 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 352
 353         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 354         (default_priv_spec): Updated type to riscv_spec_class.
 355         (parse_riscv_dis_option): Updated.
 356         * riscv-opc.c: Moved stuff and make the file tidy.
 357
 358 2021-02-17  Alan Modra  <amodra@gmail.com>
 359
 360         * wasm32-dis.c: Include limits.h.
 361         (CHAR_BIT): Provide backup define.
 362         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 363         Correct signed overflow checking.
 364
 365 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 368         * i386-tbl.h: Re-generate.
 369
 370 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 373         Oword.
 374         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 375
 376 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 377
 378         * s390-mkopc.c (main): Accept arch14 as cpu string.
 379         * s390-opc.txt: Add new arch14 instructions.
 380
 381 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 382
 383         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 384         favour of LIBINTL.
 385         * configure: Regenerated.
 386
 387 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 388
 389         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 390         * tic54x-opc.c (regs): Rename to ...
 391         (tic54x_regs): ... this.
 392         (mmregs): Rename to ...
 393         (tic54x_mmregs): ... this.
 394         (condition_codes): Rename to ...
 395         (tic54x_condition_codes): ... this.
 396         (cc2_codes): Rename to ...
 397         (tic54x_cc2_codes): ... this.
 398         (cc3_codes): Rename to ...
 399         (tic54x_cc3_codes): ... this.
 400         (status_bits): Rename to ...
 401         (tic54x_status_bits): ... this.
 402         (misc_symbols): Rename to ...
 403         (tic54x_misc_symbols): ... this.
 404
 405 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 406
 407         * riscv-opc.c (MASK_RVB_IMM): Removed.
 408         (riscv_opcodes): Removed zb* instructions.
 409         (riscv_ext_version_table): Removed versions for zb*.
 410
 411 2021-01-26  Alan Modra  <amodra@gmail.com>
 412
 413         * i386-gen.c (parse_template): Ensure entire template_instance
 414         is initialised.
 415
 416 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 417
 418         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 419         (riscv_fpr_names_abi): Likewise.
 420         (riscv_opcodes): Likewise.
 421         (riscv_insn_types): Likewise.
 422
 423 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 424
 425         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 426
 427 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 428
 429         * riscv-dis.c: Comments tidy and improvement.
 430         * riscv-opc.c: Likewise.
 431
 432 2021-01-13  Alan Modra  <amodra@gmail.com>
 433
 434         * Makefile.in: Regenerate.
 435
 436 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 437
 438         PR binutils/26792
 439         * configure.ac: Use GNU_MAKE_JOBSERVER.
 440         * aclocal.m4: Regenerated.
 441         * configure: Likewise.
 442
 443 2021-01-12  Nick Clifton  <nickc@redhat.com>
 444
 445         * po/sr.po: Updated Serbian translation.
 446
 447 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         PR ld/27173
 450         * configure: Regenerated.
 451
 452 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 453
 454         * aarch64-asm-2.c: Regenerate.
 455         * aarch64-dis-2.c: Likewise.
 456         * aarch64-opc-2.c: Likewise.
 457         * aarch64-opc.c (aarch64_print_operand):
 458         Delete handling of AARCH64_OPND_CSRE_CSR.
 459         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 460         (CSRE): Likewise.
 461         (_CSRE_INSN): Likewise.
 462         (aarch64_opcode_table): Delete csr.
 463
 464 2021-01-11  Nick Clifton  <nickc@redhat.com>
 465
 466         * po/de.po: Updated German translation.
 467         * po/fr.po: Updated French translation.
 468         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 469         * po/sv.po: Updated Swedish translation.
 470         * po/uk.po: Updated Ukranian translation.
 471
 472 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 473
 474         * configure: Regenerated.
 475
 476 2021-01-09  Nick Clifton  <nickc@redhat.com>
 477
 478         * configure: Regenerate.
 479         * po/opcodes.pot: Regenerate.
 480
 481 2021-01-09  Nick Clifton  <nickc@redhat.com>
 482
 483         * 2.36 release branch crated.
 484
 485 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 486
 487         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 488         (DW, (XRC_MASK): Define.
 489         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 490
 491 2021-01-09  Alan Modra  <amodra@gmail.com>
 492
 493         * configure: Regenerate.
 494
 495 2021-01-08  Nick Clifton  <nickc@redhat.com>
 496
 497         * po/sv.po: Updated Swedish translation.
 498
 499 2021-01-08  Nick Clifton  <nickc@redhat.com>
 500
 501         PR 27129
 502         * aarch64-dis.c (determine_disassembling_preference): Move call to
 503         aarch64_match_operands_constraint outside of the assertion.
 504         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 505         Replace with a return of FALSE.
 506
 507         PR 27139
 508         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 509         core system register.
 510
 511 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 512
 513         * configure: Regenerate.
 514
 515 2021-01-07  Nick Clifton  <nickc@redhat.com>
 516
 517         * po/fr.po: Updated French translation.
 518
 519 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 520
 521         * m68k-opc.c (chkl): Change minimum architecture requirement to
 522         m68020.
 523
 524 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 525
 526         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 527
 528 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 529             Jim Wilson  <jimw@sifive.com>
 530             Andrew Waterman  <andrew@sifive.com>
 531             Maxim Blinov  <maxim.blinov@embecosm.com>
 532             Kito Cheng  <kito.cheng@sifive.com>
 533             Nelson Chu  <nelson.chu@sifive.com>
 534
 535         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 536         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 537
 538 2021-01-01  Alan Modra  <amodra@gmail.com>
 539
 540         Update year range in copyright notice of all files.
 541
 542 For older changes see ChangeLog-2020
 543 \f
 544 Copyright (C) 2021 Free Software Foundation, Inc.
 545
 546 Copying and distribution of this file, with or without modification,
 547 are permitted in any medium without royalty provided the copyright
 548 notice and this notice are preserved.
 549
 550 Local Variables:
 551 mode: change-log
 552 left-margin: 8
 553 fill-column: 74
 554 version-control: never
 555 End: