opcodes/ChangeLog

   1 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
   2
   3         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
   4         * Makefile.in: Regenerated.
   5         * configure.ac: Add C-SKY.
   6         * configure: Regenerated.
   7         * csky-dis.c: New file.
   8         * csky-opc.h: New file.
   9         * disassemble.c (ARCH_csky): Define.
  10         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
  11         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
  12
  13 2018-07-27  Alan Modra  <amodra@gmail.com>
  14
  15         * ppc-opc.c (insert_sprbat): Correct function parameter and
  16         return type.
  17         (extract_sprbat): Likewise, variable too.
  18
  19 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
  20             Alan Modra  <amodra@gmail.com>
  21
  22         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
  23         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
  24         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
  25         support disjointed BAT.
  26         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
  27         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
  28         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
  29
  30 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
  31             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  32
  33         * i386-gen.c (adjust_broadcast_modifier): New function.
  34         (process_i386_opcode_modifier): Add an argument for operands.
  35         Adjust the Broadcast value based on operands.
  36         (output_i386_opcode): Pass operand_types to
  37         process_i386_opcode_modifier.
  38         (process_i386_opcodes): Pass NULL as operands to
  39         process_i386_opcode_modifier.
  40         * i386-opc.h (BYTE_BROADCAST): New.
  41         (WORD_BROADCAST): Likewise.
  42         (DWORD_BROADCAST): Likewise.
  43         (QWORD_BROADCAST): Likewise.
  44         (i386_opcode_modifier): Expand broadcast to 3 bits.
  45         * i386-tbl.h: Regenerated.
  46
  47 2018-07-24  Alan Modra  <amodra@gmail.com>
  48
  49         PR 23430
  50         * or1k-desc.h: Regenerate.
  51
  52 2018-07-24  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
  55         vcvtusi2ss, and vcvtusi2sd.
  56         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
  57         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
  58         * i386-tbl.h: Re-generate.
  59
  60 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
  61
  62         * arc-opc.c (extract_w6): Fix extending the sign.
  63
  64 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
  65
  66         * arc-tbl.h (vewt): Allow it for ARC EM family.
  67
  68 2018-07-23  Alan Modra  <amodra@gmail.com>
  69
  70         PR 23419
  71         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
  72         opcode variants for mtspr/mfspr encodings.
  73
  74 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
  75             Maciej W. Rozycki  <macro@mips.com>
  76
  77         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
  78         loongson3a descriptors.
  79         (parse_mips_ase_option): Handle -M loongson-mmi option.
  80         (print_mips_disassembler_options): Document -M loongson-mmi.
  81         * mips-opc.c (LMMI): New macro.
  82         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
  83         instructions.
  84
  85 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  88         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
  89         IgnoreSize and [XYZ]MMword where applicable.
  90         * i386-tbl.h: Re-generate.
  91
  92 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
  95         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
  96         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
  97         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
  98         * i386-tbl.h: Re-generate.
  99
 100 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
 103         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
 104         VPCLMULQDQ templates into their respective AVX512VL counterparts
 105         where possible, using Disp8ShiftVL and CheckRegSize instead of
 106         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
 107         * i386-tbl.h: Re-generate.
 108
 109 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 110
 111         * i386-opc.tbl: Fold AVX512DQ templates into their respective
 112         AVX512VL counterparts where possible, using Disp8ShiftVL and
 113         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 114         IgnoreSize) as appropriate.
 115         * i386-tbl.h: Re-generate.
 116
 117 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-opc.tbl: Fold AVX512BW templates into their respective
 120         AVX512VL counterparts where possible, using Disp8ShiftVL and
 121         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 122         IgnoreSize) as appropriate.
 123         * i386-tbl.h: Re-generate.
 124
 125 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-opc.tbl: Fold AVX512CD templates into their respective
 128         AVX512VL counterparts where possible, using Disp8ShiftVL and
 129         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 130         IgnoreSize) as appropriate.
 131         * i386-tbl.h: Re-generate.
 132
 133 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-opc.h (DISP8_SHIFT_VL): New.
 136         * i386-opc.tbl (Disp8ShiftVL):  Define.
 137         (various): Fold AVX512VL templates into their respective
 138         AVX512F counterparts where possible, using Disp8ShiftVL and
 139         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 140         IgnoreSize) as appropriate.
 141         * i386-tbl.h: Re-generate.
 142
 143 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 144
 145         * Makefile.am: Change dependencies and rule for
 146         $(srcdir)/i386-init.h.
 147         * Makefile.in: Re-generate.
 148         * i386-gen.c (process_i386_opcodes): New local variable
 149         "marker". Drop opening of input file. Recognize marker and line
 150         number directives.
 151         * i386-opc.tbl (OPCODE_I386_H): Define.
 152         (i386-opc.h): Include it.
 153         (None): Undefine.
 154
 155 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 156
 157         PR gas/23418
 158         * i386-opc.h (Byte): Update comments.
 159         (Word): Likewise.
 160         (Dword): Likewise.
 161         (Fword): Likewise.
 162         (Qword): Likewise.
 163         (Tbyte): Likewise.
 164         (Xmmword): Likewise.
 165         (Ymmword): Likewise.
 166         (Zmmword): Likewise.
 167         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 168         vcvttps2uqq.
 169         * i386-tbl.h: Regenerated.
 170
 171 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 172
 173         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 174         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 175         * aarch64-asm-2.c: Regenerate.
 176         * aarch64-dis-2.c: Regenerate.
 177         * aarch64-opc-2.c: Regenerate.
 178
 179 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 180
 181         PR binutils/23192
 182         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 183         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 184         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 185         sqdmulh, sqrdmulh): Use Em16.
 186
 187 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 188
 189         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 190         csdb together with them.
 191         (thumb32_opcodes): Likewise.
 192
 193 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 196         requiring 32-bit registers as operands 2 and 3. Improve
 197         comments.
 198         (mwait, mwaitx): Fold templates. Improve comments.
 199         OPERAND_TYPE_INOUTPORTREG.
 200         * i386-tbl.h: Re-generate.
 201
 202 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 203
 204         * i386-gen.c (operand_type_init): Remove
 205         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 206         OPERAND_TYPE_INOUTPORTREG.
 207         * i386-init.h: Re-generate.
 208
 209 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 210
 211         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 212         (wrssq, wrussq): Add Qword.
 213         * i386-tbl.h: Re-generate.
 214
 215 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 216
 217         * i386-opc.h: Rename OTMax to OTNum.
 218         (OTNumOfUints): Adjust calculation.
 219         (OTUnused): Directly alias to OTNum.
 220
 221 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 222
 223         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 224         `reg_xys'.
 225         (lea_reg_xys): Likewise.
 226         (print_insn_loop_primitive): Rename `reg' local variable to
 227         `reg_dxy'.
 228
 229 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 230
 231         PR binutils/23242
 232         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 233
 234 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 235
 236         PR binutils/23369
 237         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 238         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 239
 240 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 241
 242         PR tdep/8282
 243         * mips-dis.c (mips_option_arg_t): New enumeration.
 244         (mips_options): New variable.
 245         (disassembler_options_mips): New function.
 246         (print_mips_disassembler_options): Reimplement in terms of
 247         `disassembler_options_mips'.
 248         * arm-dis.c (disassembler_options_arm): Adapt to using the
 249         `disasm_options_and_args_t' structure.
 250         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 251         * s390-dis.c (disassembler_options_s390): Likewise.
 252
 253 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 254
 255         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 256         expected result.
 257         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 258         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 259         * testsuite/ld-arm/tls-longplt.d: Likewise.
 260
 261 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 262
 263         PR binutils/23192
 264         * aarch64-asm-2.c: Regenerate.
 265         * aarch64-dis-2.c: Likewise.
 266         * aarch64-opc-2.c: Likewise.
 267         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 268         * aarch64-opc.c (operand_general_constraint_met_p,
 269         aarch64_print_operand): Likewise.
 270         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 271         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 272         fmlal2, fmlsl2.
 273         (AARCH64_OPERANDS): Add Em2.
 274
 275 2018-06-26  Nick Clifton  <nickc@redhat.com>
 276
 277         * po/uk.po: Updated Ukranian translation.
 278         * po/de.po: Updated German translation.
 279         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 280
 281 2018-06-26  Nick Clifton  <nickc@redhat.com>
 282
 283         * nfp-dis.c: Fix spelling mistake.
 284
 285 2018-06-24  Nick Clifton  <nickc@redhat.com>
 286
 287         * configure: Regenerate.
 288         * po/opcodes.pot: Regenerate.
 289
 290 2018-06-24  Nick Clifton  <nickc@redhat.com>
 291
 292         2.31 branch created.
 293
 294 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 295
 296         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 297         * aarch64-asm-2.c: Regenerate.
 298         * aarch64-dis-2.c: Likewise.
 299
 300 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 301
 302         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 303         `-M ginv' option description.
 304
 305 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 306
 307         PR gas/23305
 308         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 309         la and lla.
 310
 311 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 312
 313         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 314         * configure.ac: Remove AC_PREREQ.
 315         * Makefile.in: Re-generate.
 316         * aclocal.m4: Re-generate.
 317         * configure: Re-generate.
 318
 319 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 320
 321         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 322         mips64r6 descriptors.
 323         (parse_mips_ase_option): Handle -Mginv option.
 324         (print_mips_disassembler_options): Document -Mginv.
 325         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 326         (GINV): New macro.
 327         (mips_opcodes): Define ginvi and ginvt.
 328
 329 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 330             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 331
 332         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 333         * mips-opc.c (CRC, CRC64): New macros.
 334         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 335         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 336         crc32cd for CRC64.
 337
 338 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 339
 340         PR 20319
 341         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 342         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 343
 344 2018-06-06  Alan Modra  <amodra@gmail.com>
 345
 346         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 347         setjmp.  Move init for some other vars later too.
 348
 349 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 350
 351         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 352         (dis_private): Add new fields for property section tracking.
 353         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 354         (xtensa_instruction_fits): New functions.
 355         (fetch_data): Bump minimal fetch size to 4.
 356         (print_insn_xtensa): Make struct dis_private static.
 357         Load and prepare property table on section change.
 358         Don't disassemble literals. Don't disassemble instructions that
 359         cross property table boundaries.
 360
 361 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 362
 363         * configure: Regenerated.
 364
 365 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 368         * i386-tbl.h: Re-generate.
 369
 370 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-opc.tbl (sldt, str): Add NoRex64.
 373         * i386-tbl.h: Re-generate.
 374
 375 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 376
 377         * i386-opc.tbl (invpcid): Add Oword.
 378         * i386-tbl.h: Re-generate.
 379
 380 2018-06-01  Alan Modra  <amodra@gmail.com>
 381
 382         * sysdep.h (_bfd_error_handler): Don't declare.
 383         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 384         * rl78-decode.opc: Likewise.
 385         * msp430-decode.c: Regenerate.
 386         * rl78-decode.c: Regenerate.
 387
 388 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 389
 390         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 391         * i386-init.h : Regenerated.
 392
 393 2018-05-25  Alan Modra  <amodra@gmail.com>
 394
 395         * Makefile.in: Regenerate.
 396         * po/POTFILES.in: Regenerate.
 397
 398 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 399
 400         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 401         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 402         (insert_bab, extract_bab, insert_btab, extract_btab,
 403         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 404         (BAT, BBA VBA RBS XB6S): Delete macros.
 405         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 406         (BB, BD, RBX, XC6): Update for new macros.
 407         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 408         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 409         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 410         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 411
 412 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 413
 414         * Makefile.am: Add support for s12z architecture.
 415         * configure.ac: Likewise.
 416         * disassemble.c: Likewise.
 417         * disassemble.h: Likewise.
 418         * Makefile.in: Regenerate.
 419         * configure: Regenerate.
 420         * s12z-dis.c: New file.
 421         * s12z.h: New file.
 422
 423 2018-05-18  Alan Modra  <amodra@gmail.com>
 424
 425         * nfp-dis.c: Don't #include libbfd.h.
 426         (init_nfp3200_priv): Use bfd_get_section_contents.
 427         (nit_nfp6000_mecsr_sec): Likewise.
 428
 429 2018-05-17  Nick Clifton  <nickc@redhat.com>
 430
 431         * po/zh_CN.po: Updated simplified Chinese translation.
 432
 433 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 434
 435         PR binutils/23109
 436         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 437         * aarch64-dis-2.c: Regenerate.
 438
 439 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 440
 441         PR binutils/21446
 442         * aarch64-asm.c (opintl.h): Include.
 443         (aarch64_ins_sysreg): Enforce read/write constraints.
 444         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 445         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 446         (F_REG_READ, F_REG_WRITE): New.
 447         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 448         AARCH64_OPND_SYSREG.
 449         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 450         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 451         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 452         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 453         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 454         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 455         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 456         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 457         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 458         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 459         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 460         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 461         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 462         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 463         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 464         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 465         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 466
 467 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 468
 469         PR binutils/21446
 470         * aarch64-dis.c (no_notes: New.
 471         (parse_aarch64_dis_option): Support notes.
 472         (aarch64_decode_insn, print_operands): Likewise.
 473         (print_aarch64_disassembler_options): Document notes.
 474         * aarch64-opc.c (aarch64_print_operand): Support notes.
 475
 476 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 477
 478         PR binutils/21446
 479         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 480         and take error struct.
 481         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 482         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 483         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 484         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 485         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 486         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 487         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 488         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 489         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 490         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 491         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 492         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 493         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 494         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 495         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 496         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 497         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 498         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 499         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 500         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 501         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 502         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 503         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 504         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 505         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 506         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 507         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 508         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 509         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 510         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 511         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 512         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 513         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 514         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 515         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 516         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 517         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 518         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 519         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 520         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 521         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 522         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 523         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 524         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 525         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 526         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 527         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 528         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 529         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 530         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 531         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 532         (determine_disassembling_preference, aarch64_decode_insn,
 533         print_insn_aarch64_word, print_insn_data): Take errors struct.
 534         (print_insn_aarch64): Use errors.
 535         * aarch64-asm-2.c: Regenerate.
 536         * aarch64-dis-2.c: Regenerate.
 537         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 538         boolean in aarch64_insert_operan.
 539         (print_operand_extractor): Likewise.
 540         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 541
 542 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 543
 544         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 545
 546 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 547
 548         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 549
 550 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 551
 552         * cr16-opc.c (cr16_instruction): Comment typo fix.
 553         * hppa-dis.c (print_insn_hppa): Likewise.
 554
 555 2018-05-08  Jim Wilson  <jimw@sifive.com>
 556
 557         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 558         (match_c_slli64, match_srxi_as_c_srxi): New.
 559         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 560         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 561         <c.slli, c.srli, c.srai>: Use match_s_slli.
 562         <c.slli64, c.srli64, c.srai64>: New.
 563
 564 2018-05-08  Alan Modra  <amodra@gmail.com>
 565
 566         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 567         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 568         partition opcode space for index lookup.
 569
 570 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 571
 572         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 573         <insn_length>: ...with this.  Update usage.
 574         Remove duplicate call to *info->memory_error_func.
 575
 576 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 577             H.J. Lu  <hongjiu.lu@intel.com>
 578
 579         * i386-dis.c (Gva): New.
 580         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 581         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 582         (prefix_table): New instructions (see prefix above).
 583         (mod_table): New instructions (see prefix above).
 584         (OP_G): Handle va_mode.
 585         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 586         CPU_MOVDIR64B_FLAGS.
 587         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 588         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 589         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 590         * i386-opc.tbl: Add movidir{i,64b}.
 591         * i386-init.h: Regenerated.
 592         * i386-tbl.h: Likewise.
 593
 594 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 597         AddrPrefixOpReg.
 598         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 599         (AddrPrefixOpReg): This.
 600         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 601         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 602
 603 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 604
 605         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 606         (vle_num_opcodes): Likewise.
 607         (spe2_num_opcodes): Likewise.
 608         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 609         initialization loop.
 610         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 611         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 612         only once.
 613
 614 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 615
 616         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 617
 618 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 619
 620         Makefile.am: Added nfp-dis.c.
 621         configure.ac: Added bfd_nfp_arch.
 622         disassemble.h: Added print_insn_nfp prototype.
 623         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 624         nfp-dis.c: New, for NFP support.
 625         po/POTFILES.in: Added nfp-dis.c to the list.
 626         Makefile.in: Regenerate.
 627         configure: Regenerate.
 628
 629 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 632         templates into their base ones.
 633         * i386-tlb.h: Re-generate.
 634
 635 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 638         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 639         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 640         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 641         * i386-init.h: Re-generate.
 642
 643 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 644
 645         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 646         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 647         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 648         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 649         comment.
 650         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 651         and CpuRegMask.
 652         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 653         CpuRegMask: Delete.
 654         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 655         cpuregzmm, and cpuregmask.
 656         * i386-init.h: Re-generate.
 657         * i386-tbl.h: Re-generate.
 658
 659 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 662         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 663         * i386-init.h: Re-generate.
 664
 665 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-gen.c (VexImmExt): Delete.
 668         * i386-opc.h (VexImmExt, veximmext): Delete.
 669         * i386-opc.tbl: Drop all VexImmExt uses.
 670         * i386-tlb.h: Re-generate.
 671
 672 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 673
 674         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 675         register-only forms.
 676         * i386-tlb.h: Re-generate.
 677
 678 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 679
 680         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 681
 682 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 683
 684         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 685         PREFIX_0F1C.
 686         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 687         (cpu_flags): Add CpuCLDEMOTE.
 688         * i386-init.h: Regenerate.
 689         * i386-opc.h (enum): Add CpuCLDEMOTE,
 690         (i386_cpu_flags): Add cpucldemote.
 691         * i386-opc.tbl: Add cldemote.
 692         * i386-tbl.h: Regenerate.
 693
 694 2018-04-16  Alan Modra  <amodra@gmail.com>
 695
 696         * Makefile.am: Remove sh5 and sh64 support.
 697         * configure.ac: Likewise.
 698         * disassemble.c: Likewise.
 699         * disassemble.h: Likewise.
 700         * sh-dis.c: Likewise.
 701         * sh64-dis.c: Delete.
 702         * sh64-opc.c: Delete.
 703         * sh64-opc.h: Delete.
 704         * Makefile.in: Regenerate.
 705         * configure: Regenerate.
 706         * po/POTFILES.in: Regenerate.
 707
 708 2018-04-16  Alan Modra  <amodra@gmail.com>
 709
 710         * Makefile.am: Remove w65 support.
 711         * configure.ac: Likewise.
 712         * disassemble.c: Likewise.
 713         * disassemble.h: Likewise.
 714         * w65-dis.c: Delete.
 715         * w65-opc.h: Delete.
 716         * Makefile.in: Regenerate.
 717         * configure: Regenerate.
 718         * po/POTFILES.in: Regenerate.
 719
 720 2018-04-16  Alan Modra  <amodra@gmail.com>
 721
 722         * configure.ac: Remove we32k support.
 723         * configure: Regenerate.
 724
 725 2018-04-16  Alan Modra  <amodra@gmail.com>
 726
 727         * Makefile.am: Remove m88k support.
 728         * configure.ac: Likewise.
 729         * disassemble.c: Likewise.
 730         * disassemble.h: Likewise.
 731         * m88k-dis.c: Delete.
 732         * Makefile.in: Regenerate.
 733         * configure: Regenerate.
 734         * po/POTFILES.in: Regenerate.
 735
 736 2018-04-16  Alan Modra  <amodra@gmail.com>
 737
 738         * Makefile.am: Remove i370 support.
 739         * configure.ac: Likewise.
 740         * disassemble.c: Likewise.
 741         * disassemble.h: Likewise.
 742         * i370-dis.c: Delete.
 743         * i370-opc.c: Delete.
 744         * Makefile.in: Regenerate.
 745         * configure: Regenerate.
 746         * po/POTFILES.in: Regenerate.
 747
 748 2018-04-16  Alan Modra  <amodra@gmail.com>
 749
 750         * Makefile.am: Remove h8500 support.
 751         * configure.ac: Likewise.
 752         * disassemble.c: Likewise.
 753         * disassemble.h: Likewise.
 754         * h8500-dis.c: Delete.
 755         * h8500-opc.h: Delete.
 756         * Makefile.in: Regenerate.
 757         * configure: Regenerate.
 758         * po/POTFILES.in: Regenerate.
 759
 760 2018-04-16  Alan Modra  <amodra@gmail.com>
 761
 762         * configure.ac: Remove tahoe support.
 763         * configure: Regenerate.
 764
 765 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 766
 767         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 768         umwait.
 769         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 770         64-bit mode.
 771         * i386-tbl.h: Regenerated.
 772
 773 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 774
 775         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 776         PREFIX_MOD_1_0FAE_REG_6.
 777         (va_mode): New.
 778         (OP_E_register): Use va_mode.
 779         * i386-dis-evex.h (prefix_table):
 780         New instructions (see prefixes above).
 781         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 782         (cpu_flags): Likewise.
 783         * i386-opc.h (enum): Likewise.
 784         (i386_cpu_flags): Likewise.
 785         * i386-opc.tbl: Add umonitor, umwait, tpause.
 786         * i386-init.h: Regenerate.
 787         * i386-tbl.h: Likewise.
 788
 789 2018-04-11  Alan Modra  <amodra@gmail.com>
 790
 791         * opcodes/i860-dis.c: Delete.
 792         * opcodes/i960-dis.c: Delete.
 793         * Makefile.am: Remove i860 and i960 support.
 794         * configure.ac: Likewise.
 795         * disassemble.c: Likewise.
 796         * disassemble.h: Likewise.
 797         * Makefile.in: Regenerate.
 798         * configure: Regenerate.
 799         * po/POTFILES.in: Regenerate.
 800
 801 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 802
 803         PR binutils/23025
 804         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 805         to 0.
 806         (print_insn): Clear vex instead of vex.evex.
 807
 808 2018-04-04  Nick Clifton  <nickc@redhat.com>
 809
 810         * po/es.po: Updated Spanish translation.
 811
 812 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-gen.c (opcode_modifiers): Delete VecESize.
 815         * i386-opc.h (VecESize): Delete.
 816         (struct i386_opcode_modifier): Delete vecesize.
 817         * i386-opc.tbl: Drop VecESize.
 818         * i386-tlb.h: Re-generate.
 819
 820 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 823         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 824         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 825         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 826         * i386-tlb.h: Re-generate.
 827
 828 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 831         Fold AVX512 forms
 832         * i386-tlb.h: Re-generate.
 833
 834 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 837         (vex_len_table): Drop Y for vcvt*2si.
 838         (putop): Replace plain 'Y' handling by abort().
 839
 840 2018-03-28  Nick Clifton  <nickc@redhat.com>
 841
 842         PR 22988
 843         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 844         instructions with only a base address register.
 845         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 846         handle AARHC64_OPND_SVE_ADDR_R.
 847         (aarch64_print_operand): Likewise.
 848         * aarch64-asm-2.c: Regenerate.
 849         * aarch64_dis-2.c: Regenerate.
 850         * aarch64-opc-2.c: Regenerate.
 851
 852 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 853
 854         * i386-opc.tbl: Drop VecESize from register only insn forms and
 855         memory forms not allowing broadcast.
 856         * i386-tlb.h: Re-generate.
 857
 858 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 859
 860         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 861         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 862         sha256*): Drop Disp<N>.
 863
 864 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-dis.c (EbndS, bnd_swap_mode): New.
 867         (prefix_table): Use EbndS.
 868         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 869         * i386-opc.tbl (bndmov): Move misplaced Load.
 870         * i386-tlb.h: Re-generate.
 871
 872 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 875         templates allowing memory operands and folded ones for register
 876         only flavors.
 877         * i386-tlb.h: Re-generate.
 878
 879 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 880
 881         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 882         256-bit templates. Drop redundant leftover Disp<N>.
 883         * i386-tlb.h: Re-generate.
 884
 885 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 886
 887         * riscv-opc.c (riscv_insn_types): New.
 888
 889 2018-03-13  Nick Clifton  <nickc@redhat.com>
 890
 891         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 892
 893 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 894
 895         * i386-opc.tbl: Add Optimize to clr.
 896         * i386-tbl.h: Regenerated.
 897
 898 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 901         * i386-opc.h (OldGcc): Removed.
 902         (i386_opcode_modifier): Remove oldgcc.
 903         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 904         instructions for old (<= 2.8.1) versions of gcc.
 905         * i386-tbl.h: Regenerated.
 906
 907 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-opc.h (EVEXDYN): New.
 910         * i386-opc.tbl: Fold various AVX512VL templates.
 911         * i386-tlb.h: Re-generate.
 912
 913 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 914
 915         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 916         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 917         vpexpandd, vpexpandq): Fold AFX512VF templates.
 918         * i386-tlb.h: Re-generate.
 919
 920 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 921
 922         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 923         Fold 128- and 256-bit VEX-encoded templates.
 924         * i386-tlb.h: Re-generate.
 925
 926 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 927
 928         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 929         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 930         vpexpandd, vpexpandq): Fold AVX512F templates.
 931         * i386-tlb.h: Re-generate.
 932
 933 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 934
 935         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 936         64-bit templates. Drop Disp<N>.
 937         * i386-tlb.h: Re-generate.
 938
 939 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 940
 941         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 942         and 256-bit templates.
 943         * i386-tlb.h: Re-generate.
 944
 945 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 946
 947         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 948         * i386-tlb.h: Re-generate.
 949
 950 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 951
 952         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 953         Drop NoAVX.
 954         * i386-tlb.h: Re-generate.
 955
 956 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 957
 958         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 959         * i386-tlb.h: Re-generate.
 960
 961 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 962
 963         * i386-gen.c (opcode_modifiers): Delete FloatD.
 964         * i386-opc.h (FloatD): Delete.
 965         (struct i386_opcode_modifier): Delete floatd.
 966         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 967         FloatD by D.
 968         * i386-tlb.h: Re-generate.
 969
 970 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 971
 972         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 973
 974 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 975
 976         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 977         * i386-tlb.h: Re-generate.
 978
 979 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 980
 981         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 982         forms.
 983         * i386-tlb.h: Re-generate.
 984
 985 2018-03-07  Alan Modra  <amodra@gmail.com>
 986
 987         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 988         bfd_arch_rs6000.
 989         * disassemble.h (print_insn_rs6000): Delete.
 990         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 991         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 992         (print_insn_rs6000): Delete.
 993
 994 2018-03-03  Alan Modra  <amodra@gmail.com>
 995
 996         * sysdep.h (opcodes_error_handler): Define.
 997         (_bfd_error_handler): Declare.
 998         * Makefile.am: Remove stray #.
 999         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1000         EDIT" comment.
1001         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1002         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1003         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1004         opcodes_error_handler to print errors.  Standardize error messages.
1005         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1006         and include opintl.h.
1007         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1008         * i386-gen.c: Standardize error messages.
1009         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1010         * Makefile.in: Regenerate.
1011         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1012         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1013         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1014         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1015         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1016         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1017         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1018         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1019         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1020         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1021         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1022         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1023         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1024
1025 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1026
1027         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1028         vpsub[bwdq] instructions.
1029         * i386-tbl.h: Regenerated.
1030
1031 2018-03-01  Alan Modra  <amodra@gmail.com>
1032
1033         * configure.ac (ALL_LINGUAS): Sort.
1034         * configure: Regenerate.
1035
1036 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1037
1038         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1039         macro by assignements.
1040
1041 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1042
1043         PR gas/22871
1044         * i386-gen.c (opcode_modifiers): Add Optimize.
1045         * i386-opc.h (Optimize): New enum.
1046         (i386_opcode_modifier): Add optimize.
1047         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1048         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1049         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1050         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1051         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1052         vpxord and vpxorq.
1053         * i386-tbl.h: Regenerated.
1054
1055 2018-02-26  Alan Modra  <amodra@gmail.com>
1056
1057         * crx-dis.c (getregliststring): Allocate a large enough buffer
1058         to silence false positive gcc8 warning.
1059
1060 2018-02-22  Shea Levy <shea@shealevy.com>
1061
1062         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1063
1064 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1065
1066         * i386-opc.tbl: Add {rex},
1067         * i386-tbl.h: Regenerated.
1068
1069 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1070
1071         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1072         (mips16_opcodes): Replace `M' with `m' for "restore".
1073
1074 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1075
1076         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1077
1078 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1079
1080         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1081         variable to `function_index'.
1082
1083 2018-02-13  Nick Clifton  <nickc@redhat.com>
1084
1085         PR 22823
1086         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1087         about truncation of printing.
1088
1089 2018-02-12  Henry Wong <henry@stuffedcow.net>
1090
1091         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1092
1093 2018-02-05  Nick Clifton  <nickc@redhat.com>
1094
1095         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1096
1097 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1098
1099         * i386-dis.c (enum): Add pconfig.
1100         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1101         (cpu_flags): Add CpuPCONFIG.
1102         * i386-opc.h (enum): Add CpuPCONFIG.
1103         (i386_cpu_flags): Add cpupconfig.
1104         * i386-opc.tbl: Add PCONFIG instruction.
1105         * i386-init.h: Regenerate.
1106         * i386-tbl.h: Likewise.
1107
1108 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1109
1110         * i386-dis.c (enum): Add PREFIX_0F09.
1111         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1112         (cpu_flags): Add CpuWBNOINVD.
1113         * i386-opc.h (enum): Add CpuWBNOINVD.
1114         (i386_cpu_flags): Add cpuwbnoinvd.
1115         * i386-opc.tbl: Add WBNOINVD instruction.
1116         * i386-init.h: Regenerate.
1117         * i386-tbl.h: Likewise.
1118
1119 2018-01-17  Jim Wilson  <jimw@sifive.com>
1120
1121         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1122
1123 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1124
1125         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1126         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1127         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1128         (cpu_flags): Add CpuIBT, CpuSHSTK.
1129         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1130         (i386_cpu_flags): Add cpuibt, cpushstk.
1131         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1132         * i386-init.h: Regenerate.
1133         * i386-tbl.h: Likewise.
1134
1135 2018-01-16  Nick Clifton  <nickc@redhat.com>
1136
1137         * po/pt_BR.po: Updated Brazilian Portugese translation.
1138         * po/de.po: Updated German translation.
1139
1140 2018-01-15  Jim Wilson  <jimw@sifive.com>
1141
1142         * riscv-opc.c (match_c_nop): New.
1143         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1144
1145 2018-01-15  Nick Clifton  <nickc@redhat.com>
1146
1147         * po/uk.po: Updated Ukranian translation.
1148
1149 2018-01-13  Nick Clifton  <nickc@redhat.com>
1150
1151         * po/opcodes.pot: Regenerated.
1152
1153 2018-01-13  Nick Clifton  <nickc@redhat.com>
1154
1155         * configure: Regenerate.
1156
1157 2018-01-13  Nick Clifton  <nickc@redhat.com>
1158
1159         2.30 branch created.
1160
1161 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1162
1163         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1164         * i386-tbl.h: Regenerate.
1165
1166 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1167
1168         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1169         * i386-tbl.h: Re-generate.
1170
1171 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1172
1173         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1174         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1175         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1176         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1177         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1178         Disp8MemShift of AVX512VL forms.
1179         * i386-tbl.h: Re-generate.
1180
1181 2018-01-09  Jim Wilson  <jimw@sifive.com>
1182
1183         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1184         then the hi_addr value is zero.
1185
1186 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1187
1188         * arm-dis.c (arm_opcodes): Add csdb.
1189         (thumb32_opcodes): Add csdb.
1190
1191 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1192
1193         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1194         * aarch64-asm-2.c: Regenerate.
1195         * aarch64-dis-2.c: Regenerate.
1196         * aarch64-opc-2.c: Regenerate.
1197
1198 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1199
1200         PR gas/22681
1201         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1202         Remove AVX512 vmovd with 64-bit operands.
1203         * i386-tbl.h: Regenerated.
1204
1205 2018-01-05  Jim Wilson  <jimw@sifive.com>
1206
1207         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1208         jalr.
1209
1210 2018-01-03  Alan Modra  <amodra@gmail.com>
1211
1212         Update year range in copyright notice of all files.
1213
1214 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1215
1216         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1217         and OPERAND_TYPE_REGZMM entries.
1218
1219 For older changes see ChangeLog-2017
1220 \f
1221 Copyright (C) 2018 Free Software Foundation, Inc.
1222
1223 Copying and distribution of this file, with or without modification,
1224 are permitted in any medium without royalty provided the copyright
1225 notice and this notice are preserved.
1226
1227 Local Variables:
1228 mode: change-log
1229 left-margin: 8
1230 fill-column: 74
1231 version-control: never
1232 End: