opcodes/ChangeLog

   1 2020-04-07  Lili Cui  <lili.cui@intel.com>
   2
   3         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
   4         (prefix_table): New instructions (see prefixes above).
   5         (rm_table): Likewise
   6         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
   7         CPU_ANY_TSXLDTRK_FLAGS.
   8         (cpu_flags): Add CpuTSXLDTRK.
   9         * i386-opc.h (enum): Add CpuTSXLDTRK.
  10         (i386_cpu_flags): Add cputsxldtrk.
  11         * i386-opc.tbl: Add XSUSPLDTRK insns.
  12         * i386-init.h: Regenerate.
  13         * i386-tbl.h: Likewise.
  14
  15 2020-04-02  Lili Cui  <lili.cui@intel.com>
  16
  17         * i386-dis.c (prefix_table): New instructions serialize.
  18         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
  19         CPU_ANY_SERIALIZE_FLAGS.
  20         (cpu_flags): Add CpuSERIALIZE.
  21         * i386-opc.h (enum): Add CpuSERIALIZE.
  22         (i386_cpu_flags): Add cpuserialize.
  23         * i386-opc.tbl: Add SERIALIZE insns.
  24         * i386-init.h: Regenerate.
  25         * i386-tbl.h: Likewise.
  26
  27 2020-03-26  Alan Modra  <amodra@gmail.com>
  28
  29         * disassemble.h (opcodes_assert): Declare.
  30         (OPCODES_ASSERT): Define.
  31         * disassemble.c: Don't include assert.h.  Include opintl.h.
  32         (opcodes_assert): New function.
  33         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
  34         (bfd_h8_disassemble): Reduce size of data array.  Correctly
  35         calculate maxlen.  Omit insn decoding when insn length exceeds
  36         maxlen.  Exit from nibble loop when looking for E, before
  37         accessing next data byte.  Move processing of E outside loop.
  38         Replace tests of maxlen in loop with assertions.
  39
  40 2020-03-26  Alan Modra  <amodra@gmail.com>
  41
  42         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
  43
  44 2020-03-25  Alan Modra  <amodra@gmail.com>
  45
  46         * z80-dis.c (suffix): Init mybuf.
  47
  48 2020-03-22  Alan Modra  <amodra@gmail.com>
  49
  50         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
  51         successflly read from section.
  52
  53 2020-03-22  Alan Modra  <amodra@gmail.com>
  54
  55         * arc-dis.c (find_format): Use ISO C string concatenation rather
  56         than line continuation within a string.  Don't access needs_limm
  57         before testing opcode != NULL.
  58
  59 2020-03-22  Alan Modra  <amodra@gmail.com>
  60
  61         * ns32k-dis.c (print_insn_arg): Update comment.
  62         (print_insn_ns32k): Reduce size of index_offset array, and
  63         initialize, passing -1 to print_insn_arg for args that are not
  64         an index.  Don't exit arg loop early.  Abort on bad arg number.
  65
  66 2020-03-22  Alan Modra  <amodra@gmail.com>
  67
  68         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
  69         * s12z-opc.c: Formatting.
  70         (operands_f): Return an int.
  71         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
  72         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
  73         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
  74         (exg_sex_discrim): Likewise.
  75         (create_immediate_operand, create_bitfield_operand),
  76         (create_register_operand_with_size, create_register_all_operand),
  77         (create_register_all16_operand, create_simple_memory_operand),
  78         (create_memory_operand, create_memory_auto_operand): Don't
  79         segfault on malloc failure.
  80         (z_ext24_decode): Return an int status, negative on fail, zero
  81         on success.
  82         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
  83         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
  84         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
  85         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
  86         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
  87         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
  88         (loop_primitive_decode, shift_decode, psh_pul_decode),
  89         (bit_field_decode): Similarly.
  90         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
  91         to return value, update callers.
  92         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
  93         Don't segfault on NULL operand.
  94         (decode_operation): Return OP_INVALID on first fail.
  95         (decode_s12z): Check all reads, returning -1 on fail.
  96
  97 2020-03-20  Alan Modra  <amodra@gmail.com>
  98
  99         * metag-dis.c (print_insn_metag): Don't ignore status from
 100         read_memory_func.
 101
 102 2020-03-20  Alan Modra  <amodra@gmail.com>
 103
 104         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 105         Initialize parts of buffer not written when handling a possible
 106         2-byte insn at end of section.  Don't attempt decoding of such
 107         an insn by the 4-byte machinery.
 108
 109 2020-03-20  Alan Modra  <amodra@gmail.com>
 110
 111         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 112         partially filled buffer.  Prevent lookup of 4-byte insns when
 113         only VLE 2-byte insns are possible due to section size.  Print
 114         ".word" rather than ".long" for 2-byte leftovers.
 115
 116 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 117
 118         PR 25641
 119         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 120
 121 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 122
 123         * i386-dis.c (X86_64_0D): Rename to ...
 124         (X86_64_0E): ... this.
 125
 126 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 127
 128         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 129         * Makefile.in: Regenerated.
 130
 131 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 134         3-operand pseudos.
 135         * i386-tbl.h: Re-generate.
 136
 137 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 140         vprot*, vpsha*, and vpshl*.
 141         * i386-tbl.h: Re-generate.
 142
 143 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 146         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 147         * i386-tbl.h: Re-generate.
 148
 149 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 152         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 153         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 154         * i386-tbl.h: Re-generate.
 155
 156 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-gen.c (struct template_arg, struct template_instance,
 159         struct template_param, struct template, templates,
 160         parse_template, expand_templates): New.
 161         (process_i386_opcodes): Various local variables moved to
 162         expand_templates. Call parse_template and expand_templates.
 163         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 164         * i386-tbl.h: Re-generate.
 165
 166 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 167
 168         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 169         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 170         register and memory source templates. Replace VexW= by VexW*
 171         where applicable.
 172         * i386-tbl.h: Re-generate.
 173
 174 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 177         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 178         * i386-tbl.h: Re-generate.
 179
 180 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 183         * i386-tbl.h: Re-generate.
 184
 185 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 188         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 189         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 190         VexW0 on SSE2AVX variants.
 191         (vmovq): Drop NoRex64 from XMM/XMM variants.
 192         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 193         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 194         applicable use VexW0.
 195         * i386-tbl.h: Re-generate.
 196
 197 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 200         * i386-opc.h (Rex64): Delete.
 201         (struct i386_opcode_modifier): Remove rex64 field.
 202         * i386-opc.tbl (crc32): Drop Rex64.
 203         Replace Rex64 with Size64 everywhere else.
 204         * i386-tbl.h: Re-generate.
 205
 206 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-dis.c (OP_E_memory): Exclude recording of used address
 209         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 210         addressed memory operands for MPX insns.
 211
 212 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 213
 214         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 215         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 216         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 217         (ptwrite): Split into non-64-bit and 64-bit forms.
 218         * i386-tbl.h: Re-generate.
 219
 220 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 223         template.
 224         * i386-tbl.h: Re-generate.
 225
 226 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 229         (prefix_table): Move vmmcall here. Add vmgexit.
 230         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 231         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 232         (cpu_flags): Add CpuSEV_ES entry.
 233         * i386-opc.h (CpuSEV_ES): New.
 234         (union i386_cpu_flags): Add cpusev_es field.
 235         * i386-opc.tbl (vmgexit): New.
 236         * i386-init.h, i386-tbl.h: Re-generate.
 237
 238 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 241         with MnemonicSize.
 242         * i386-opc.h (IGNORESIZE): New.
 243         (DEFAULTSIZE): Likewise.
 244         (IgnoreSize): Removed.
 245         (DefaultSize): Likewise.
 246         (MnemonicSize): New.
 247         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 248         mnemonicsize.
 249         * i386-opc.tbl (IgnoreSize): New.
 250         (DefaultSize): Likewise.
 251         * i386-tbl.h: Regenerated.
 252
 253 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 254
 255         PR 25627
 256         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 257         instructions.
 258
 259 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         PR gas/25622
 262         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 263         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 264         * i386-tbl.h: Regenerated.
 265
 266 2020-02-26  Alan Modra  <amodra@gmail.com>
 267
 268         * aarch64-asm.c: Indent labels correctly.
 269         * aarch64-dis.c: Likewise.
 270         * aarch64-gen.c: Likewise.
 271         * aarch64-opc.c: Likewise.
 272         * alpha-dis.c: Likewise.
 273         * i386-dis.c: Likewise.
 274         * nds32-asm.c: Likewise.
 275         * nfp-dis.c: Likewise.
 276         * visium-dis.c: Likewise.
 277
 278 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 279
 280         * arc-regs.h (int_vector_base): Make it available for all ARC
 281         CPUs.
 282
 283 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 284
 285         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 286         changed.
 287
 288 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 289
 290         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 291         c.mv/c.li if rs1 is zero.
 292
 293 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 296         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 297         CPU_POPCNT_FLAGS.
 298         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 299         * i386-opc.h (CpuABM): Removed.
 300         (CpuPOPCNT): New.
 301         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 302         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 303         popcnt.  Remove CpuABM from lzcnt.
 304         * i386-init.h: Regenerated.
 305         * i386-tbl.h: Likewise.
 306
 307 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 310         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 311         VexW1 instead of open-coding them.
 312         * i386-tbl.h: Re-generate.
 313
 314 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-opc.tbl (AddrPrefixOpReg): Define.
 317         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 318         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 319         templates. Drop NoRex64.
 320         * i386-tbl.h: Re-generate.
 321
 322 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 323
 324         PR gas/6518
 325         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 326         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 327         into Intel syntax instance (with Unpsecified) and AT&T one
 328         (without).
 329         (vcvtneps2bf16): Likewise, along with folding the two so far
 330         separate ones.
 331         * i386-tbl.h: Re-generate.
 332
 333 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 336         CPU_ANY_SSE4A_FLAGS.
 337
 338 2020-02-17  Alan Modra  <amodra@gmail.com>
 339
 340         * i386-gen.c (cpu_flag_init): Correct last change.
 341
 342 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 343
 344         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 345         CPU_ANY_SSE4_FLAGS.
 346
 347 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 348
 349         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 350         (movzx): Likewise.
 351
 352 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 353
 354         PR gas/25438
 355         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 356         destination for Cpu64-only variant.
 357         (movzx): Fold patterns.
 358         * i386-tbl.h: Re-generate.
 359
 360 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 363         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 364         CPU_ANY_SSE4_FLAGS entry.
 365         * i386-init.h: Re-generate.
 366
 367 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 370         with Unspecified, making the present one AT&T syntax only.
 371         * i386-tbl.h: Re-generate.
 372
 373 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 376         * i386-tbl.h: Re-generate.
 377
 378 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 379
 380         PR gas/24546
 381         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 382         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 383         Amd64 and Intel64 templates.
 384         (call, jmp): Likewise for far indirect variants. Dro
 385         Unspecified.
 386         * i386-tbl.h: Re-generate.
 387
 388 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 391         * i386-opc.h (ShortForm): Delete.
 392         (struct i386_opcode_modifier): Remove shortform field.
 393         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 394         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 395         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 396         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 397         Drop ShortForm.
 398         * i386-tbl.h: Re-generate.
 399
 400 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 401
 402         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 403         fucompi): Drop ShortForm from operand-less templates.
 404         * i386-tbl.h: Re-generate.
 405
 406 2020-02-11  Alan Modra  <amodra@gmail.com>
 407
 408         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 409         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 410         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 411         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 412         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 413
 414 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 415
 416         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 417         (cde_opcodes): Add VCX* instructions.
 418
 419 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 420             Matthew Malcomson  <matthew.malcomson@arm.com>
 421
 422         * arm-dis.c (struct cdeopcode32): New.
 423         (CDE_OPCODE): New macro.
 424         (cde_opcodes): New disassembly table.
 425         (regnames): New option to table.
 426         (cde_coprocs): New global variable.
 427         (print_insn_cde): New
 428         (print_insn_thumb32): Use print_insn_cde.
 429         (parse_arm_disassembler_options): Parse coprocN args.
 430
 431 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 432
 433         PR gas/25516
 434         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 435         with ISA64.
 436         * i386-opc.h (AMD64): Removed.
 437         (Intel64): Likewose.
 438         (AMD64): New.
 439         (INTEL64): Likewise.
 440         (INTEL64ONLY): Likewise.
 441         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 442         * i386-opc.tbl (Amd64): New.
 443         (Intel64): Likewise.
 444         (Intel64Only): Likewise.
 445         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 446         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 447         * i386-tbl.h: Regenerated.
 448
 449 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 450
 451         PR 25469
 452         * z80-dis.c: Add support for GBZ80 opcodes.
 453
 454 2020-02-04  Alan Modra  <amodra@gmail.com>
 455
 456         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 457
 458 2020-02-03  Alan Modra  <amodra@gmail.com>
 459
 460         * m32c-ibld.c: Regenerate.
 461
 462 2020-02-01  Alan Modra  <amodra@gmail.com>
 463
 464         * frv-ibld.c: Regenerate.
 465
 466 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 467
 468         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 469         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 470         (OP_E_memory): Replace xmm_mdq_mode case label by
 471         vex_scalar_w_dq_mode one.
 472         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 473
 474 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 477         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 478         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 479         (intel_operand_size): Drop vex_w_dq_mode case label.
 480
 481 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 482
 483         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 484         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 485
 486 2020-01-30  Alan Modra  <amodra@gmail.com>
 487
 488         * m32c-ibld.c: Regenerate.
 489
 490 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 491
 492         * bpf-opc.c: Regenerate.
 493
 494 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 495
 496         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 497         (dis386): Use them to replace C2/C3 table entries.
 498         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 499         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 500         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 501         * i386-tbl.h: Re-generate.
 502
 503 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 504
 505         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 506         forms.
 507         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 508         DefaultSize.
 509         * i386-tbl.h: Re-generate.
 510
 511 2020-01-30  Alan Modra  <amodra@gmail.com>
 512
 513         * tic4x-dis.c (tic4x_dp): Make unsigned.
 514
 515 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 516             Jan Beulich  <jbeulich@suse.com>
 517
 518         PR binutils/25445
 519         * i386-dis.c (MOVSXD_Fixup): New function.
 520         (movsxd_mode): New enum.
 521         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 522         (intel_operand_size): Handle movsxd_mode.
 523         (OP_E_register): Likewise.
 524         (OP_G): Likewise.
 525         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 526         register on movsxd.  Add movsxd with 16-bit destination register
 527         for AMD64 and Intel64 ISAs.
 528         * i386-tbl.h: Regenerated.
 529
 530 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 531
 532         PR 25403
 533         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 534         * aarch64-asm-2.c: Regenerate
 535         * aarch64-dis-2.c: Likewise.
 536         * aarch64-opc-2.c: Likewise.
 537
 538 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-opc.tbl (sysret): Drop DefaultSize.
 541         * i386-tbl.h: Re-generate.
 542
 543 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 544
 545         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 546         Dword.
 547         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 548         * i386-tbl.h: Re-generate.
 549
 550 2020-01-20  Nick Clifton  <nickc@redhat.com>
 551
 552         * po/de.po: Updated German translation.
 553         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 554         * po/uk.po: Updated Ukranian translation.
 555
 556 2020-01-20  Alan Modra  <amodra@gmail.com>
 557
 558         * hppa-dis.c (fput_const): Remove useless cast.
 559
 560 2020-01-20  Alan Modra  <amodra@gmail.com>
 561
 562         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 563
 564 2020-01-18  Nick Clifton  <nickc@redhat.com>
 565
 566         * configure: Regenerate.
 567         * po/opcodes.pot: Regenerate.
 568
 569 2020-01-18  Nick Clifton  <nickc@redhat.com>
 570
 571         Binutils 2.34 branch created.
 572
 573 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 574
 575         * opintl.h: Fix spelling error (seperate).
 576
 577 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 578
 579         * i386-opc.tbl: Add {vex} pseudo prefix.
 580         * i386-tbl.h: Regenerated.
 581
 582 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 583
 584         PR 25376
 585         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 586         (neon_opcodes): Likewise.
 587         (select_arm_features): Make sure we enable MVE bits when selecting
 588         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 589         any architecture.
 590
 591 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 592
 593         * i386-opc.tbl: Drop stale comment from XOP section.
 594
 595 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 596
 597         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 598         (extractps): Add VexWIG to SSE2AVX forms.
 599         * i386-tbl.h: Re-generate.
 600
 601 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 602
 603         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 604         Size64 from and use VexW1 on SSE2AVX forms.
 605         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 606         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 607         * i386-tbl.h: Re-generate.
 608
 609 2020-01-15  Alan Modra  <amodra@gmail.com>
 610
 611         * tic4x-dis.c (tic4x_version): Make unsigned long.
 612         (optab, optab_special, registernames): New file scope vars.
 613         (tic4x_print_register): Set up registernames rather than
 614         malloc'd registertable.
 615         (tic4x_disassemble): Delete optable and optable_special.  Use
 616         optab and optab_special instead.  Throw away old optab,
 617         optab_special and registernames when info->mach changes.
 618
 619 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 620
 621         PR 25377
 622         * z80-dis.c (suffix): Use .db instruction to generate double
 623         prefix.
 624
 625 2020-01-14  Alan Modra  <amodra@gmail.com>
 626
 627         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 628         values to unsigned before shifting.
 629
 630 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 631
 632         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 633         flow instructions.
 634         (print_insn_thumb16, print_insn_thumb32): Likewise.
 635         (print_insn): Initialize the insn info.
 636         * i386-dis.c (print_insn): Initialize the insn info fields, and
 637         detect jumps.
 638
 639 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 640
 641         * arc-opc.c (C_NE): Make it required.
 642
 643 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 644
 645         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 646         reserved register name.
 647
 648 2020-01-13  Alan Modra  <amodra@gmail.com>
 649
 650         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 651         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 652
 653 2020-01-13  Alan Modra  <amodra@gmail.com>
 654
 655         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 656         result of wasm_read_leb128 in a uint64_t and check that bits
 657         are not lost when copying to other locals.  Use uint32_t for
 658         most locals.  Use PRId64 when printing int64_t.
 659
 660 2020-01-13  Alan Modra  <amodra@gmail.com>
 661
 662         * score-dis.c: Formatting.
 663         * score7-dis.c: Formatting.
 664
 665 2020-01-13  Alan Modra  <amodra@gmail.com>
 666
 667         * score-dis.c (print_insn_score48): Use unsigned variables for
 668         unsigned values.  Don't left shift negative values.
 669         (print_insn_score32): Likewise.
 670         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 671
 672 2020-01-13  Alan Modra  <amodra@gmail.com>
 673
 674         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 675
 676 2020-01-13  Alan Modra  <amodra@gmail.com>
 677
 678         * fr30-ibld.c: Regenerate.
 679
 680 2020-01-13  Alan Modra  <amodra@gmail.com>
 681
 682         * xgate-dis.c (print_insn): Don't left shift signed value.
 683         (ripBits): Formatting, use 1u.
 684
 685 2020-01-10  Alan Modra  <amodra@gmail.com>
 686
 687         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 688         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 689
 690 2020-01-10  Alan Modra  <amodra@gmail.com>
 691
 692         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 693         and XRREG value earlier to avoid a shift with negative exponent.
 694         * m10200-dis.c (disassemble): Similarly.
 695
 696 2020-01-09  Nick Clifton  <nickc@redhat.com>
 697
 698         PR 25224
 699         * z80-dis.c (ld_ii_ii): Use correct cast.
 700
 701 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 702
 703         PR 25224
 704         * z80-dis.c (ld_ii_ii): Use character constant when checking
 705         opcode byte value.
 706
 707 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 708
 709         * i386-dis.c (SEP_Fixup): New.
 710         (SEP): Define.
 711         (dis386_twobyte): Use it for sysenter/sysexit.
 712         (enum x86_64_isa): Change amd64 enumerator to value 1.
 713         (OP_J): Compare isa64 against intel64 instead of amd64.
 714         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 715         forms.
 716         * i386-tbl.h: Re-generate.
 717
 718 2020-01-08  Alan Modra  <amodra@gmail.com>
 719
 720         * z8k-dis.c: Include libiberty.h
 721         (instr_data_s): Make max_fetched unsigned.
 722         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 723         Don't exceed byte_info bounds.
 724         (output_instr): Make num_bytes unsigned.
 725         (unpack_instr): Likewise for nibl_count and loop.
 726         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 727         idx unsigned.
 728         * z8k-opc.h: Regenerate.
 729
 730 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 731
 732         * arc-tbl.h (llock): Use 'LLOCK' as class.
 733         (llockd): Likewise.
 734         (scond): Use 'SCOND' as class.
 735         (scondd): Likewise.
 736         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 737         (scondd): Likewise.
 738
 739 2020-01-06  Alan Modra  <amodra@gmail.com>
 740
 741         * m32c-ibld.c: Regenerate.
 742
 743 2020-01-06  Alan Modra  <amodra@gmail.com>
 744
 745         PR 25344
 746         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 747         Peek at next byte to prevent recursion on repeated prefix bytes.
 748         Ensure uninitialised "mybuf" is not accessed.
 749         (print_insn_z80): Don't zero n_fetch and n_used here,..
 750         (print_insn_z80_buf): ..do it here instead.
 751
 752 2020-01-04  Alan Modra  <amodra@gmail.com>
 753
 754         * m32r-ibld.c: Regenerate.
 755
 756 2020-01-04  Alan Modra  <amodra@gmail.com>
 757
 758         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 759
 760 2020-01-04  Alan Modra  <amodra@gmail.com>
 761
 762         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 763
 764 2020-01-04  Alan Modra  <amodra@gmail.com>
 765
 766         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 767
 768 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 769
 770         * aarch64-tbl.h (aarch64_opcode_table): Use
 771         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 772
 773 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 774
 775         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 776         forms of SUDOT and USDOT.
 777
 778 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 779
 780         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 781         uzip{1,2}.
 782         * opcodes/aarch64-dis-2.c: Re-generate.
 783
 784 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 785
 786         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 787         FMMLA encoding.
 788         * opcodes/aarch64-dis-2.c: Re-generate.
 789
 790 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 791
 792         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 793
 794 2020-01-01  Alan Modra  <amodra@gmail.com>
 795
 796         Update year range in copyright notice of all files.
 797
 798 For older changes see ChangeLog-2019
 799 \f
 800 Copyright (C) 2020 Free Software Foundation, Inc.
 801
 802 Copying and distribution of this file, with or without modification,
 803 are permitted in any medium without royalty provided the copyright
 804 notice and this notice are preserved.
 805
 806 Local Variables:
 807 mode: change-log
 808 left-margin: 8
 809 fill-column: 74
 810 version-control: never
 811 End: