opcodes/ChangeLog

   1 2018-07-23  Alan Modra  <amodra@gmail.com>
   2
   3         PR 23419
   4         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
   5         opcode variants for mtspr/mfspr encodings.
   6
   7 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
   8             Maciej W. Rozycki  <macro@mips.com>
   9
  10         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
  11         loongson3a descriptors.
  12         (parse_mips_ase_option): Handle -M loongson-mmi option.
  13         (print_mips_disassembler_options): Document -M loongson-mmi.
  14         * mips-opc.c (LMMI): New macro.
  15         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
  16         instructions.
  17
  18 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  19
  20         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  21         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
  22         IgnoreSize and [XYZ]MMword where applicable.
  23         * i386-tbl.h: Re-generate.
  24
  25 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
  28         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
  29         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
  30         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
  31         * i386-tbl.h: Re-generate.
  32
  33 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  34
  35         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
  36         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
  37         VPCLMULQDQ templates into their respective AVX512VL counterparts
  38         where possible, using Disp8ShiftVL and CheckRegSize instead of
  39         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
  40         * i386-tbl.h: Re-generate.
  41
  42 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.tbl: Fold AVX512DQ templates into their respective
  45         AVX512VL counterparts where possible, using Disp8ShiftVL and
  46         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  47         IgnoreSize) as appropriate.
  48         * i386-tbl.h: Re-generate.
  49
  50 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-opc.tbl: Fold AVX512BW templates into their respective
  53         AVX512VL counterparts where possible, using Disp8ShiftVL and
  54         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  55         IgnoreSize) as appropriate.
  56         * i386-tbl.h: Re-generate.
  57
  58 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-opc.tbl: Fold AVX512CD templates into their respective
  61         AVX512VL counterparts where possible, using Disp8ShiftVL and
  62         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  63         IgnoreSize) as appropriate.
  64         * i386-tbl.h: Re-generate.
  65
  66 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  67
  68         * i386-opc.h (DISP8_SHIFT_VL): New.
  69         * i386-opc.tbl (Disp8ShiftVL):  Define.
  70         (various): Fold AVX512VL templates into their respective
  71         AVX512F counterparts where possible, using Disp8ShiftVL and
  72         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  73         IgnoreSize) as appropriate.
  74         * i386-tbl.h: Re-generate.
  75
  76 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  77
  78         * Makefile.am: Change dependencies and rule for
  79         $(srcdir)/i386-init.h.
  80         * Makefile.in: Re-generate.
  81         * i386-gen.c (process_i386_opcodes): New local variable
  82         "marker". Drop opening of input file. Recognize marker and line
  83         number directives.
  84         * i386-opc.tbl (OPCODE_I386_H): Define.
  85         (i386-opc.h): Include it.
  86         (None): Undefine.
  87
  88 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  89
  90         PR gas/23418
  91         * i386-opc.h (Byte): Update comments.
  92         (Word): Likewise.
  93         (Dword): Likewise.
  94         (Fword): Likewise.
  95         (Qword): Likewise.
  96         (Tbyte): Likewise.
  97         (Xmmword): Likewise.
  98         (Ymmword): Likewise.
  99         (Zmmword): Likewise.
 100         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 101         vcvttps2uqq.
 102         * i386-tbl.h: Regenerated.
 103
 104 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 105
 106         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 107         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 108         * aarch64-asm-2.c: Regenerate.
 109         * aarch64-dis-2.c: Regenerate.
 110         * aarch64-opc-2.c: Regenerate.
 111
 112 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 113
 114         PR binutils/23192
 115         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 116         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 117         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 118         sqdmulh, sqrdmulh): Use Em16.
 119
 120 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 121
 122         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 123         csdb together with them.
 124         (thumb32_opcodes): Likewise.
 125
 126 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 127
 128         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 129         requiring 32-bit registers as operands 2 and 3. Improve
 130         comments.
 131         (mwait, mwaitx): Fold templates. Improve comments.
 132         OPERAND_TYPE_INOUTPORTREG.
 133         * i386-tbl.h: Re-generate.
 134
 135 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-gen.c (operand_type_init): Remove
 138         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 139         OPERAND_TYPE_INOUTPORTREG.
 140         * i386-init.h: Re-generate.
 141
 142 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 143
 144         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 145         (wrssq, wrussq): Add Qword.
 146         * i386-tbl.h: Re-generate.
 147
 148 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.h: Rename OTMax to OTNum.
 151         (OTNumOfUints): Adjust calculation.
 152         (OTUnused): Directly alias to OTNum.
 153
 154 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 155
 156         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 157         `reg_xys'.
 158         (lea_reg_xys): Likewise.
 159         (print_insn_loop_primitive): Rename `reg' local variable to
 160         `reg_dxy'.
 161
 162 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 163
 164         PR binutils/23242
 165         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 166
 167 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 168
 169         PR binutils/23369
 170         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 171         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 172
 173 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 174
 175         PR tdep/8282
 176         * mips-dis.c (mips_option_arg_t): New enumeration.
 177         (mips_options): New variable.
 178         (disassembler_options_mips): New function.
 179         (print_mips_disassembler_options): Reimplement in terms of
 180         `disassembler_options_mips'.
 181         * arm-dis.c (disassembler_options_arm): Adapt to using the
 182         `disasm_options_and_args_t' structure.
 183         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 184         * s390-dis.c (disassembler_options_s390): Likewise.
 185
 186 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 187
 188         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 189         expected result.
 190         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 191         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 192         * testsuite/ld-arm/tls-longplt.d: Likewise.
 193
 194 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 195
 196         PR binutils/23192
 197         * aarch64-asm-2.c: Regenerate.
 198         * aarch64-dis-2.c: Likewise.
 199         * aarch64-opc-2.c: Likewise.
 200         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 201         * aarch64-opc.c (operand_general_constraint_met_p,
 202         aarch64_print_operand): Likewise.
 203         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 204         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 205         fmlal2, fmlsl2.
 206         (AARCH64_OPERANDS): Add Em2.
 207
 208 2018-06-26  Nick Clifton  <nickc@redhat.com>
 209
 210         * po/uk.po: Updated Ukranian translation.
 211         * po/de.po: Updated German translation.
 212         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 213
 214 2018-06-26  Nick Clifton  <nickc@redhat.com>
 215
 216         * nfp-dis.c: Fix spelling mistake.
 217
 218 2018-06-24  Nick Clifton  <nickc@redhat.com>
 219
 220         * configure: Regenerate.
 221         * po/opcodes.pot: Regenerate.
 222
 223 2018-06-24  Nick Clifton  <nickc@redhat.com>
 224
 225         2.31 branch created.
 226
 227 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 228
 229         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 230         * aarch64-asm-2.c: Regenerate.
 231         * aarch64-dis-2.c: Likewise.
 232
 233 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 234
 235         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 236         `-M ginv' option description.
 237
 238 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 239
 240         PR gas/23305
 241         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 242         la and lla.
 243
 244 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 245
 246         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 247         * configure.ac: Remove AC_PREREQ.
 248         * Makefile.in: Re-generate.
 249         * aclocal.m4: Re-generate.
 250         * configure: Re-generate.
 251
 252 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 253
 254         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 255         mips64r6 descriptors.
 256         (parse_mips_ase_option): Handle -Mginv option.
 257         (print_mips_disassembler_options): Document -Mginv.
 258         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 259         (GINV): New macro.
 260         (mips_opcodes): Define ginvi and ginvt.
 261
 262 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 263             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 264
 265         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 266         * mips-opc.c (CRC, CRC64): New macros.
 267         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 268         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 269         crc32cd for CRC64.
 270
 271 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 272
 273         PR 20319
 274         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 275         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 276
 277 2018-06-06  Alan Modra  <amodra@gmail.com>
 278
 279         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 280         setjmp.  Move init for some other vars later too.
 281
 282 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 283
 284         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 285         (dis_private): Add new fields for property section tracking.
 286         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 287         (xtensa_instruction_fits): New functions.
 288         (fetch_data): Bump minimal fetch size to 4.
 289         (print_insn_xtensa): Make struct dis_private static.
 290         Load and prepare property table on section change.
 291         Don't disassemble literals. Don't disassemble instructions that
 292         cross property table boundaries.
 293
 294 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 295
 296         * configure: Regenerated.
 297
 298 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 301         * i386-tbl.h: Re-generate.
 302
 303 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 304
 305         * i386-opc.tbl (sldt, str): Add NoRex64.
 306         * i386-tbl.h: Re-generate.
 307
 308 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-opc.tbl (invpcid): Add Oword.
 311         * i386-tbl.h: Re-generate.
 312
 313 2018-06-01  Alan Modra  <amodra@gmail.com>
 314
 315         * sysdep.h (_bfd_error_handler): Don't declare.
 316         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 317         * rl78-decode.opc: Likewise.
 318         * msp430-decode.c: Regenerate.
 319         * rl78-decode.c: Regenerate.
 320
 321 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 322
 323         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 324         * i386-init.h : Regenerated.
 325
 326 2018-05-25  Alan Modra  <amodra@gmail.com>
 327
 328         * Makefile.in: Regenerate.
 329         * po/POTFILES.in: Regenerate.
 330
 331 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 332
 333         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 334         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 335         (insert_bab, extract_bab, insert_btab, extract_btab,
 336         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 337         (BAT, BBA VBA RBS XB6S): Delete macros.
 338         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 339         (BB, BD, RBX, XC6): Update for new macros.
 340         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 341         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 342         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 343         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 344
 345 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 346
 347         * Makefile.am: Add support for s12z architecture.
 348         * configure.ac: Likewise.
 349         * disassemble.c: Likewise.
 350         * disassemble.h: Likewise.
 351         * Makefile.in: Regenerate.
 352         * configure: Regenerate.
 353         * s12z-dis.c: New file.
 354         * s12z.h: New file.
 355
 356 2018-05-18  Alan Modra  <amodra@gmail.com>
 357
 358         * nfp-dis.c: Don't #include libbfd.h.
 359         (init_nfp3200_priv): Use bfd_get_section_contents.
 360         (nit_nfp6000_mecsr_sec): Likewise.
 361
 362 2018-05-17  Nick Clifton  <nickc@redhat.com>
 363
 364         * po/zh_CN.po: Updated simplified Chinese translation.
 365
 366 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 367
 368         PR binutils/23109
 369         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 370         * aarch64-dis-2.c: Regenerate.
 371
 372 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 373
 374         PR binutils/21446
 375         * aarch64-asm.c (opintl.h): Include.
 376         (aarch64_ins_sysreg): Enforce read/write constraints.
 377         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 378         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 379         (F_REG_READ, F_REG_WRITE): New.
 380         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 381         AARCH64_OPND_SYSREG.
 382         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 383         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 384         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 385         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 386         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 387         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 388         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 389         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 390         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 391         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 392         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 393         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 394         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 395         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 396         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 397         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 398         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 399
 400 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 401
 402         PR binutils/21446
 403         * aarch64-dis.c (no_notes: New.
 404         (parse_aarch64_dis_option): Support notes.
 405         (aarch64_decode_insn, print_operands): Likewise.
 406         (print_aarch64_disassembler_options): Document notes.
 407         * aarch64-opc.c (aarch64_print_operand): Support notes.
 408
 409 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 410
 411         PR binutils/21446
 412         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 413         and take error struct.
 414         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 415         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 416         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 417         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 418         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 419         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 420         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 421         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 422         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 423         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 424         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 425         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 426         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 427         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 428         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 429         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 430         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 431         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 432         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 433         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 434         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 435         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 436         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 437         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 438         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 439         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 440         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 441         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 442         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 443         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 444         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 445         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 446         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 447         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 448         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 449         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 450         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 451         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 452         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 453         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 454         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 455         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 456         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 457         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 458         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 459         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 460         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 461         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 462         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 463         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 464         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 465         (determine_disassembling_preference, aarch64_decode_insn,
 466         print_insn_aarch64_word, print_insn_data): Take errors struct.
 467         (print_insn_aarch64): Use errors.
 468         * aarch64-asm-2.c: Regenerate.
 469         * aarch64-dis-2.c: Regenerate.
 470         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 471         boolean in aarch64_insert_operan.
 472         (print_operand_extractor): Likewise.
 473         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 474
 475 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 476
 477         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 478
 479 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 480
 481         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 482
 483 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 484
 485         * cr16-opc.c (cr16_instruction): Comment typo fix.
 486         * hppa-dis.c (print_insn_hppa): Likewise.
 487
 488 2018-05-08  Jim Wilson  <jimw@sifive.com>
 489
 490         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 491         (match_c_slli64, match_srxi_as_c_srxi): New.
 492         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 493         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 494         <c.slli, c.srli, c.srai>: Use match_s_slli.
 495         <c.slli64, c.srli64, c.srai64>: New.
 496
 497 2018-05-08  Alan Modra  <amodra@gmail.com>
 498
 499         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 500         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 501         partition opcode space for index lookup.
 502
 503 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 504
 505         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 506         <insn_length>: ...with this.  Update usage.
 507         Remove duplicate call to *info->memory_error_func.
 508
 509 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 510             H.J. Lu  <hongjiu.lu@intel.com>
 511
 512         * i386-dis.c (Gva): New.
 513         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 514         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 515         (prefix_table): New instructions (see prefix above).
 516         (mod_table): New instructions (see prefix above).
 517         (OP_G): Handle va_mode.
 518         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 519         CPU_MOVDIR64B_FLAGS.
 520         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 521         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 522         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 523         * i386-opc.tbl: Add movidir{i,64b}.
 524         * i386-init.h: Regenerated.
 525         * i386-tbl.h: Likewise.
 526
 527 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 530         AddrPrefixOpReg.
 531         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 532         (AddrPrefixOpReg): This.
 533         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 534         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 535
 536 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 537
 538         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 539         (vle_num_opcodes): Likewise.
 540         (spe2_num_opcodes): Likewise.
 541         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 542         initialization loop.
 543         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 544         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 545         only once.
 546
 547 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 548
 549         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 550
 551 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 552
 553         Makefile.am: Added nfp-dis.c.
 554         configure.ac: Added bfd_nfp_arch.
 555         disassemble.h: Added print_insn_nfp prototype.
 556         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 557         nfp-dis.c: New, for NFP support.
 558         po/POTFILES.in: Added nfp-dis.c to the list.
 559         Makefile.in: Regenerate.
 560         configure: Regenerate.
 561
 562 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 565         templates into their base ones.
 566         * i386-tlb.h: Re-generate.
 567
 568 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 569
 570         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 571         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 572         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 573         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 574         * i386-init.h: Re-generate.
 575
 576 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 577
 578         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 579         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 580         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 581         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 582         comment.
 583         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 584         and CpuRegMask.
 585         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 586         CpuRegMask: Delete.
 587         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 588         cpuregzmm, and cpuregmask.
 589         * i386-init.h: Re-generate.
 590         * i386-tbl.h: Re-generate.
 591
 592 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 595         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 596         * i386-init.h: Re-generate.
 597
 598 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-gen.c (VexImmExt): Delete.
 601         * i386-opc.h (VexImmExt, veximmext): Delete.
 602         * i386-opc.tbl: Drop all VexImmExt uses.
 603         * i386-tlb.h: Re-generate.
 604
 605 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 606
 607         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 608         register-only forms.
 609         * i386-tlb.h: Re-generate.
 610
 611 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 612
 613         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 614
 615 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 616
 617         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 618         PREFIX_0F1C.
 619         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 620         (cpu_flags): Add CpuCLDEMOTE.
 621         * i386-init.h: Regenerate.
 622         * i386-opc.h (enum): Add CpuCLDEMOTE,
 623         (i386_cpu_flags): Add cpucldemote.
 624         * i386-opc.tbl: Add cldemote.
 625         * i386-tbl.h: Regenerate.
 626
 627 2018-04-16  Alan Modra  <amodra@gmail.com>
 628
 629         * Makefile.am: Remove sh5 and sh64 support.
 630         * configure.ac: Likewise.
 631         * disassemble.c: Likewise.
 632         * disassemble.h: Likewise.
 633         * sh-dis.c: Likewise.
 634         * sh64-dis.c: Delete.
 635         * sh64-opc.c: Delete.
 636         * sh64-opc.h: Delete.
 637         * Makefile.in: Regenerate.
 638         * configure: Regenerate.
 639         * po/POTFILES.in: Regenerate.
 640
 641 2018-04-16  Alan Modra  <amodra@gmail.com>
 642
 643         * Makefile.am: Remove w65 support.
 644         * configure.ac: Likewise.
 645         * disassemble.c: Likewise.
 646         * disassemble.h: Likewise.
 647         * w65-dis.c: Delete.
 648         * w65-opc.h: Delete.
 649         * Makefile.in: Regenerate.
 650         * configure: Regenerate.
 651         * po/POTFILES.in: Regenerate.
 652
 653 2018-04-16  Alan Modra  <amodra@gmail.com>
 654
 655         * configure.ac: Remove we32k support.
 656         * configure: Regenerate.
 657
 658 2018-04-16  Alan Modra  <amodra@gmail.com>
 659
 660         * Makefile.am: Remove m88k support.
 661         * configure.ac: Likewise.
 662         * disassemble.c: Likewise.
 663         * disassemble.h: Likewise.
 664         * m88k-dis.c: Delete.
 665         * Makefile.in: Regenerate.
 666         * configure: Regenerate.
 667         * po/POTFILES.in: Regenerate.
 668
 669 2018-04-16  Alan Modra  <amodra@gmail.com>
 670
 671         * Makefile.am: Remove i370 support.
 672         * configure.ac: Likewise.
 673         * disassemble.c: Likewise.
 674         * disassemble.h: Likewise.
 675         * i370-dis.c: Delete.
 676         * i370-opc.c: Delete.
 677         * Makefile.in: Regenerate.
 678         * configure: Regenerate.
 679         * po/POTFILES.in: Regenerate.
 680
 681 2018-04-16  Alan Modra  <amodra@gmail.com>
 682
 683         * Makefile.am: Remove h8500 support.
 684         * configure.ac: Likewise.
 685         * disassemble.c: Likewise.
 686         * disassemble.h: Likewise.
 687         * h8500-dis.c: Delete.
 688         * h8500-opc.h: Delete.
 689         * Makefile.in: Regenerate.
 690         * configure: Regenerate.
 691         * po/POTFILES.in: Regenerate.
 692
 693 2018-04-16  Alan Modra  <amodra@gmail.com>
 694
 695         * configure.ac: Remove tahoe support.
 696         * configure: Regenerate.
 697
 698 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 699
 700         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 701         umwait.
 702         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 703         64-bit mode.
 704         * i386-tbl.h: Regenerated.
 705
 706 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 707
 708         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 709         PREFIX_MOD_1_0FAE_REG_6.
 710         (va_mode): New.
 711         (OP_E_register): Use va_mode.
 712         * i386-dis-evex.h (prefix_table):
 713         New instructions (see prefixes above).
 714         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 715         (cpu_flags): Likewise.
 716         * i386-opc.h (enum): Likewise.
 717         (i386_cpu_flags): Likewise.
 718         * i386-opc.tbl: Add umonitor, umwait, tpause.
 719         * i386-init.h: Regenerate.
 720         * i386-tbl.h: Likewise.
 721
 722 2018-04-11  Alan Modra  <amodra@gmail.com>
 723
 724         * opcodes/i860-dis.c: Delete.
 725         * opcodes/i960-dis.c: Delete.
 726         * Makefile.am: Remove i860 and i960 support.
 727         * configure.ac: Likewise.
 728         * disassemble.c: Likewise.
 729         * disassemble.h: Likewise.
 730         * Makefile.in: Regenerate.
 731         * configure: Regenerate.
 732         * po/POTFILES.in: Regenerate.
 733
 734 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 735
 736         PR binutils/23025
 737         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 738         to 0.
 739         (print_insn): Clear vex instead of vex.evex.
 740
 741 2018-04-04  Nick Clifton  <nickc@redhat.com>
 742
 743         * po/es.po: Updated Spanish translation.
 744
 745 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 746
 747         * i386-gen.c (opcode_modifiers): Delete VecESize.
 748         * i386-opc.h (VecESize): Delete.
 749         (struct i386_opcode_modifier): Delete vecesize.
 750         * i386-opc.tbl: Drop VecESize.
 751         * i386-tlb.h: Re-generate.
 752
 753 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 754
 755         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 756         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 757         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 758         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 759         * i386-tlb.h: Re-generate.
 760
 761 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 764         Fold AVX512 forms
 765         * i386-tlb.h: Re-generate.
 766
 767 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 768
 769         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 770         (vex_len_table): Drop Y for vcvt*2si.
 771         (putop): Replace plain 'Y' handling by abort().
 772
 773 2018-03-28  Nick Clifton  <nickc@redhat.com>
 774
 775         PR 22988
 776         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 777         instructions with only a base address register.
 778         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 779         handle AARHC64_OPND_SVE_ADDR_R.
 780         (aarch64_print_operand): Likewise.
 781         * aarch64-asm-2.c: Regenerate.
 782         * aarch64_dis-2.c: Regenerate.
 783         * aarch64-opc-2.c: Regenerate.
 784
 785 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 786
 787         * i386-opc.tbl: Drop VecESize from register only insn forms and
 788         memory forms not allowing broadcast.
 789         * i386-tlb.h: Re-generate.
 790
 791 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 792
 793         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 794         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 795         sha256*): Drop Disp<N>.
 796
 797 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 798
 799         * i386-dis.c (EbndS, bnd_swap_mode): New.
 800         (prefix_table): Use EbndS.
 801         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 802         * i386-opc.tbl (bndmov): Move misplaced Load.
 803         * i386-tlb.h: Re-generate.
 804
 805 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 808         templates allowing memory operands and folded ones for register
 809         only flavors.
 810         * i386-tlb.h: Re-generate.
 811
 812 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 815         256-bit templates. Drop redundant leftover Disp<N>.
 816         * i386-tlb.h: Re-generate.
 817
 818 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 819
 820         * riscv-opc.c (riscv_insn_types): New.
 821
 822 2018-03-13  Nick Clifton  <nickc@redhat.com>
 823
 824         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 825
 826 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 827
 828         * i386-opc.tbl: Add Optimize to clr.
 829         * i386-tbl.h: Regenerated.
 830
 831 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 832
 833         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 834         * i386-opc.h (OldGcc): Removed.
 835         (i386_opcode_modifier): Remove oldgcc.
 836         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 837         instructions for old (<= 2.8.1) versions of gcc.
 838         * i386-tbl.h: Regenerated.
 839
 840 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 841
 842         * i386-opc.h (EVEXDYN): New.
 843         * i386-opc.tbl: Fold various AVX512VL templates.
 844         * i386-tlb.h: Re-generate.
 845
 846 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 847
 848         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 849         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 850         vpexpandd, vpexpandq): Fold AFX512VF templates.
 851         * i386-tlb.h: Re-generate.
 852
 853 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 854
 855         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 856         Fold 128- and 256-bit VEX-encoded templates.
 857         * i386-tlb.h: Re-generate.
 858
 859 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 860
 861         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 862         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 863         vpexpandd, vpexpandq): Fold AVX512F templates.
 864         * i386-tlb.h: Re-generate.
 865
 866 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 869         64-bit templates. Drop Disp<N>.
 870         * i386-tlb.h: Re-generate.
 871
 872 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 875         and 256-bit templates.
 876         * i386-tlb.h: Re-generate.
 877
 878 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 879
 880         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 881         * i386-tlb.h: Re-generate.
 882
 883 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 886         Drop NoAVX.
 887         * i386-tlb.h: Re-generate.
 888
 889 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 892         * i386-tlb.h: Re-generate.
 893
 894 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 895
 896         * i386-gen.c (opcode_modifiers): Delete FloatD.
 897         * i386-opc.h (FloatD): Delete.
 898         (struct i386_opcode_modifier): Delete floatd.
 899         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 900         FloatD by D.
 901         * i386-tlb.h: Re-generate.
 902
 903 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 904
 905         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 906
 907 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 910         * i386-tlb.h: Re-generate.
 911
 912 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 913
 914         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 915         forms.
 916         * i386-tlb.h: Re-generate.
 917
 918 2018-03-07  Alan Modra  <amodra@gmail.com>
 919
 920         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 921         bfd_arch_rs6000.
 922         * disassemble.h (print_insn_rs6000): Delete.
 923         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 924         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 925         (print_insn_rs6000): Delete.
 926
 927 2018-03-03  Alan Modra  <amodra@gmail.com>
 928
 929         * sysdep.h (opcodes_error_handler): Define.
 930         (_bfd_error_handler): Declare.
 931         * Makefile.am: Remove stray #.
 932         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 933         EDIT" comment.
 934         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 935         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 936         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 937         opcodes_error_handler to print errors.  Standardize error messages.
 938         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 939         and include opintl.h.
 940         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 941         * i386-gen.c: Standardize error messages.
 942         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 943         * Makefile.in: Regenerate.
 944         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 945         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 946         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 947         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 948         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 949         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 950         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 951         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 952         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 953         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 954         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 955         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 956         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 957
 958 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 959
 960         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 961         vpsub[bwdq] instructions.
 962         * i386-tbl.h: Regenerated.
 963
 964 2018-03-01  Alan Modra  <amodra@gmail.com>
 965
 966         * configure.ac (ALL_LINGUAS): Sort.
 967         * configure: Regenerate.
 968
 969 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 970
 971         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 972         macro by assignements.
 973
 974 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 975
 976         PR gas/22871
 977         * i386-gen.c (opcode_modifiers): Add Optimize.
 978         * i386-opc.h (Optimize): New enum.
 979         (i386_opcode_modifier): Add optimize.
 980         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 981         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 982         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 983         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 984         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 985         vpxord and vpxorq.
 986         * i386-tbl.h: Regenerated.
 987
 988 2018-02-26  Alan Modra  <amodra@gmail.com>
 989
 990         * crx-dis.c (getregliststring): Allocate a large enough buffer
 991         to silence false positive gcc8 warning.
 992
 993 2018-02-22  Shea Levy <shea@shealevy.com>
 994
 995         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 996
 997 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 998
 999         * i386-opc.tbl: Add {rex},
1000         * i386-tbl.h: Regenerated.
1001
1002 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1003
1004         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1005         (mips16_opcodes): Replace `M' with `m' for "restore".
1006
1007 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1008
1009         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1010
1011 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1012
1013         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1014         variable to `function_index'.
1015
1016 2018-02-13  Nick Clifton  <nickc@redhat.com>
1017
1018         PR 22823
1019         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1020         about truncation of printing.
1021
1022 2018-02-12  Henry Wong <henry@stuffedcow.net>
1023
1024         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1025
1026 2018-02-05  Nick Clifton  <nickc@redhat.com>
1027
1028         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1029
1030 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1031
1032         * i386-dis.c (enum): Add pconfig.
1033         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1034         (cpu_flags): Add CpuPCONFIG.
1035         * i386-opc.h (enum): Add CpuPCONFIG.
1036         (i386_cpu_flags): Add cpupconfig.
1037         * i386-opc.tbl: Add PCONFIG instruction.
1038         * i386-init.h: Regenerate.
1039         * i386-tbl.h: Likewise.
1040
1041 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1042
1043         * i386-dis.c (enum): Add PREFIX_0F09.
1044         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1045         (cpu_flags): Add CpuWBNOINVD.
1046         * i386-opc.h (enum): Add CpuWBNOINVD.
1047         (i386_cpu_flags): Add cpuwbnoinvd.
1048         * i386-opc.tbl: Add WBNOINVD instruction.
1049         * i386-init.h: Regenerate.
1050         * i386-tbl.h: Likewise.
1051
1052 2018-01-17  Jim Wilson  <jimw@sifive.com>
1053
1054         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1055
1056 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1057
1058         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1059         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1060         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1061         (cpu_flags): Add CpuIBT, CpuSHSTK.
1062         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1063         (i386_cpu_flags): Add cpuibt, cpushstk.
1064         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1065         * i386-init.h: Regenerate.
1066         * i386-tbl.h: Likewise.
1067
1068 2018-01-16  Nick Clifton  <nickc@redhat.com>
1069
1070         * po/pt_BR.po: Updated Brazilian Portugese translation.
1071         * po/de.po: Updated German translation.
1072
1073 2018-01-15  Jim Wilson  <jimw@sifive.com>
1074
1075         * riscv-opc.c (match_c_nop): New.
1076         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1077
1078 2018-01-15  Nick Clifton  <nickc@redhat.com>
1079
1080         * po/uk.po: Updated Ukranian translation.
1081
1082 2018-01-13  Nick Clifton  <nickc@redhat.com>
1083
1084         * po/opcodes.pot: Regenerated.
1085
1086 2018-01-13  Nick Clifton  <nickc@redhat.com>
1087
1088         * configure: Regenerate.
1089
1090 2018-01-13  Nick Clifton  <nickc@redhat.com>
1091
1092         2.30 branch created.
1093
1094 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1095
1096         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1097         * i386-tbl.h: Regenerate.
1098
1099 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1100
1101         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1102         * i386-tbl.h: Re-generate.
1103
1104 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1105
1106         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1107         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1108         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1109         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1110         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1111         Disp8MemShift of AVX512VL forms.
1112         * i386-tbl.h: Re-generate.
1113
1114 2018-01-09  Jim Wilson  <jimw@sifive.com>
1115
1116         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1117         then the hi_addr value is zero.
1118
1119 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1120
1121         * arm-dis.c (arm_opcodes): Add csdb.
1122         (thumb32_opcodes): Add csdb.
1123
1124 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1125
1126         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1127         * aarch64-asm-2.c: Regenerate.
1128         * aarch64-dis-2.c: Regenerate.
1129         * aarch64-opc-2.c: Regenerate.
1130
1131 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1132
1133         PR gas/22681
1134         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1135         Remove AVX512 vmovd with 64-bit operands.
1136         * i386-tbl.h: Regenerated.
1137
1138 2018-01-05  Jim Wilson  <jimw@sifive.com>
1139
1140         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1141         jalr.
1142
1143 2018-01-03  Alan Modra  <amodra@gmail.com>
1144
1145         Update year range in copyright notice of all files.
1146
1147 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1148
1149         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1150         and OPERAND_TYPE_REGZMM entries.
1151
1152 For older changes see ChangeLog-2017
1153 \f
1154 Copyright (C) 2018 Free Software Foundation, Inc.
1155
1156 Copying and distribution of this file, with or without modification,
1157 are permitted in any medium without royalty provided the copyright
1158 notice and this notice are preserved.
1159
1160 Local Variables:
1161 mode: change-log
1162 left-margin: 8
1163 fill-column: 74
1164 version-control: never
1165 End: